Estimation of memory cell read thresholds by sampling inside programming level distribution intervals

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent application Ser. No. 12/558,528, filed Sep. 13, 2009, which claims the benefit of U.S. Provisional Patent Application 61/096,806, filed Sep. 14, 2008. The disclosures of these related applications are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates generally to memory devices, and particularly to methods and systems for setting read thresholds in analog memory cell devices.

BACKGROUND OF THE INVENTION

Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. This analog value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into intervals, each interval corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.

Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible programming levels. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible programming levels.

Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.

Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24^th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.

Analog memory cells are typically read by comparing their analog values (storage values) to one or more read thresholds. Several methods for determining read threshold values are known in the art. For example, U.S. Patent Application Publication 2005/0013165, whose disclosure is incorporated herein by reference, describes methods for reading cells of a Flash memory. The cells are read by determining respective adaptive reference voltages for the cells and comparing the cells' threshold voltages to their respective reference voltages. The adaptive reference voltages are determined either from analog measurements of the threshold voltages of the cells' neighbors, or from preliminary estimates of the cells' threshold voltages based on comparisons of the cells' threshold voltages with integral or fractional reference voltages common to all the cells. Cells of a Flash memory are also read by comparing the cells' threshold voltages to integral reference voltages, comparing the threshold voltages of cells that share a common bit pattern to a fractional reference voltage, and adjusting the reference voltages in accordance with the comparisons.

U.S. Patent Application Publication 2006/0028875, whose disclosure is incorporated herein by reference, describes methods for managing a plurality of memory cells. The cells are managed by obtaining values of one or more environmental parameters of the cells and adjusting values of one or more reference voltages of the cells accordingly. Alternatively, a statistic of at least some of the cells, relative to a single reference parameter that corresponds to a control parameter of the cells, is measured, and the value of the reference voltage is adjusted accordingly.

U.S. Pat. No. 5,657,332, whose disclosure is incorporated herein by reference, describes methods for recovering from hard errors in a solid-state memory system. A memory system includes an array of memory cells, each cell capable of having its threshold voltage programmed or erased to an intended level. An error checking scheme is provided for each of a plurality of groups of cells for identifying read errors therein. A read reference level is adjusted before each read operation on the individual group of cells containing read errors, each time the read reference level being displaced a predetermined step from a reference level for normal read, until the error checking means no longer indicates read errors. The drifted threshold voltage of each cell associated with a read error is re-written to its intended level.

U.S. Pat. No. 7,023,735, whose disclosure is incorporated herein by reference, describes methods for reading Flash memory cells, which, in addition to comparing the threshold voltages of Flash cells to integral reference voltages, compare the threshold voltages to fractional reference voltages.

U.S. Patent Application Publication 2007/0091677, whose disclosure is incorporated herein by reference, describes methods, devices and computer readable code for reading data from one or more flash memory cells, and for recovering from read errors. In some embodiments, in the event of an error correction failure by an error detection and correction module, the flash memory cells are re-read at least once using one or more modified reference voltages, until successful error correction may be carried out.

U.S. Pat. No. 6,963,505, whose disclosure is incorporated herein by reference, describes a method, circuit and system for determining a reference voltage. In some embodiments a set of operating reference cells is established to be used in operating cells in a Non-Volatile Memory (NVM) block or array. At least a subset of cells of the NVM block or array may be read using each of two or more sets of test reference cells, where each set of test reference cells may generate or otherwise provide reference voltages at least slightly offset from each other set of test reference cells. For each set of test reference cells used to read at least a subset of the NVM block, a read error rate may be calculated or otherwise determined. A set of test reference cells associated with a relatively low read error rate may be selected as the set of operating reference cells to be used in operating other cells, outside the subset of cells, in the NVM block or array.

SUMMARY OF THE INVENTION

An embodiment of the present invention that is described herein provides a method for data storage. The method includes storing data in a group of analog memory cells by writing into the memory cells in the group respective storage values, which program each of the analog memory cells to a respective programming state selected from a predefined set of programming states, including at least first and second programming states, which are applied respectively to first and second subsets of the memory cells, whereby the storage values held in the memory cells in the first and second subsets are distributed in accordance with respective first and second distributions. A first median of the first distribution is estimated, and a read threshold, which differentiates between the first and second programming states, is calculated based on the estimated first median. The data is retrieved from the analog memory cells in the group by reading the storage values using the calculated read threshold.

In some embodiments, the storage values corresponding to the first programming state lie in a given interval, and estimating the first median includes reading at least some of the storage values using one or more intermediate read thresholds, which are positioned in an interior of the given interval, and assessing the first median responsively to the storage values read using the intermediate read thresholds.

In an embodiment, estimating the first median includes holding an estimated Cumulative Distribution Function (CDF) of the first distribution, and assessing the first median responsively to the storage values read using the intermediate read thresholds and to the estimated CDF. Estimating the first median may include assessing the first median responsively to the estimated CDF and to the storage values read using only a single intermediate read threshold. In a disclosed embodiment, holding the estimated CDF includes holding multiple estimated CDFs, and assessing the first median includes selecting one of the multiple CDFs in accordance with a predefined criterion, and assessing the first median using the selected estimated CDF.

In another embodiment, reading the storage values using the intermediate read thresholds includes counting the storage values falling on a given side of a given one of the intermediate read thresholds, and assessing the first median includes computing the first median based on the counted storage values. In an embodiment, counting the storage values includes incrementing one or more hardware-based counters. In yet another embodiment, reading the storage values using the intermediate read thresholds includes reading the storage values from only a partial subset of the memory cells in the group. In still another embodiment, reading the storage values using the intermediate read thresholds includes reading the storage values using two or more intermediate read thresholds in a single multi-threshold read command.

In some embodiment, estimation of the first median and calculation of the read threshold are invoked responsively to a failure to successfully retrieve the data. In an embodiment, the method further includes calculating a second median of the second distribution, and calculating the read threshold includes estimating the read threshold based on the first and second medians. Estimating the read threshold may include calculating a first estimate of the read threshold based on the first median, calculating a second estimate of the read threshold based on the second median, and combining the first and second estimates. In an embodiment, estimating the first and second medians includes holding predefined nominal values of the first and second medians, and assessing the first and second medians responsively to the nominal values.

There is additionally provided, in accordance with an embodiment of the present invention, apparatus for data storage including an interface and circuitry. The interface is coupled to communicate with a memory that includes multiple analog memory cells. The circuitry is configured to store data in a group of the analog memory cells by writing into the memory cells in the group respective storage values, which program each of the analog memory cells to a respective programming state selected from a predefined set of programming states, including at least first and second programming states, which are applied respectively to first and second subsets of the memory cells, whereby the storage values held in the memory cells in the first and second subsets are distributed in accordance with respective first and second distributions, to estimate a first median of the first distribution, to calculate a read threshold, which differentiates between the first and second programming states, based on the estimated first median, and to retrieve the data from the analog memory cells in the group by reading the storage values using the calculated read threshold.

There is also provided, in accordance with an embodiment of the present invention, apparatus for data storage including a memory and circuitry. The memory includes multiple analog memory cells. The circuitry is configured to store data in a group of the analog memory cells by writing into the memory cells in the group respective storage values, which program each of the analog memory cells to a respective programming state selected from a predefined set of programming states, including at least first and second programming states, which are applied respectively to first and second subsets of the memory cells, whereby the storage values held in the memory cells in the first and second subsets are distributed in accordance with respective first and second distributions, to estimate a first median of the first distribution, to calculate a read threshold, which differentiates between the first and second programming states, based on the estimated first median, and to retrieve the data from the analog memory cells in the group by reading the storage values using the calculated read threshold.

The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention;

FIG. 2 is a graph showing threshold voltage distributions in a group of analog memory cells, in accordance with an embodiment of the present invention;

FIG. 3 is a diagram that schematically illustrates a process for setting a read threshold, in accordance with an embodiment of the present invention;

FIG. 4 is a diagram that schematically illustrates a process for estimating the median of a threshold voltage distribution, in accordance with an embodiment of the present invention; and

FIG. 5 is a flow chart that schematically illustrates a method for setting a read threshold, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Overview

A typical analog memory device stores data by writing respective storage values into a group of analog memory cells. The storage process programs each memory cell to a respective programming level (also referred to as a programming state), which is selected from a predefined set of programming levels. Due to various impairments, the storage values associated with each programming level are not uniform, but rather are distributed in accordance with a certain statistical distribution. This distribution is commonly referred to as a programming level distribution. Data is typically read from the memory cells by comparing the storage values of the cells to one or more read thresholds, which are usually positioned between adjacent programming level distributions. An optimal read threshold between two adjacent programming level distributions is a threshold value that minimizes the number of read errors, or equivalently, maximizes the number of cells whose storage values are read out correctly. Since programming level distributions may vary over time and/or from one cell group to another, and adjacent programming level distributions may overlap at their edges, the optimal positions of read threshold often vary, as well.

Embodiments of the present invention that are described hereinbelow provide improved methods and systems for setting and adjusting read thresholds used in data readout from analog memory cells. In some embodiments, a Memory Signal Processor (MSP) or other memory controller calculates a read threshold that is used for differentiating between two programming levels by (1) estimating the statistical median of at least one of the programming level distributions, and (2) estimating the optimal read threshold position based on the median or medians.

The median of a given programming level distribution is typically estimated by reading at least some of the memory cells using one or more intermediate read thresholds. The intermediate read thresholds are positioned in the interior of the programming level distribution, rather than at the edge of the distribution or between adjacent distributions. Each read operation using an intermediate read threshold indicates the number of storage values falling on either side of the intermediate threshold, and is therefore indicative of the location of the median. Several methods for estimating the distribution median using intermediate read thresholds are described herein.

The intermediate read thresholds are positioned in the interiors of the programming level distributions and not between distributions or at the distribution edges. At these threshold positions, the Cumulative Distribution Function (CDF) of the cell storage values is relatively steep, i.e., has a relatively high derivative. As a result, the read operations using these thresholds are highly accurate in estimating the distribution medians. Consequently, the read threshold calculation processes described herein are highly accurate and reliable, even when based on a small number of read operations.

System Description

FIG. 1 is a block diagram that schematically illustrates a memory system 20, in accordance with an embodiment of the present invention. System 20 can be used in various host systems and devices, such as in computing devices, cellular phones or other communication terminals, removable memory modules (“disk-on-key” devices), Solid State Disks (SSD), digital cameras, music and other media players and/or any other system or device in which data is stored and retrieved.

System 20 comprises a memory device 24, which stores data in a memory cell array 28. The memory array comprises multiple analog memory cells 32. In the context of the present patent application and in the claims, the term “analog memory cell” is used to describe any memory cell that holds a continuous, analog value of a physical parameter, such as an electrical voltage or charge. Array 32 may comprise analog memory cells of any kind, such as, for example, NAND, NOR and Charge Trap Flash (CTF) Flash cells, phase change RAM (PRAM, also referred to as Phase Change Memory—PCM), Nitride Read Only Memory (NROM), Ferroelectric RAM (FRAM), magnetic RAM (MRAM) and/or Dynamic RAM (DRAM) cells.

The charge levels stored in the cells and/or the analog voltages or currents written into and read out of the cells are referred to herein collectively as analog values or storage values. Although the embodiments described herein mainly address threshold voltages, the methods and systems described herein may be used with any other suitable kind of storage values.

System 20 stores data in the analog memory cells by programming the cells to assume respective memory states, which are also referred to as programming levels. The programming levels are selected from a finite set of possible levels, and each level corresponds to a certain nominal storage value. For example, a 2 bit/cell MLC can be programmed to assume one of four possible programming levels by writing one of four possible nominal storage values into the cell.

Memory device 24 comprises a reading/writing (R/W) unit 36, which converts data for storage in the memory device to analog storage values and writes them into memory cells 32. In alternative embodiments, the R/W unit does not perform the conversion, but is provided with voltage samples, i.e., with the storage values for storage in the cells. When reading data out of array 28, R/W unit 36 converts the storage values of memory cells 32 into digital samples having a resolution of one or more bits. Data is typically written to and read from the memory cells in groups that are referred to as pages. In some embodiments, the R/W unit can erase a group of cells 32 by applying one or more negative erasure pulses to the cells.

The storage and retrieval of data in and out of memory device 24 is performed by a Memory Signal Processor (MSP) 40. MSP 40 comprises an interface 44 for communicating with memory device 24, and a signal processing unit 48, which processes the data that is written into and read from device 24. In particular, unit sets and adjusts read thresholds that are used for reading data from memory cells 32, using methods that are described below.

In some embodiments, unit 48 encodes the data for storage using a suitable Error Correction Code (ECC) and decodes the ECC of data retrieved from the memory. In some embodiments, unit 48 produces the storage values for storing in the memory cells and provides these values to R/W unit 36. Alternatively, unit 48 provides the data for storage, and the conversion to storage values is carried out by the R/W unit internally to the memory device. Alternatively to using an MSP, the methods described herein can be carried out by any suitable type of memory controller.

MSP 40 communicates with a host 52, for accepting data for storage in the memory device and for outputting data retrieved from the memory device. MSP 40, and in particular unit 48, may be implemented in hardware. Alternatively, MSP 40 may comprise a microprocessor that runs suitable software, or a combination of hardware and software elements.

The configuration of FIG. 1 is an exemplary system configuration, which is shown purely for the sake of conceptual clarity. Any other suitable memory system configuration can also be used. Elements that are not necessary for understanding the principles of the present invention, such as various interfaces, addressing circuits, timing and sequencing circuits and debugging circuits, have been omitted from the figure for clarity.

In the exemplary system configuration shown in FIG. 1, memory device 24 and MSP 40 are implemented as two separate Integrated Circuits (ICs). In alternative embodiments, however, the memory device and the MSP may be integrated on separate semiconductor dies in a single Multi-Chip Package (MCP) or System on Chip (SoC), and may be interconnected by an internal bus. Further alternatively, some or all of the MSP circuitry may reside on the same die on which the memory array is disposed. Further alternatively, some or all of the functionality of MSP 40 can be implemented in software and carried out by a processor or other element of the host system. In some embodiments, host 44 and MSP 40 may be fabricated on the same die, or on separate dies in the same device package.

In some embodiments, MSP 40 (or other memory controller that carries out the methods described herein) comprises a general-purpose processor, which is programmed in software to carry out the functions described herein. The software may be downloaded to the processor in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and/or stored on tangible media, such as magnetic, optical, or electronic memory.

In an example configuration of array 28, memory cells 32 are arranged in multiple rows and columns, and each memory cell comprises a floating-gate transistor. The gates of the transistors in each row are connected by word lines, and the sources of the transistors in each column are connected by bit lines. The memory array is typically divided into multiple pages, i.e., groups of memory cells that are programmed and read simultaneously. Pages are sometimes sub-divided into sectors. In some embodiments, each page comprises an entire row of the array. In alternative embodiments, each row (word line) can be divided into two or more pages. For example, in some devices each row is divided into two pages, one comprising the odd-order cells and the other comprising the even-order cells. In a typical implementation, a two-bit-per-cell memory device may have four pages per row, a three-bit-per-cell memory device may have six pages per row, and a four-bit-per-cell memory device may have eight pages per row.

Erasing of cells is usually carried out in blocks that contain multiple pages. Typical memory devices may comprise several thousand erasure blocks. In a typical two-bit-per-cell MLC device, each erasure block is on the order of 32 word lines, each comprising several thousand cells. Each word line of such a device is often partitioned into four pages (odd/even order cells, least/most significant bit of the cells). Three-bit-per cell devices having 32 word lines per erasure block would have 192 pages per erasure block, and four-bit-per-cell devices would have 256 pages per block. Alternatively, other block sizes and configurations can also be used.

Some memory devices comprise two or more separate memory cell arrays, often referred to as planes. Since each plane has a certain “busy” period between successive write operations, data can be written alternately to the different planes in order to increase programming speed.

Threshold Voltage Distributions

Analog memory cells are programmed to store data by writing storage values into the cells. Although the programming operation attempts to write nominal storage values that represent the data, the actual storage values found in the cells at the time of readout may deviate from these nominal values. The deviations may be caused by several factors, such as inaccuracies in the programming process, drift due to device aging, cell wearing due to previous programming and erasure cycles, disturb noise caused by memory operations applied to other cells in the array and/or cross-coupling interference from other cells. In practice, the storage values of the cells typically have a certain statistical distribution, which may vary from one cell group to another and/or over the lifetime of the memory cells.

(Although the description that follows refers mainly to threshold voltages of Flash memory cells, this choice is made purely for the sake of conceptual clarity. The methods and systems described herein can be used with any other type of storage value used in any other type of analog memory cells.)

FIG. 2 is a graph showing a distribution (upper plot) and a Cumulative Density Function (CDF, lower plot) of threshold voltages (V_TH) in a group of analog memory cells, in accordance with an embodiment of the present invention. The cell group may comprise, for example, memory cells belonging to a given memory page or word line.

In the present example, the memory cells comprise four-level MLC, with each cell storing two data bits. Curves 60A . . . 60D show the distributions of threshold voltages in the group of cells. Each curve corresponds to a subset of the cells that are programmed to a certain programming level or state. Thus, distributions 60A . . . 60D are also referred to as programming level distributions. Distributions 60A . . . 60D have respective median values denoted M1 . . . M4. In order to read the data from the memory cells, R/W unit 36 compares the storage values of the cells with one or more read thresholds. In the present example, three read thresholds TH1 . . . TH3 are used to differentiate between the four programming levels.

A curve 64 shows the Cumulative Distribution Function (CDF) of the threshold voltages in the group of cells. For a given threshold voltage on the horizontal axis, the CDF gives the relative number of cells whose threshold voltage does not exceed the given threshold voltage. In other words, CDF(x) gives the relative number of memory cells in the group, for which V_TH≦x. Thus, the CDF is zero at the lower edge of the voltage axis, and increases monotonically to reach a value of unity at the upper edge of the voltage axis. Distributions 60A . . . 60D are sometimes referred to as Probability Density Functions (PDFs) of the programming levels, and the CDF can be regarded as the integral of the PDFs along the V_TH axis.

Two regions 65 and 66 are marked on curve 64, in order to demonstrate the advantage of performing read operations using intermediate read thresholds that are positioned inside the programming level distributions. Region 65 is in the vicinity of the median of one of the programming level distribution (in the vicinity of median M3 of distribution 60C). Region 66, on the other hand, is in the boundary region between adjacent distributions (between distributions 60A and 60B. As can be appreciated, the CDF (curve 64) is relatively steep in region 65, and relatively flat in region 66. For a given reading accuracy, a steeper CDF enables higher accuracy in estimating CDF properties, such as distribution medians.

Setting Read Thresholds Using Distribution Medians

Embodiments of the present invention provide improved methods and systems for setting and adjusting the positions of read thresholds, e.g., thresholds TH1 . . . TH3 in FIG. 2. The methods and systems described herein, however, are in no way limited to any specific type of memory cells or a specific number of programming levels. The disclosed techniques can be used to calculate and set read thresholds in any suitable type of analog memory cells having any desired number and arrangement of programming levels. Specifically, these techniques are applicable to SLC as well as MLC configurations.

For a given read threshold used in differentiating between adjacent programming levels, the optimal threshold position is typically in the boundary region that separates the two programming levels. The location of this boundary region (and therefore the optimal read threshold position) may change over time, as explained above. The techniques described herein estimate the distribution medians, and then find the optimal read threshold position using the estimated medians.

FIG. 3 is a diagram that schematically illustrates a process for setting a read threshold, in accordance with an embodiment of the present invention. The figure shows two threshold voltage distributions 68A and 68B, each corresponding to a respective programming level. In some embodiments, MSP 40 estimates the position of a read threshold 76 by estimating respective medians 72A and 72B of distributions 68A and 68B, and then calculating the read threshold position using the two medians.

The median of a statistical distribution is commonly known as a value that is higher than half of the population and lower than the other half of the population. The median of a given threshold voltage distribution is a (not necessarily unique) threshold voltage that is lower than half of the threshold voltages in the distribution, and higher than the other half. In the context of the present patent application and in the claims, the term “estimating a median” is used broadly to describe various calculations that provide information as to the median. For example, processes that estimate the distribution mean, as well as processes that estimate the peak (highest value) of the distribution's Probability Density Function (PDF), are also regarded as types of median estimation.

Thus, in the context of the present patent application and in the claims, the term “median” also covers other central values or measures of central tendency of the distribution, such as the distribution mean (arithmetic, weighted, geometric or any other type of mean), the peak of the distribution PDF (sometimes referred to as the mode of the distribution), or any other suitable measure. Typically, the disclosed techniques do not require that the median be estimated with high accuracy, and rough estimation is often sufficient for determining the optimal read threshold positions.

MSP 40 may estimate the median of a given threshold voltage distribution in various ways. Typically, the MSP finds the median by performing one or more read operations using intermediate read thresholds, which are positioned in the interior of the distribution (rather than in the boundary region between the distributions or at the distribution edges). Each read operation of this sort compares the cell threshold voltages to a given intermediate read threshold. The MSP or R/W unit may count the number of storage values that are below (or above) the intermediate read threshold.

If the intermediate read threshold were positioned at the distribution median, the read operation would indicate that 50% of the read threshold voltages are below the intermediate threshold and 50% are above it. A read result that deviates from 50% indicates that the intermediate threshold is offset from the median. The MSP may estimate the offset and thus determine the median value. In some embodiments, the functional behavior or shape of the CDF or PDF may be known a-priori, and only its position on the V_TH axis is unknown. For example, the cell threshold voltages in a given programming level may be distributed according to a Gaussian distribution having a known variance. Alternatively, the MSP may store an estimated CDF, e.g., in numerical or analytical form. When the CDF shape is known, the MSP can calculate the distribution median using (1) the read results of a single read operation using an intermediate read threshold, and (2) the known shape of the CDF.

(In the present context, the term “estimated CDF” refers to any representation that is indicative of the estimated statistical distribution of the cell threshold voltages, such as CDF, inverse CDF, PDF, histogram or any other suitable representation.)

Alternatively, the MSP may perform two or more read operations, using different intermediate read thresholds that are placed at different positions within the threshold voltage distribution in question. Each read operation produces an additional data point of the programming level CDF. The MSP may thus estimate the distribution median using the results of the multiple read operations. Any suitable number of read operations can be used. A large number of read operations increases the estimation accuracy at the expense of higher computational complexity, and vice versa.

In the embodiments described herein, each intermediate read threshold is placed in the interior of the threshold voltage distribution in question, rather than between distributions. In other words, the threshold voltages of a given programming level distribution may be regarded as occupying a certain interval. The intermediate read thresholds, which are used for estimating the median of that distribution, are positioned in the interior of the interval. In the context of the present patent application and in the claims, the term “interior” is used to describe any position that contains a statistically-significant level of the distribution PDF, as opposed to interval edges. The interior of the interval may be defined, for example, as the positions that are distant from the distribution medians by less than a certain amount. This amount may be quantified, for example, in units of cell number or CDF value. The interior may also be defined as the positions that are within one standard deviation of the distribution mean or median, the positions for which the distribution PDF is larger than a certain value (e.g., 50% of the PDF peak), or using any other suitable definition.

MSP 40 may apply various methods for calculating the optimal read threshold based on the estimated medians. For example, the MSP may calculate the read threshold position based on each estimated median separately, and then combine (e.g., average) the two results. When calculating the average, the MSP may give different weights to the two medians, according to any suitable criterion. Alternatively, the MSP may apply any other suitable method for calculating the optimal read threshold based on the estimated medians.

FIG. 4 is a diagram that schematically illustrates a process for estimating the median of a threshold voltage distribution, in accordance with an embodiment of the present invention. FIG. 4 shows a process of estimating median 72A of threshold voltage distribution 68A. In the present example, the threshold voltages of distribution 68A lie in an interval 80. In order to estimate the distribution median, the MSP initially reads the memory cells using an intermediate threshold 84, which is positioned in the interior of the interval.

The read operation indicates that 43% of the memory cells have threshold voltages that are lower than intermediate threshold 84, and 57% of the memory cells have threshold voltages that are higher than the intermediate threshold. Based on this result (and assuming that the shape of distribution 68A is known) the MSP can estimate an offset 88 between intermediate threshold 84 and media 72A, and thus estimate the median.

Alternatively, as noted above, the MSP may perform two or more read operations, using different intermediate thresholds in the interior of interval 80, and estimate median 72A using the results of these multiple read operations. This technique can be used, for example, when the shape of distribution 68A in unknown a-priori or when the actual CDF differs from the estimated (reference) CDF. Consider, for example, a scenario in which the estimated CDF represents wider programming level distributions than the actual CDF. In such a case, reading the memory cells using two intermediate read thresholds, one on either side of the reference CDF's median. This kind of two-sided estimation would detect and correct the difference between the actual and estimated CDFs, resulting in accurate median estimation.

In some embodiments, system 20 may comprise one or more hardware-based counters, which are incremented so as to count the number of memory cells whose threshold voltages fall on either side of the read threshold. The counters may be part of MSP 40 or of R/W unit 36 in the memory device.

FIG. 5 is a flow chart that schematically illustrates a method for setting a read threshold for reading a group of analog memory cells, in accordance with an embodiment of the present invention. The method begins with MSP 40 instructing R/W unit 36 to read the memory cells in the group using intermediate read thresholds, at an intermediate reading step 90. The MSP positions the intermediate thresholds in the interiors of the threshold voltage distributions. Using the results of the intermediate read operations, the MSP estimates the medians of the threshold voltage distributions, at a media estimation step 94. Based on the estimated medians, the MSP calculates the optimal position of the read threshold used for data readout from the cell group, at a threshold calculation step 98. When reading data from the cell group in question, the MSP sets the read threshold to the position calculated at step 98 above, and reads the threshold voltages of the cells using this read threshold.

The description of FIGS. 3-5 refers to a single read threshold that differentiates between two adjacent programming levels. These embodiments, however, are chosen purely for the sake of conceptual clarity. In alternative embodiments, the techniques described herein can be used to estimate any desired number of read thresholds for differentiating between any desired number of programming levels.

Additional Embodiments and Examples

In the embodiments described above, the read threshold position is estimated based on the medians of two adjacent programming level distributions, one on either side of the read threshold. In alternative embodiments, the MSP may estimate the read threshold position based on a single median of a single programming level distribution. In an example embodiment of this sort, the MSP reads a certain group of memory cells using one or more intermediate read thresholds that are positioned in the interior of a single programming level distribution, as explained above. Using the results of these read operations, the MSP estimates the median of the programming level distribution. Based on the median (e.g., using the known shape of the distribution) the MSP estimates the optimal position of the read threshold. Referring to FIG. 3 above, the MSP may estimate the optimal position of read threshold 76 by calculating only median 72A of distribution 68A (or only median 72B of distribution 68B).

As can be appreciated, the read threshold estimation methods described herein involve additional read operations, which cause an increase in computational complexity. In some embodiments, the MSP attempts to optimize read thresholds only in response to an indication that the currently-used read thresholds are not set properly. For example, the MSP may invoke the methods of FIGS. 3-5 in response to a failure to read the data, e.g., in response to an ECC decoding failure. In MLC configurations, if a particular read threshold in known to be the cause of failure, the MSP may adjust only this read threshold using the disclosed techniques. Alternatively, the MSP may adapt all the read thresholds or any desired subset of the read thresholds.

In some embodiments, the MSP may assume certain nominal positions of the programming level distribution medians. Consider, for example, a group (e.g., word line) of N memory cells, each storing data in M programming levels. Assume also that the MSP stores a nominal CDF, such as curve 64 in FIG. 2 above. Assuming that the data is randomized, the number of memory cells programmed to each programming level is approximately the same and is given by N/M. Under these assumptions, the nominal distribution medians meet the relation:

CDF ⁡ ( median ) = N 2 ⁢ M + N M ⁢ K , K = 0 , 1 , 2 , …

The MSP can determine the nominal media positions from the stored CDF using the relation above. When the actual CDF differs from the stored CDF (e.g., because the data is not distributed uniformly among the different programming levels, or because of various impairments), the actual median locations may deviate from the nominal locations. Nevertheless, the MSP may use the nominal media locations as a first approximate for read threshold calculation. In some embodiments, when applying the methods of FIGS. 3-5, the MSP may position the intermediate read thresholds at the nominal median locations. This choice ensures with high likelihood that the intermediate read thresholds are located well within the interior of the programming level distribution.

When carrying out the methods of FIGS. 3-5, a trade-off exists between threshold setting accuracy (which reflects on read error performance) and computational complexity (which reflects on read threshold computation time). In order to reduce computation time, system 20 may estimate the medians and read thresholds over only a partial subset of the memory cells to be read. For example, in an N-cell word line, the system may estimate the medians and read thresholds over only N/2 or N/4 memory cells. This technique reduces the sampling time in the R/W unit, transfer time over the interface from the memory device to the MSP, and computation time in the MSP.

In some embodiments, the MSP stores multiple different CDFs, and selects the CDF that best matching CDF at any given time. The different stored CDFs may correspond, for example, to different wear levels of the memory cells (e.g., one CDF that best matches fresh memory cells, another CDF that well represents mid-life memory cells, and a third CDF that represents heavily-cycled memory cells). When calculation read thresholds for a given memory cell group, the MSP may choose the appropriate stored CDF based on any suitable criterion, such as the number of programming and erasure cycles the memory cells have gone through, previously-calculated read threshold positions in other cells groups (e.g., other word lines in the same block), or previously-estimated median locations in the same word lines.

In many MLC devices, different bits are read from the memory cells using respective, different read commands that use different sets of read thresholds. For example, in an eight-level MLC configuration, each memory cell stores three bits, which are referred to as a Least Significant Bit (LSB), a Central Significance Bit (CSB) and a Most Significant Bit (MSB). In a common reading scheme, the LSB is read using a read command having a single threshold, the CSB is read using a read command having a set of two thresholds, and the MSB is read using a read command having different set that includes four thresholds. In this example, the CSB and MSB read commands apply multiple read thresholds in a single read operation, and are therefore referred to herein as multi-threshold commands. Some aspects of reading memory cells using multi-threshold read commands are addressed, for example, in U.S. Patent Application Publication 2009/0106485, which is assigned to the assignee of the present patent application and whose disclosure is incorporated herein by reference.

In some embodiments, the MSP may read the memory cells using multiple intermediate read thresholds simultaneously by using the above-mentioned multi-threshold read commands. For example, in an eight-level MLC device, the MSP may sample four programming level distributions using a single MSB read command, which uses four read thresholds. This technique provides multiple CDF data points at a relatively short read time. Typically, however, in order to interpret the read results of the MSB read command, the MSP first needs to read the LSB and CSB bits of the cells (or otherwise obtain the LSB and CSB data).

Certain additional aspects of calculating read thresholds are addressed, for example, in PCT International Publications WO 2008/053472 and WO 2008/111058, which are assigned to the assignee of the present patent application and whose disclosures are incorporated herein by reference.

It will be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.