Disk drive measuring reader/writer gap by measuring fractional clock cycle over disk radius

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to provisional U.S. Patent Application Ser. No. 61/913,168, filed on Dec. 6, 2013, which is hereby incorporated by reference in its entirety.

BACKGROUND

Disk drives comprise a disk and a head connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. The disk comprises a plurality of radially spaced, concentric tracks for recording user data sectors and servo sectors. The servo sectors comprise head positioning information (e.g., a track address) which is read by the head and processed by a servo control system to control the actuator arm as it seeks from track to track.

FIG. 1 shows a prior art disk format 2 as comprising a number of servo tracks 4 defined by servo sectors 6₀-6_N recorded around the circumference of each servo track. Each servo sector 6_i comprises a preamble 8 for storing a periodic pattern, which allows proper gain adjustment and timing synchronization of the read signal, and a sync mark 10 for storing a special pattern used to symbol synchronize to a servo data field 12. The servo data field 12 stores coarse head positioning information, such as a servo track address, used to position the head over a target data track during a seek operation. Each servo sector 6_i further comprises groups of servo bursts 14 (e.g., N and Q servo bursts), which are recorded with a predetermined phase relative to one another and relative to the servo track centerlines. The phase based servo bursts 14 provide fine head position information used for centerline tracking while accessing a data track during write/read operations. A position error signal (PES) is generated by reading the servo bursts 14, wherein the PES represents a measured position of the head relative to a centerline of a target servo track. A servo controller processes the PES to generate a control signal applied to a head actuator (e.g., a voice coil motor) in order to actuate the head radially over the disk in a direction that reduces the PES.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a prior art disk format comprising a plurality of servo tracks defined by servo sectors.

FIG. 2A shows a disk drive according to an embodiment comprising a disk and head actuated radially over the disk.

FIG. 2B shows an embodiment of the head comprising a read element separated from a write element by a reader/writer gap.

FIG. 2C is a flow diagram according to an embodiment wherein a fraction of a disk-locked clock cycle is measured at a first plurality of radial locations in order to estimate a second number of radial locations wherein the fraction equals a full clock cycle.

FIG. 2D illustrates a fraction of a disk-locked clock cycle relative to the reader/writer gap according to an embodiment.

FIGS. 3A and 3B illustrate an embodiment for measuring an integer number of disk-locked clock cycles relative to the reader/writer gap.

FIG. 4 illustrates an embodiment for measuring the fraction of the disk-locked clock cycle relative to the reader/writer gap.

FIG. 5 shows an example embodiment where the second number of radial locations is estimated at the locations where the fraction equals a full clock cycle.

FIG. 6 is a flow diagram according to an embodiment wherein the reader/writer gap in disk-locked clock cycles is estimated for a target track relative to a reference track.

FIG. 7 illustrates an example for estimating the reader/writer gap in disk-locked clock cycles for a target track relative to a reference track.

FIG. 8 shows the reader/writer gap estimates over the radius of the disk according to an embodiment.

DETAILED DESCRIPTION

FIG. 2A shows a disk drive according to an embodiment comprising a disk 16, and a head 18 actuated radially over the disk 16, wherein the head 18 comprises a read element 20 separated from a write element 22 by a reader/writer gap (FIG. 2B). The disk drive further comprises control circuitry 24 configured to execute the flow diagram of FIG. 2C, wherein a disk-locked clock 28 is synchronized to a rotation of the disk (block 26), the disk-locked clock 28 comprising a plurality of clock cycles, and the reader/writer gap spans a first number of the clock cycles comprising an integer of the clock cycles plus a fraction of one of the clock cycles (FIG. 2D). The fraction of one of the clock cycles is measured when the head is positioned at a first plurality of radial locations across the disk (block 30), and a second plurality of radial locations is estimated where the fraction substantially equals a full one of the clock cycles (block 32).

In the embodiment of FIG. 2A, a plurality of concentric servo tracks 34 are defined by embedded servo sectors 36₀-36_N, wherein a plurality of concentric data tracks are defined relative to the servo tracks at the same or different radial density. The control circuitry 24 processes a read signal 38 emanating from the head 18 to demodulate the servo sectors and generate a position error signal (PES) representing an error between the actual position of the head and a target position relative to a target track. The control circuitry 24 filters the PES using a suitable compensation filter to generate a control signal 40 applied to a voice coil motor (VCM) 42 which rotates an actuator arm 44 about a pivot in order to actuate the head 18 radially over the disk 16 in a direction that reduces the PES. The servo sectors 36₀-36_N may comprise any suitable head position information, such as a track address for coarse positioning and servo bursts for fine positioning. The servo bursts may comprise any suitable pattern, such as an amplitude based servo pattern or a phase based servo pattern.

In an embodiment described below, extended servo data may be learned (e.g., compensation values that account for a repeatable disturbance) which may then be written after each servo sector as illustrated in the embodiment of FIG. 2A. During normal operation, the control circuitry 24 may read and process the extended servo data to facilitate servoing the head radially over the disk. In one embodiment, it may be desirable to write the extended servo data synchronous with each servo sector in order to obviate a preamble and sync mark in front of the extended servo data, thereby improving the format efficiency. In order to write the extended servo data synchronous with each servo sector, in one embodiment the reader/writer gap in terms of clock cycles of the disk-locked clock is measured and then used to write the extended servo data synchronous with each servo sector.

FIGS. 3A and 3B illustrate a technique for measuring the reader/writer gap when the reader/writer gap spans an integer number of the clock cycles 28. A reference clock cycle of the disk-locked clock is determined, such as when the read element 20 reaches the end of a first sync mark 46 in a servo sector 36_i. After delaying by a write delay (D_w) comprising an integer number of clock cycles as measured from the reference clock cycle, a second sync mark 48 is written during a first revolution of the disk. During a second revolution of the disk, a read delay (D_r) is measured from the reference clock cycle to the beginning of the second sync mark 48 (as determined after detecting the second sync mark 48). The reader/writer gap is then computed by subtracting the read delay (D_r) from the write delay (D_w).

Any suitable technique may be employed to measure the fraction of the clock cycle in the reader/writer gap measurement. FIG. 4 illustrates an embodiment wherein the fraction is measured by writing a second preamble at the end of a servo sector similar to writing the second sync mark 48 shown in FIG. 3A. During the second disk revolution, a first disk-locked clock 28 is synchronized to the first preamble of the servo sector, and a second disk-locked clock 50 is synchronized to the second preamble. The phase difference between the first disk-locked clock 28 and the second disk-locked clock 50 represents the fraction of the clock cycle in the reader/writer gap. In another embodiment, the second preamble may be sampled asynchronously with the first disk-locked clock 28 and with the timing recovery disabled. The phase offset between the first preamble and the second preamble may then be measured by computing a discrete Fourier transform (DFT) of the asynchronous signal samples of the second preamble relative to a DFT computed over the synchronous samples of the first preamble (or over synchronous samples of a servo burst).

FIG. 5 illustrates an example where the fraction of the clock cycle is measured when the head is positioned at a first plurality of radial locations across the disk 16 represented by the black dots. In on embodiment, the reader/writer gap increases from the outer diameter of the disk toward the inner diameter of the disk due to the decrease in the circumference of the servo tracks. That is, since the physical distance of the reader/writer gap remains constant, the number of clock cycles spanned by the reader/writer gap will increase toward the inner diameter of the disk due to the decrease in the linear velocity of the servo tracks (and the corresponding increase in the linear bit density of the servo data). In the example of FIG. 5, the variation in the reader/writer gap spans multiple clock cycles from the outer diameter to the inner diameter of the disk. Accordingly, the fraction of the clock cycle will vary from zero to a full clock cycle several times as the head moves from the outer diameter toward the inner diameter as shown in FIG. 5. In one embodiment, the control circuitry 24 measures the fraction at a first plurality of radial locations which may be evenly spaced across the radius of the disk as shown in FIG. 5. The control circuitry 24 may then curve fit the fractions between zero and one to a suitable polynomial, which may be a plurality of simple linear equations as shown in FIG. 5. The curve fitted polynomials may then be used to estimate the second plurality of radial locations where the fraction substantially equals a full one of the disk-locked clock cycles as shown in FIG. 5.

The radial locations where the fraction substantially equals a full one of the disk-locked clock cycles may be used in any suitable manner. FIG. 6 is a flow diagram according to an embodiment which extends on the flow diagram of FIG. 2C, wherein the control circuitry 24 measures the reader/writer gap at any given radial location in units of disk-locked clock cycles based on the second plurality of radial locations where the fraction substantially equals a full one of the clock cycles (block 52). For example, in one embodiment the control circuitry 24 may measure the reader/writer gap in units of disk-locked clock cycles (integer plus fraction) at a first radial location, such as at the first radial location 54 shown in FIG. 5. The first integer M of clock cycles in the reader/writer gap at the first radial location 54 may be measured in any suitable manner, such as described above with reference to FIGS. 3A and 3B. The reader/writer gap in units of disk-locked clock cycles may then be estimated at a second radial location by adding an integer N to the integer M, where N represents a number of times the fraction substantially equals a full one of the clock cycles between the first radial location and the second radial location. An example of this embodiment is illustrated in FIG. 7 where the reader/writer gap is estimated at a second radial location by adding N=4 to M, where N increments by one each time the fraction wraps (i.e., each time the fraction equals a full disk-locked clock cycle). In one embodiment, the fraction of the disk-locked clock cycle at the second radial location may be estimated by using the curve fitted polynomial equation, such as the linear equation shown in FIG. 5 that corresponds to the second radial location. Accordingly, the fraction of the disk-locked clock cycle measured at the first radial locations across the radius of the disk as shown in the example of FIG. 5 may be used to estimate the reader/writer gap in units of the disk-locked clock (integer plus fraction) at any given radial location, and in one embodiment the reader/writer gap may be estimated across the entire radius of the disk as shown in the example of FIG. 8.

In one embodiment, the reader/writer gap in units of the disk-locked clock may be used to write extended servo data synchronous with the end of each servo sector, such as compensation values that account for a repeatable disturbance. For example, when the read element 22 passes over the end of a servo sector, the control circuitry may delay by the estimated reader/writer gap (integer plus fraction of disk-locked clock cycles) and then write the extended servo data just past the end of the servo sector. In this manner, when the servo sector is read again, the disk-locked clock used to sample the read signal generated by the read element 22 will be synchronized to the extended servo data, thereby enabling accurate recovery of the extended servo data while minimizing the recording area consumed by the extended servo data. That is, since the extended servo data is written synchronous with the end of the servo sector, there may be no need to record a preamble and sync mark at the beginning of the extended servo data. In addition, since the reader/writer gap has been estimated at each radial location, the extended servo data may be written very close to the end of each servo sector in order to minimize the gap between the servo sector and extended servo data.

Any suitable control circuitry may be employed to implement the flow diagrams in the above embodiments, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain operations described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into a SOC.

In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.

The various features and processes described above may be used independently of one another, or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of this disclosure. In addition, certain method, event or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate. For example, described tasks or events may be performed in an order other than that specifically disclosed, or multiple may be combined in a single block or state. The example tasks or events may be performed in serial, in parallel, or in some other manner. Tasks or events may be added to or removed from the disclosed example embodiments. The example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed example embodiments.

While certain example embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions disclosed herein. Thus, nothing in the foregoing description is intended to imply that any particular feature, characteristic, step, module, or block is necessary or indispensable. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the embodiments disclosed herein.