Disk drive compensating for cycle slip of disk locked clock when reading mini-wedge

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to provisional U.S. Patent Application Ser. No. 61/922,996, filed on Jan. 2, 2014, which is hereby incorporated by reference in its entirety.

BACKGROUND

Disk drives comprise a disk and a head connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. The disk comprises a plurality of radially spaced, concentric tracks for recording user data sectors and servo sectors. The servo sectors comprise head positioning information (e.g., a track address) which is read by the head and processed by a servo control system to control the actuator arm as it seeks from track to track.

FIG. 1 shows a prior art disk format 2 as comprising a number of servo tracks 4 defined by servo sectors 6₀-6_N recorded around the circumference of each servo track. Each servo sector 6_i comprises a preamble 8 for storing a periodic pattern, which allows proper gain adjustment and timing synchronization of the read signal, and a sync mark 10 for storing a special pattern used to symbol synchronize to a servo data field 12. The servo data field 12 stores coarse head positioning information, such as a servo track address, used to position the head over a target data track during a seek operation. Each servo sector 6_i further comprises groups of servo bursts 14 (e.g., N and Q servo bursts), which are recorded with a predetermined phase relative to one another and relative to the servo track centerlines. The phase based servo bursts 14 provide fine head position information used for centerline tracking while accessing a data track during write/read operations. A position error signal (PES) is generated by reading the servo bursts 14, wherein the PES represents a measured position of the head relative to a centerline of a target servo track. A servo controller processes the PES to generate a control signal applied to a head actuator (e.g., a voice coil motor) in order to actuate the head radially over the disk in a direction that reduces the PES.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a prior art disk format comprising a plurality of servo tracks defined by servo sectors.

FIG. 2A shows a disk drive according to an embodiment comprising a head actuated over a disk comprising full servo sectors and short servo sectors.

FIG. 2B shows an embodiment wherein each full servo sector comprises a sync mark whereas each short servo sector does not comprise a sync mark.

FIG. 2C shows a flow diagram according to an embodiment wherein a disk locked clock is adjusted based on a first phase error generated by reading the sync marks in the full servo sectors and based on a second phase error generated by reading a reference pattern in the short servo sectors.

FIG. 2D shows a timing recovery system according to an embodiment for generating the disk locked clock based on the first phase error generated by reading the sync marks in the full servo sectors.

FIGS. 3A and 3B illustrate an embodiment wherein the second phase error is processed to determine whether the disk locked clock slipped a cycle before the head reaching a short servo sector.

FIG. 4 illustrates an embodiment wherein the second phase error generated by reading the reference pattern in a short servo sector is adjusted by −360 or +360 degrees depending on the polarity of the second phase error.

FIG. 5 shows a timing recovery system according to an embodiment wherein when the adjusted second phase error indicates the disk locked clock slipped a cycle, the adjusted second phase error is used to adjust the disk locked clock.

DETAILED DESCRIPTION

FIG. 2A shows a disk drive according to an embodiment comprising a head 16 actuated over a disk 18 comprising a plurality of servo tracks 20 defined by full sectors 22₀-22_N and intervening short servo sectors (e.g., short servo sector 24), where FIG. 2B shows each full servo sector 22 comprises a sync mark 26, a preamble 28, and servo bursts 30, and each short servo sector 24 comprises a reference pattern 32 and servo bursts 34. The disk drive further comprises control circuitry 36 operable to execute the flow diagram of FIG. 2C, wherein a first phase error is generated based on the sync mark in a first full servo sector (block 38), and a disk locked clock is adjusted in response to the first phase error (block 40). A second phase error is generated based on the reference pattern in a first short servo sector (block 42), and the second phase error is processed to determine whether the disk locked clock slipped a cycle before the head reaching the first short servo sector (block 44).

FIG. 2D shows a timing recovery system according to an embodiment comprising a timing plant 48 for generating a disk locked clock 46. In the embodiment of FIG. 2D, the plant 48 comprises a frequency generator 48A for generating the disk locked clock 46 at a frequency based on an input control signal 50. The timing plant 48 further comprises a block 48B for measuring a phase 52 of the disk locked clock 46 relative to a rotation speed of the disk 18. The measured phase 52 is subtracted from a target phase 54 to generate a phase error 56. A suitable compensator 58 filters the phase error 56 to generate the control signal 50 applied to the frequency generator 48A, thereby adjusting the disk locked clock 46 so as to be synchronized with the rotation speed of the disk 18.

The phase 52 of the disk locked clock 46 relative to the rotation speed of the disk may be measured in any suitable manner. In one embodiment, the disk locked clock 46 is used to clock a counter which counts an integer number of clock cycles between the sync marks 26 in each of the full servo sectors 22. In addition, the preamble 28 of a full servo sector 22 may be sampled using the disk locked clock 46 in order to measure a fractional phase of the disk locked clock 46 by, for example, computing a Discrete Fourier Transform (DFT). If the disk locked clock 46 is exactly synchronized to the rotation speed of the disk 18, the integer number of clock cycles between the sync marks 26 of consecutive full servo sectors will match a target integer, and the fractional phase when sampling the preamble 28 will match a target fraction (e.g., zero). However, imperfections in the spindle motor that rotates the disk 18 as well as other factors, such as eccentricity of the servo tracks 20, will cause the rotation speed of the disk 18 relative to the head 16 to vary as the disk 18 rotates, thereby inducing a phase error 56 in the timing recovery system of FIG. 2D.

In one embodiment, the sampling frequency of the phase error 56 in the timing recovery system affects the ability to accurately synchronize the disk locked clock 46 to within an acceptable error. Accordingly, in order to improve the performance of the timing recovery system and/or in order to abort a write operation due to a substantial disturbance to the disk drive (e.g., a physical shock), the phase error of the disk locked clock 46 may be updated when reading one of the short servo sectors 24 shown in FIG. 2B. In one embodiment, the short servo sector 24 is recorded without a sync mark so as to improve the format efficiency, and therefore only a fractional phase of the disk locked clock 46 may be measured by reading the reference pattern 32. However, if the disk locked clock 46 slips a full cycle before the head 16 reaches the short servo sector 24, the fractional phase may be measured incorrectly.

FIG. 3A shows an example where the target fractional phase is zero and the actual fractional phase error 60 at the short servo sector exceeds +180 degrees due to the disk locked clock 46 having a positive cycle slip, thereby causing the measured phase error to become negative (e.g., −170 degrees instead of +190 degrees). FIG. 3B illustrates the opposite example where the actual fractional phase error 62 at the short servo sector exceeds −180 due to the disk locked clock 46 having a negative cycle slip, thereby causing the measured phase error to become positive (e.g., +170 degrees instead of −190 degrees). Accordingly, in one embodiment the phase error measured at a short servo sector is processed to determine whether the disk locked clock 46 slipped a cycle before the head 16 reached the short servo sector.

FIG. 4 shows an example embodiment for processing the phase error 56 measured at a short servo sector. In this embodiment, the timing recovery system comprises a suitable phase error estimator 64 which processes the previously generated phase error 56 and the control signal 50 in order to estimate the phase error when the head 16 reaches a short servo sector. If the phase error measured at the short servo sector (by reading the reference pattern 32) is less than a negative threshold at comparator 66, it means there is a chance of a positive cycle slip by the disk locked clock 46 as illustrated in FIG. 3A. Accordingly, the measured phase error 56 is adjusted by adding 360 degrees to convert the negative phase error into an equivalent positive phase error as shown in FIG. 3A. Conversely, if the phase error measured at the short servo sector (by reading the reference pattern 32) is greater than a positive threshold at comparator 68, it means there is a chance of a negative cycle slip by the disk locked clock 46 as illustrated in FIG. 3B. Accordingly, the measured phase error 56 is adjusted by subtracting 360 degrees to convert the positive phase error into an equivalent negative phase error as shown in FIG. 3B. The adjusted phase error 70 is compared to the estimated phase error 72 (by computing a subtraction 74 and absolute value 76), and when the comparison is less than a threshold at comparator 78, a cycle slip of the disk locked clock 46 is detected. That is, when the adjusted phase error is close to the estimate phase error within a predetermined margin, it is assumed the disk locked clock 46 slipped a cycle.

Any suitable action may be taken when a cycle slip of the disk locked clock 46 is detected at a short servo sector, such as aborting a write operation. That is, a cycle slip may be caused by a substantial disturbance such as a physical shock to the disk drive during a write operation. A physical shock that induces a cycle slip of the disk locked clock 46 may also cause the head 16 to deviate away from the center of the target track causing an off-track write condition. Accordingly, when a cycle slip is detected during a write operation while the head is between full servo sectors, a write operation may be aborted sooner so as to avoid corrupting data recorded in adjacent tracks (as compared to delaying the write abort until the next full servo sector is reached).

In another embodiment illustrated in FIG. 5, when a cycle slip of the disk locked clock is detected at a short servo sector, the adjusted phase error 70 may be selected (by configuring multiplexer 80) as the phase error input into the compensator 58. Adjusting the disk locked clock 46 based on the adjusted phase error 70 rather than the measured phase error 56 avoids the transient that would otherwise be introduced into the timing recovery system, while still improving the timing recovery performance by providing at least one extra phase error sampling between full servo sectors.

Although the embodiment of FIG. 2A shows a single short servo sector between consecutive full servo sectors, other embodiments may employ two or more short servo sectors, wherein a phase error for the disk locked clock may be measured at each short servo sector. In addition, any suitable format may be employed for the full servo sectors as well as the short servo sectors as compared to the embodiment shown in FIG. 2B. For example, one or more of the short servo sectors 24 may comprise additional fields that may precede or follow the servo bursts 34. For example, a field following the servo bursts 34 may comprise additional servo information, such as a partial track ID and/or compensation values that compensate for a repeatable runout (RRO) of the disk 18.

Any suitable control circuitry may be employed to implement the flow diagrams in the above embodiments, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain operations described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into a SOC.

In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.

The various features and processes described above may be used independently of one another, or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of this disclosure. In addition, certain method, event or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate. For example, described tasks or events may be performed in an order other than that specifically disclosed, or multiple may be combined in a single block or state. The example tasks or events may be performed in serial, in parallel, or in some other manner. Tasks or events may be added to or removed from the disclosed example embodiments. The example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed example embodiments.

While certain example embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions disclosed herein. Thus, nothing in the foregoing description is intended to imply that any particular feature, characteristic, step, module, or block is necessary or indispensable. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the embodiments disclosed herein.