CHEMICAL MECHANICAL PLANARIZATION TOOL

Description

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims the benefits of U.S. Provisional Application No. 63/715,039, filed on Nov. 1, 2024, which application is hereby incorporated herein by reference in its entirety.

BACKGROUND

As the layers of a semiconductor device are formed, planarization processes may be performed to planarize the layers to facilitate formation of subsequent layers. For example, the formation of metallic features in the substrate or in a metal layer may cause uneven topography. This uneven topography may create difficulties in the formation of subsequent layers. For example, uneven topography may interfere with the photolithographic process commonly used to form various features in a device. Therefore, it may be advantageous to planarize the surface of the device after various features or layers are formed.

Chemical mechanical polishing (CMP) is a common practice in the formation of integrated circuits. Typically, CMP is used for the planarization of semiconductor wafers. CMP takes advantage of the synergetic effect of both physical and chemical forces for the polishing of wafers. It is performed by applying a load force to the back of a wafer while the wafer rests on a polishing pad. A polishing pad is placed against the wafer. Both the polishing pad and the wafer are then rotated while a slurry containing both abrasives and reactive chemicals is passed therebetween. CMP is an effective way to achieve global planarization of wafers.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a perspective view of a chemical mechanical polishing (CMP) apparatus, in accordance with an embodiment.

FIG. 2 illustrates a magnified cross-sectional view of a CMP apparatus, in accordance with an embodiment.

FIG. 3 illustrates a partial schematic of a CMP apparatus in a perspective view, in accordance with an embodiment.

FIGS. 4, 5, 6, and 7 illustrate magnified cross-sectional views of a CMP apparatus, in accordance with some embodiments.

FIG. 8 illustrates a magnified cross-sectional view of a CMP apparatus, in accordance with an embodiment.

FIGS. 9, 10, 11, 12, 13, 14, 15, and 16 illustrate top-down plan views of polishing pads, in accordance with some embodiments.

FIG. 17 illustrates a perspective view of example Complementary Field-Effect Transistors (CFETs), in accordance with some embodiments.

FIGS. 18, 19, 20, 21, 22, 23, 24, and 25 illustrate cross-sectional views of intermediate stages in the manufacturing of a CFET structure, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Through the description herein, unless other specified, the same reference numeral in different figures refers to the same or similar component.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Chemical mechanical polishing (CMP) is a method of planarizing features produced in the manufacture of semiconductor devices. The process uses an abrasive material in a reactive chemical slurry in conjunction with a polishing pad. The polishing pad typically has a greater diameter than that of the semiconductor wafer. In some cases, the polishing pad may be formed of a stack of multiple pads, such as a top pad attached to a sub pad, or the like. The pad and wafer are pressed together during the CMP process. The process removes material and tends to even out irregular topography, making the wafer flat or substantially planar. This prepares the wafer for the formation of additional overlying circuit elements.

In a CMP process, a wafer is secured to a polisher head (also referred to as a “head” or a “carrier”). The polisher head and the wafer are then rotated as downward pressure is applied to press the wafer against the polishing pad. The polishing pad may also be rotated, in some cases. A reactive chemical solution (e.g., a slurry) is dispensed on a contacting surface of the polishing pad to aid planarization. The surface of a wafer may thus be planarized using a combination of both mechanical and chemical mechanisms.

Various representative embodiments are described with respect to operating a CMP tool, and in particular, inspecting a workpiece (e.g., a wafer) during operation of the CMP tool. Apertures in the polishing pad of the CMP tool allow the workpiece to be optically inspected during the planarization process. The apertures may be located within top-side grooves of the polishing pad. The apertures extend through the top pad and the sub pad that form the polishing pad. The apertures in the polishing pad can allow multiple optical inspection systems to be utilized within a CMP tool, improving in situ inspection of the workpiece. Inspecting the workpiece during planarization can, for example, reduce stop layer loss. A variety of arrangements of grooves, apertures, and inspection systems are possible.

FIG. 1 illustrates a perspective view of a chemical mechanical polishing (CMP) apparatus 100 (also referred to as a polisher or a CMP tool), in accordance with some embodiments. The CMP apparatus 100 includes a platen 140 and a polishing pad 150 attached to the platen 140. In some embodiments, the polishing pad 150 includes a single layer or multiple layers, such as multiple pads that are attached together in a stack, or the like. The layers of the polishing pad 150 may comprise one or more materials, such as felts, polymer impregnated felts, microporous polymer films, microporous synthetic leathers, filled polymer films, unfilled textured polymer films, transparent layers, combinations thereof, or the like. Representative polymers include polyurethane, polyolefins, or the like. For example, in some embodiments, the polishing pad 150 may comprise a sub pad 152 and a top pad 156 attached to the sub pad 152, described in greater detail below. In some embodiments, the polishing pad 150 comprises grooves, trenches, channels, apertures, openings, recesses, or the like.

As illustrated in FIG. 1, a polisher head 120 is placed over the polishing pad 150. During a representative CMP process, a workpiece 130 (e.g., a semiconductor wafer or the like) is secured or attached to the polisher head 120. The workpiece 130 is positioned such that a surface to be polished faces in a direction (for example, downward) towards the polishing pad 150. The polisher head 120 may be configured to apply downward force or pressure urging the workpiece 130 into contact with the polishing pad 150. In some cases, the workpiece 130 may not make direct contact with the polishing pad 150 during the CMP process. The polisher head 120 is configured to rotate the workpiece 130 over the polishing pad 150 during the CMP process, thereby imparting mechanical abrading action to affect planarization or polishing of a contacting surface of the workpiece.

In some embodiments, the CMP apparatus 100 includes a slurry dispenser 110 configured to deposit a slurry 115 onto the polishing pad 150. The platen 140 may be configured to rotate, causing the slurry 115 to be distributed between the workpiece 130 and the polishing pad 150. In some cases, the polishing pad 150 includes grooves (not illustrated in FIG. 1 but illustrated in subsequent Figures) that allow the slurry and any removed particles to flow toward the perimeter of the polishing pad 150, improving the polishing process. The composition of the slurry 115 may depend on which types of material are to be polished or removed.

FIG. 2 illustrates a magnified cross-sectional view of a portion of a CMP apparatus 100, in accordance with some embodiments. The portion illustrated in FIG. 2 may be a portion of a CMP apparatus 100 that is similar to the CMP apparatus 100 shown in FIG. 1. For example, the portion shown in FIG. 2 includes a workpiece 130 attached to a polisher head, and a polishing pad 150 attached to a platen 140. The platen 140 further includes an optical inspection system 141 used to inspect an underside of the workpiece 130 during a CMP process.

In some embodiments, the polishing pad 150 comprises multiple pads or layers. For example, the polishing pad 150 shown in FIG. 2 includes an upper pad, referred to herein as a top pad 156, attached to a lower pad, referred to herein as a sub pad 152. The top pad 156 and the sub pad 152 may be formed of similar or different materials and may have similar or different hardnesses, textures, or other characteristics. The top pad 156 and the sub pad 152 may be secured or attached together to ensure that they do not move independently relative to one another. As further described in this disclosure, the top pad 156 may have grooves 157 along and within a top surface of the top pad 156. The top pad 156 may further include top apertures 158 (described in greater detail below) within the grooves 157 that extend through the top pad 156 from the grooves 157 to a bottom surface of the top pad 156. The sub pad 152 may include sub apertures 154 that extend through the sub pad 152. In some embodiments, top apertures 158 and sub apertures 154 may be aligned (e.g., may laterally overlap or may be present along a same vertical). As will be discussed in greater detail below, a polishing pad 150 may comprise a variety of patterns, configurations, or arrangements of grooves 157, top apertures 158, and sub apertures 154.

The top pad 156 may be attached to the sub pad 152 and the sub pad 152 may be attached to the platen 140 using suitable techniques, such as using adhesives, glues, screws, clamps, or the like (not illustrated in the figures). For example, in some cases, the sub pad 152 is attached to the platen 140 using an adhesive, and the top pad 156 is attached to the sub pad 152 using an adhesive. The adhesives may include, for example, a pressure-sensitive adhesive, a reactive hot melt adhesive, a polyurethane adhesive, an epoxy, an adhesive layer or adhesive pad, or the like. Other techniques are possible.

In some embodiments, the platen 140 includes one or more optical inspection systems 141. The optical inspection systems 141 may rotate along with the platen 140, though in other embodiments the optical inspection systems 141 may be fixed with respect to the rotation of the platen 140. The optical inspection systems 141 are devices, components, modules, systems, or the like that may inspect (e.g., measure, monitor, detect, etc.) characteristics of a bottom surface of the workpiece 130 to facilitate the desired planarization performed by the CMP process. For example, an optical inspection system 141 may inspect the surface of the workpiece 130 being planarized (e.g., the bottom or underside surface) to determine a thickness or a thickness profile of a layer (e.g., the bottommost layer) of the workpiece 130. As another example, an optical inspection system 141 may detect the spectrum of light reflected by a bottom surface of workpiece 130 to determine the composition of the material at the bottom surface of the workpiece 130. In this manner, an optical detection system 141 may be able to determine if a bottommost layer of the workpiece 130 has been removed based on the spectrum of reflected light. For example, if the bottommost layer covers a stop layer, the polishing operation can be halted when the stop layer is exposed. In this manner, the amount of stop layer material that is removed by a polishing process can be reduced.

Characteristics such as roughness, material, reflectivity, absorption, or the like may also be determined by an optical inspection system 141. The optical inspection systems 141 may utilize appropriate techniques such as ellipsometry, interferometry, reflectometry, spectrometry, imaging, or the like. Other techniques or characteristics are possible. The CMP apparatus 100 may include more than one type of optical inspection system 141, in some embodiments. In some embodiments, the optical inspection systems 141 are operated during (e.g., simultaneous with) the polishing operation of the CMP process. In other embodiments, the polishing operation of the CMP process may be stopped or paused to allow the optical inspection systems 141 to operate.

As an example, in some embodiments, an optical inspection system 141 may comprise a light source 142 and a detector 144. The light source 142 may emit light that is directed toward a region of the bottom surface the workpiece 130, and the detector 144 senses light that is reflected or scattered from the region of the bottom surface of the workpiece 130. The optical inspection system 141 may determine the characteristics of the region of the bottom surface of the workpiece 130 based on the light received by the detector 144. The light source 142 may be any suitable source of electromagnetic radiation, such as a light-emitting diode, a laser, a lamp, a broadband light source, or the like, which may depend on the inspection technique being used by the optical inspection system 141. The detector 144 may be any suitable optical detector, optical sensor, light sensor, or the like, which may depend on the inspection technique being used by the optical inspection system 141. In some cases, the spectrum of light emitted by the light source 142 may fully or partially overlap the spectrum of light sensed by the detector 144. For example, an optical inspection system 141 may operate in a white light spectrum (e.g., wavelengths in the range of about 300 nm to about 700 nm), operate in an infrared spectrum (e.g., wavelengths in the range of about 780 nm to about 1400 nm), or operate using any other suitable wavelengths of light.

As shown in FIG. 2, in order to allow light emitted from a light source 142 to reach the workpiece 130, and in order to allow light reflected from a workpiece 130 to reach the detector 144, the sub pad 152 includes sub apertures 154, and the top pad 156 includes top apertures 158. The sub apertures 154 are openings in the sub pad 152, and the top apertures 158 are openings in the top pad 156 over sub apertures 154. Thus, an open (or optically transparent) region of the polishing pad 150 is provided for the transmission of light. In this manner, light emitted and/or received by an optical inspection system 141 is able to travel through associated apertures 154/158 to allow for optical inspection of the workpiece 130 through the polishing pad 150. Accordingly, the openings extending fully through the polishing pad 150, including the apertures 154/158, may be considered “inspection holes 153.” Each optical inspection system 141 is aligned to a top aperture 158 and a sub aperture 154, and in some embodiments multiple optical inspection systems may be aligned to the same top aperture 158 and/or the same sub aperture 154. In some embodiments, the light emitted by an optical inspection system 141 and the light received by the same optical inspection system 141 travels through the same set of apertures 154/158.

In some embodiments, each top aperture 158 is aligned to a groove 157 of the top pad 156. In other words, the portions of the inspection holes 153 that extend through the top pad 156 include both grooves 157 and top apertures 158. Each top aperture 158 is underneath a groove 157 to form a continuous opening (e.g., hole) extending through the top pad 156 formed by the top aperture 158 and the groove 157. A groove 157 may extend over or across one or more top apertures 158. In some cases, multiple top apertures 158 may be underneath the same groove 157. Aligning the top apertures 158 to grooves 157 allows for top apertures 158 to have smaller heights, as the top apertures 158 do not need to extend through the full thickness of the top pad 156. Additionally, locating the top apertures 158 underneath grooves 157 can reduce the effects of the presence of the top apertures 158 on the polishing of the workpiece 130. Each sub aperture 154 is located underneath a top aperture 158 to form a continuous inspection hole 153 through the polishing pad 150. Accordingly, each sub aperture 154 is aligned to both a top aperture 158 and a groove 157. In this manner, each inspection hole 153 includes a groove 157, a top aperture 158, and a sub aperture 154. The grooves 157, top apertures 158, and/or sub apertures 154 may be shared by two or more inspection holes 153, in some cases.

The grooves 157, top apertures 158, and sub apertures 154 may have any suitable lengths, widths, or shapes that allow for the transmission of light through the polishing pad 150. For example, FIG. 2 illustrates an embodiment in which a top aperture 158 underneath a groove 157 has a smaller width than the groove 157, and in which a sub aperture 154 underneath a top aperture 158 has a larger width than the top aperture 158. In other embodiments, the widths of the grooves 157, top apertures 158, and sub apertures 154 may be larger, smaller, or about the same as each other, in any suitable combination. In some embodiments, a groove 157 may extend a depth in the range of about 0.2 mm to about 2 mm into the top pad 156. In some embodiments, a groove 157 may have a width in the range of about 0.3 mm to about 2 mm, a top aperture 158 may have a width in the range of about 0.3 mm to about 2.5 mm, and a sub aperture may have a width in the range of about 0.3 mm to about 2 mm. In some embodiments, the top pad 156 has a thickness in the range of about 0.5 mm to about 3 mm, and the sub pad 152 has a thickness in the range of about 0.5 mm to about 3 mm. Other configurations, shapes, widths, thicknesses, or sizes are possible.

FIG. 3 illustrates a partial schematic of a CMP apparatus 100 in a perspective view, in accordance with some embodiments. The CMP apparatus 100 shown in FIG. 3 may be similar to those described previously for FIGS. 1 and 2. For example, FIG. 3 illustrates a “exploded” view of a polishing pad 150 comprising a top pad 156 and a sub pad 152. The top pad 156 comprises a pattern of grooves 157, and a plurality of top apertures 158 aligned to the grooves 157. The sub pad 152 comprises a plurality of sub apertures 154 aligned to the top apertures 158. The platen 140 (outlined in dashed lines) comprises a plurality of optical inspection systems 141 aligned to the sub apertures 154. The “footprint” of the workpiece 130 is indicated by dashed lines. As shown in FIG. 3, the optical inspection systems 141 can transmit and receive light through the apertures 154/158 in the polishing pad 150 to inspect different regions of the workpiece 130.

The pattern, arrangement, or number of grooves 157, top apertures 158, sub apertures 154, and/or optical inspection systems 141 may be different than shown in FIG. 3, and all suitable variations are considered within the scope of the present disclosure. The optical inspection systems 141 may be arranged in a suitable spatial distribution, which may depend on the configuration of the apertures 154/158 of the polishing pad 150.

Distributing multiple inspection systems 141 across the area of a workpiece 130 can allow for the simultaneous inspection of different portions of the workpiece 130. The use of apertures 154/158 as described herein allow for multiple optical inspection systems 141 to be used in a CMP process, enabling more sampling locations. This can allow for improved workpiece inspection during planarization, improved planarization uniformity, improved planarization accuracy, and improved yield.

FIGS. 4-7 illustrate embodiments of polishing pads 150 that include a transparent layer 155, in accordance with some embodiments. The polishing pads 150 of FIG. 4-7 are similar to that described for FIGS. 1-3 and shown in FIG. 2, except that a transparent layer 155 extends across the inspection holes 153. The transparent layer 155 may be present, for example, to at least partially block slurry 115 from flowing into the apertures 154/158. The transparent layer 155 can also prevent slurry 115 from flowing onto the platen 140 or onto components of the optical inspection systems 141. In this manner, the amount of light absorbed or blocked by slurry 115 in the inspection holes 153 can be reduced, and components of the optical inspection systems 141 can be protected from slurry 115. Thus, the use of a transparent layer 155 within a polishing pad 150 can improve the operation of the optical inspection systems 141.

The transparent layer 155 may be a layer having a high transmittance of light (e.g., a transmittance in the range of about 60% to about 99%) within a wavelength range used by the optical inspection systems 141. For example, the transparent layer 155 may be formed of a polymer material such as polymethyl methacrylate (PMMA) or the like, though other materials are possible. In some embodiments, the transparent layer 155 may be attached using one or more adhesive layers (not illustrated), such as those described previously for the polishing pad 150.

The transparent layer 155 may have any suitable thickness. The transparent layer 155 may be a single continuous layer within the polishing pad 150 that extends across all inspection holes 153 in the polishing pad 150. In some cases, the transparent layer 155 extends fully across the polishing pad 150. Although a single transparent layer 155 is shown in FIGS. 4-7, multiple transparent layers may be present in other embodiments. FIGS. 4-7 illustrate some example locations of the transparent layer 155 within a polishing pad 150, but a transparent layer 155 may have other locations in other embodiments.

FIG. 4 illustrates an embodiment in which the polishing pad 150 includes a transparent layer 155 that is located between the sub pad 152 and the top pad 156. In this manner, slurry 115 may be prevented from flowing into the sub apertures 154. In some embodiments, the transparent layer 155 may be attached to the sub pad 152 using an adhesive, and the transparent layer 155 may be attached to the top pad 156 using an adhesive.

FIG. 5 illustrates an embodiment in which the polishing pad 150 includes a transparent layer 155 that is located within the sub pad 152. In other words, the transparent layer 155 extends across the sub apertures 154. In this manner, slurry 115 may be prevented from flowing into lower regions of the sub apertures 154. FIG. 6 illustrates an embodiment in which the polishing pad 150 includes a transparent layer 155 that is located within the top pad 156. In other words, the transparent layer 155 extends across the top apertures 158. In this manner, slurry 115 may be prevented from flowing into lower regions of the top apertures 158 and into the sub apertures 154. In other embodiments, the transparent layer 155 may be located between the grooves 157 and the top apertures 158, separating the grooves 157 from the top apertures 158.

FIG. 7 illustrates an embodiment in which the polishing pad 150 includes a transparent layer 155 that is located under the sub pad 152. In other words, the transparent layer 155 is located between the sub pad 152 and the platen 140. In this manner, slurry 115 may be prevented from flowing onto the platen 140 and on components of the optical inspection systems 141. In some embodiments, the transparent layer 155 may be attached to the sub pad 152 using an adhesive, and the transparent layer 155 may be attached to the platen 140 using an adhesive.

FIG. 8 illustrates a polishing pad 150 that includes a transparent sub pad 152, in accordance with some embodiments. The polishing pad 150 of FIG. 8 is similar to that described for FIGS. 1-3 and shown in FIG. 2, except that the sub pad 152 itself is a transparent layer. Accordingly, sub apertures 154 are not present in the embodiment of FIG. 8, as the light can be transmitted directly through the transparent sub pad 152. The optical inspection systems 141 may be aligned to the top apertures 158. The transparent sub pad 152 may have a high transmittance of light (e.g., a transmittance in the range of about 60% to about 99%) within a wavelength range used by the optical inspection systems 141. The transparent sub pad 152 may be formed of materials similar to those described for the transparent layer 155, such as PMMA or the like, though other materials are possible. The use of a transparent sub pad 152 as described herein can reduce light attenuation due to the presence of slurry 115, and can allow for improved optical inspection during a CMP process. Additionally, a transparent sub pad 152 can protect the platen 140 or components of the optical inspection systems 141 from the slurry 115.

FIGS. 9 through 16 illustrate plan views of polishing pads 150, in accordance with some embodiments. FIGS. 9-16 illustrate a top-down view, with the workpiece 130 indicated by a dashed line. During a CMP process, the polishing pad 150 and/or the workpiece 130 may rotate, and the workpiece 130 may be translated along the surface of the polishing pad 150. The polishing pads 150 are similar to those described previously for FIGS. 1-7. For example, the polishing pads 150 in FIGS. 9-16 include a top pad 156 over a sub pad 152 (only visible in FIG. 16). The top pad 156 includes one or more grooves 157 in a top surface of the top pad 156, and a plurality of top apertures 158 within the grooves 157 and extending through the top pad 156. The sub pad 152 includes a plurality of sub apertures 154 (only separately visible in FIG. 16) aligned to the top apertures 158. The grooves 157, top apertures 158, and sub apertures 154 collectively form inspection holes 153 that extend through the polishing pad 150. In FIGS. 9-15, the sub apertures 154 have a similar or larger area as the overlying top apertures 158, and are thus not visible in a top-down view. The sub apertures 154 may have a smaller area than the overlying top apertures 158 in other embodiments. The platen 140 (not visible in the figures) is beneath the polishing pad 150, and includes optical inspection systems 141, which are represented in the figures as circles. The optical inspection systems 141 are aligned to the inspection holes 153, and thus may be seen through the inspection holes 153 in the top-down views of FIGS. 9-16.

FIGS. 9-16 illustrate a variety of configurations and arrangements of grooves 157, inspection holes 153, and optical inspection systems 141. The polishing pads 150 shown in FIGS. 9-16 are intended as non-limiting illustrative examples, and any other suitable configurations or arrangements are considered within the scope of the present disclosure. The various features and arrangements described in the present disclosure for the polishing pads 150 may be combined in any suitable manner. For example, in other embodiments, the polishing pads 150 of FIGS. 9-16 may include a transparent layer 155, or may include a combination of grooves 157, inspection holes 153, and optical inspection systems 141 having various configurations or arrangements.

FIG. 9 illustrates a polishing pad 150 having concentric grooves 157, in accordance with some embodiments. For example, the grooves 157 may be arranged in a configuration of concentric circles. FIG. 9 illustrates three concentric grooves 157 in the top pad 156, but another number of grooves 157 may be present in other embodiments. The inspection holes 153 are arranged evenly around the grooves 157, but the inspection holes 153 may have a different number or arrangement in other embodiments. In the embodiment of FIG. 9, each inspection hole 153 corresponds to one optical inspection system 141. In other words, each optical inspection system 141 underlies a unique inspection hole 153, through which it inspects the workpiece 130.

FIG. 10 illustrates a polishing pad 150 having concentric grooves 157, in accordance with some embodiments. The polishing pad 150 is similar to the polishing pad 150 of FIG. 9, except that multiple optical inspection systems 141 inspect the workpiece 130 through the same inspection hole 153. In other words, each inspection hole 153 extends over multiple optical inspection systems 141. In FIG. 10, three optical inspection systems 141 are associated with each inspection hole 153, but any number of optical inspection systems 141 may use the same inspection hole 153 in other embodiments. In some cases, distributing the optical inspection systems 141 such that multiple optical inspection systems 141 inspect the workpiece 130 through the same inspection hole 153 can allow for a larger number or larger density of optical inspection systems 141 that are able to simultaneously inspect the workpiece 130.

FIG. 11 illustrates a polishing pad 150 having both radial grooves 157A and concentric grooves 157B, in accordance with some embodiments. The radial grooves 157A and concentric grooves 157B may form a continuous pattern, as shown in FIG. 11. In other cases, some grooves 157A-B may be separated from other grooves 157A-B. Another number of grooves 157A-B may be present in other embodiments. As shown in FIG. 11, different grooves 157A-B in a polishing pad 150 may have different widths. The inspection holes 153 are shown as arranged evenly on the radial grooves 157A, but the inspection holes 153 may have a different number or arrangement in other embodiments. In the embodiment of FIG. 11, each inspection hole 153 corresponds to a single optical inspection system 141.

FIG. 12 illustrates a polishing pad 150 similar to that of FIG. 11, except that each inspection hole 153 corresponds to multiple optical inspection systems 141.

FIG. 13 illustrates a polishing pad 150 having a grid-like pattern of grooves 157, in accordance with some embodiments. FIG. 13 illustrates the grooves 157 forming a continuous pattern, but some grooves 157 may be separated from each other in other embodiments. The grooves 157 may be arranged in a rectangular grid-like pattern or another grid-like pattern. In the embodiment of FIG. 13, each inspection hole 153 corresponds to a single optical inspection system 141.

FIG. 14 illustrates a polishing pad 150 having a spiral pattern of grooves 157, in accordance with some embodiments. In some cases, a spiral pattern of grooves 157 can allow for improved flow of slurry 115 toward the edges of the polishing pad 150. Another number or shape of grooves 157 in a spiral pattern is possible. In the embodiment of FIG. 14, each inspection hole 153 corresponds to a single optical inspection system 141. FIG. 15 illustrates a polishing pad 150 similar to that of FIG. 14, except that each inspection hole 153 corresponds to multiple optical inspection systems 141.

FIG. 16 illustrates a polishing pad 150 similar to the polishing pad 150 shown in FIG. 10, except that the sub apertures 154 are smaller than the top apertures 158. In the embodiment of FIG. 16, each top aperture 158 extends over multiple sub apertures 154, and each sub aperture 154 corresponds to a single optical inspection system 141. In other embodiments, some sub apertures 154 may extend over multiple optical inspection systems 141. Because the sub apertures 154 are smaller than the top apertures 158, portions of the sub pad 152 are visible through the top apertures 158 in the top-down view of FIG. 16. The polishing pad 150 of FIG. 16 is intended as a representative and non-limiting example.

FIG. 17 through 25 provide a description of forming a complementary field-effect transistor (CFET) structure, in accordance with some embodiments. The CMP apparatus and method described herein may be utilized in the formation of the CFET structure as, in some cases, a CFET structure may have very strict specifications for the planarization processes in its fabrication process. However, the disclosed CMP apparatus and method are not limited to the fabrication of CFETs, but may be utilized during the formation of other types of devices, such as FinFETs, nanostructure-FETs, or the like.

FIG. 17 illustrates an example of CFETs 210 (including FETs (transistors) 210U and 210L) in accordance with some embodiments. FIG. 17 is a three-dimensional view, wherein some features of the CFETs are omitted for illustration clarity. The CFETs include multiple vertically stacked FETs. For example, a CFET may include a lower nanostructure-FET 210L of a first device type (e.g., n-type/p-type) and an upper nanostructure-FET 210U of a second device type (e.g., p-type/n-type) that is opposite the first device type. The nanostructure-FETs 210U and 210L include semiconductor nanostructures 226 (including lower semiconductor nanostructures 226L and upper semiconductor nanostructures 226U), where the semiconductor nanostructures 226 act as the channel regions for the nanostructure-FETs. The lower semiconductor nanostructures 226L are for the lower nanostructure—FET 210L, and the upper semiconductor nanostructures 226U are for the upper nanostructure—FET 210U. In other embodiments, the CFETs may be applied to other types of transistors (e.g., FinFETs, nanostructure—FETs, or the like) as well.

Gate dielectrics 278 encircle the respective semiconductor nanostructures 226. Gate electrodes 280 (including lower gate electrodes 280L and upper gate electrodes 280U) are over the gate dielectrics 278.

Source/drain regions 262 (including lower source/drain regions 262L and upper source/drain regions 262U) are disposed on opposing sides of the gate dielectrics 278 and the respective gate electrodes 280. The source/drain region may refer to a source or a drain, individually or collectively dependent upon the context. Isolation features (not shown) may be formed to separate desired ones of the source/drain regions 262 and/or desired ones of the gate electrodes 280.

FIG. 17 further illustrates a reference cross-section that is used in later figures. Cross-section A-A′ is a vertical cross-section that is parallel to a longitudinal axis of the semiconductor nanostructures 226 of a CFET and in a direction of, for example, a current flow between the source/drain regions 262 of the CFET. Subsequent figures may refer to this reference cross-section for clarity.

FIGS. 18 through 25 illustrate the cross-sectional views of intermediate stages in the formation of a CFET structure (as schematically represented in FIG. 17) in accordance with some embodiments. FIGS. 18 through 25 illustrate the vertical cross-sectional views along a similar cross-section as vertical reference cross-section A-A′ in FIG. 14.

In FIG. 18, a wafer, which includes a substrate 220, is provided. Substrate 220 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The SOI substrate may include a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, such as a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate 220 may include silicon, germanium, carbon-doped silicon, a III-V compound semiconductor; or the like, or combinations thereof. The substrate 220 may also be referred to as the semiconductor substrate herein. The substrate 220 may be similar to a workpiece 130, in some cases.

Semiconductor strips 228 are formed extending upwards from the semiconductor substrate 220. Each of semiconductor strips 228 includes a semiconductor strip 220′ (patterned portions of the semiconductor substrate 220, also referred to as semiconductor fins 220′) and a multi-layer stack 222. The stacked components of the multi-layer stack 222 are referred to as nanostructures hereinafter. Specifically, the multi-layer stack 222 includes dummy nanostructures 224A, dummy nanostructures 224B, lower semiconductor nanostructures 226L, and upper semiconductor nanostructures 226U. Dummy nanostructures 224A and dummy nanostructures 224B may further be collectively referred to as dummy nanostructures 224 and the lower semiconductor nanostructures 226L and the upper semiconductor nanostructures 226U may further be collectively referred to as semiconductor nanostructures 226.

The dummy nanostructures 224A are formed of a first semiconductor material, and the dummy nanostructures 224B are formed of a second semiconductor material that is different from the first semiconductor material. The first and second semiconductor materials may be selected, for example, from the candidate semiconductor materials of the semiconductor substrate 220. The first and second semiconductor materials have a high etching selectivity to one another. As such, the dummy nanostructures 224B may be removed at a faster rate than the dummy nanostructures 224A in subsequent processes.

The semiconductor nanostructures 226 (including the lower semiconductor nanostructures 226L and upper semiconductor nanostructures 226U) are formed of one or more third semiconductor material(s). The third semiconductor material(s) may be selected, for example, from the candidate semiconductor materials of the semiconductor substrate 220. The lower semiconductor nanostructures 226L and the upper semiconductor nanostructures 226U may be formed of the same semiconductor material, or may be formed of different semiconductor materials. Further, the first and second semiconductor materials of the dummy nanostructures 224 have a high etching selectivity to the third semiconductor material(s) of the semiconductor nanostructures 226. As such, the dummy nanostructures 224 may be selectively removed in subsequent process steps without significantly removing the semiconductor nanostructures 226. In some embodiments, dummy nanostructures 224A are formed of or comprise silicon germanium, the semiconductor nanostructures 226 are formed of silicon, and the dummy nanostructures 224B may be formed of germanium or silicon germanium with a higher atomic percentage of germanium than the dummy nanostructures 224A.

The lower semiconductor nanostructures 226L provide channel regions for lower nanostructure-FETs of the CFETs. The upper semiconductor nanostructures 226U provide channel regions for upper nanostructure-FETs of the CFETs. The semiconductor nanostructures 226 that are immediately above/below (e.g., in contact with) the dummy nanostructures 224B may be used for isolation and may or may not act as channel regions for the CFETs. The dummy nanostructures 224B are subsequently replaced with isolation structures. The isolation structures and the dummy nanostructures 224B may define boundaries of the lower nanostructure-FETs and the upper nanostructure-FETs

To form the semiconductor strips 228, layers of the first, second, and third semiconductor materials (arranged as illustrated and described above) may be deposited over the semiconductor substrate 220. The layers of the first, second, and third semiconductor materials may be grown by a process such as Vapor Phase Epitaxy (VPE) or Molecular Beam Epitaxy (MBE), deposited by a process such as Chemical Vapor Deposition (CVD) process or an Atomic Layer deposition (ALD) process, or the like. Then, a patterning process may be applied to the layers of the first, second, and third semiconductor materials as well as the semiconductor substrate 220 to define the semiconductor strips 228, which includes the semiconductor fins 220′, the dummy nanostructure 224, and the semiconductor nanostructures 226. The semiconductor fins and the nanostructures may be patterned by any suitable method. For example, the patterning process may include one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used as an etching mask for the patterning process to etch the layers of the first, second, and third semiconductor materials and the semiconductor substrate 220. The etching may be performed by any acceptable etch process, such as a Reactive Ion Etch (RIE), Neutral Beam Etch (NBE), the like, or a combination thereof. The etching may be anisotropic.

In some embodiments, STI regions (not illustrated in the cross-section A-A′) are formed over the substrate 220 and between adjacent semiconductor strips 228. STI regions may include a dielectric liner and a dielectric material over the dielectric liner. Each of the dielectric liner and the dielectric material may include an oxide such as silicon oxide, a nitride, such as silicon nitride, the like, or a combination thereof. The formation of the STI regions may include depositing the dielectric layer(s), and performing a planarization process such as a CMP process, a mechanical polishing process, or the like to remove excess portions of the dielectric materials. In some embodiments, the CMP process may use a CMP apparatus or method such as described herein for FIGS. 1-16. The deposition processes may include ALD, High-Density Plasma CVD (HDP-CVD), Flowable CVD (FCVD), the like, or a combination thereof. In some embodiments, the STI regions include silicon oxide formed by an FCVD process, followed by an anneal process. Then, the dielectric layers(s) are recessed to define the STI regions. The dielectric layer(s) maybe recessed such that upper portions of semiconductor strips 228 (including multi-layer stacks 222) protrude higher than the remaining STI regions.

After the STI regions are formed, dummy gate stacks 242 may be formed over and along sidewalls of the upper portions of the semiconductor strips 228 (the portions that protrude higher than the STI regions). Forming the dummy gate stacks 242 may include forming dummy dielectric layer 236 is formed on the semiconductor strips 228. Dummy dielectric layer 236 may comprise, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 238 is formed over the dummy dielectric layer 236. The dummy gate layer 238 may be deposited, for example, through Physical Vapor Deposition (PVD), CVD, or other techniques, and then planarized, such as by a CMP process. The material of dummy gate layer 238 be conductive or non-conductive, and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), or the like. A mask layer 240 is formed over the planarized dummy gate layer 238, and may include, for example, silicon nitride, silicon oxynitride, or the like. Next, the mask layer 240 may be patterned through photolithography and etching processes to form a mask, which is then used to etch and pattern dummy gate layer 238, and possibly the dummy dielectric layer 236. The remaining portions of mask layer 240, dummy gate layer 238, and dummy dielectric layer 236 form dummy gate stacks 242.

Further in FIG. 18, gate spacers 244 are formed over the multi-layer stacks 222 and on exposed sidewalls of dummy gate stacks 242. The gate spacers 244 may be formed by conformally forming one or more dielectric layers and subsequently etching the dielectric layers anisotropically. The applicable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which may be formed by a deposition process such as CVD, ALD, or the like.

Source/drain recesses 246 are then formed in the semiconductor strips 228. The source/drain recesses 246 are formed by etching, and may extend through the multi-layer stacks 222 and into the semiconductor strips 220′. The bottom surfaces of the source/drain recesses 246 may be at a level above, below, or level with the top surfaces of the STI regions. In the etching processes, the gate spacers 244 and the dummy gate stacks 242 mask some portions of the semiconductor strips 228. The etching may include a single etch process or multiple etch processes. Timed etch processes may be used to stop the etching of the source/drain recesses 246 upon reaching a desired depth.

In FIG. 19, inner spacers 254 and dielectric isolation layers 256 are formed. Forming inner spacers 254 and dielectric isolation layers 256 may include an etching process that laterally etches the dummy nanostructures 224A and removes the dummy nanostructures 224B. The etching process may be isotropic and may be selective to the material of the dummy nanostructures 224, so that the dummy nanostructures 224 are etched at a faster rate than the semiconductor nanostructures 226. The etching process may also be selective to the material of the dummy nanostructures 224B, so that the dummy nanostructures 224B are etched at a faster rate than the dummy nanostructures 224A. In this manner, the dummy nanostructures 224B may be completely removed from between the lower semiconductor nanostructures 226L (collectively) and the upper semiconductor nanostructures 226U (collectively) without completely removing the dummy nanostructures 224A. In some embodiments where the dummy nanostructures 224B are formed of germanium or silicon germanium with a high germanium atomic percentage, the dummy nanostructures 224A are formed of silicon germanium with a low germanium atomic percentage, and the semiconductor nanostructures 226 are formed of silicon free from germanium, the etch process may comprise a dry etch process using chlorine gas, with or without a plasma. Because the dummy gate stacks 242 wrap around sidewalls of the semiconductor nanostructures 226, the dummy gate stacks 242 may support the upper semiconductor nanostructures 226U so that the upper semiconductor nanostructures 226U do not collapse upon removal of the dummy nanostructures 224B. Further, although sidewalls of the dummy nanostructures 224A are illustrated as being straight after the etching, the sidewalls may be concave or convex

Inner spacers 254 are formed on sidewalls of the recessed dummy nanostructures 224A, and dielectric isolation layers 256 are formed between the upper semiconductor nanostructures 226U (collectively) and the lower semiconductor nanostructures 226L (collectively). As subsequently described in greater detail, source/drain regions are subsequently formed in the source/drain recesses 246, and the dummy nanostructures 224A will be replaced with corresponding gate structures. The inner spacers 254 act as isolation features between the subsequently formed source/drain regions and the subsequently formed gate structures. Further, the inner spacers 254 may be used to prevent damage to the subsequently formed source/drain regions by subsequent etch processes, such as the etch processes used to form gate structures. Dielectric isolation layers 256, on the other hand, are used to isolate the upper semiconductor nanostructures 226U (collectively) from the lower semiconductor nanostructures 226L (collectively). Further, middle semiconductor nanostructures (ones of the semiconductor nanostructures 226 in contact with the dielectric isolation layers 256) and the dielectric isolation layers 256 may define the boundaries of the lower nanostructure-FETs and the upper nanostructure-FETs.

The inner spacers 254 and the dielectric isolation layers 256 may be formed by conformally depositing an insulating material in the source/drain recesses 246, on sidewalls of the dummy nanostructures 224A, and between the upper and lower semiconductor nanostructures 226U and 226L, and then etching the insulating material. The insulating material may be a non-low-k dielectric material, which may be a carbon-containing dielectric material such as silicon oxycarbonitride, silicon oxycarbide, silicon oxynitride, or the like. The insulating material may be formed by a deposition process, such as ALD, CVD, or the like. The etching of the insulating material may be anisotropic or isotropic. The insulating material, when etched, has portions remaining on the sidewalls of the dummy nanostructures 224A (thus forming the inner spacers 254) and has portions remaining in between the upper and lower semiconductor nanostructures 226U and 226L (thus forming the dielectric isolation layers 256).

As also illustrated by FIG. 19, lower and upper epitaxial source/drain regions 262L and 262U are formed. The lower epitaxial source/drain regions 262L are formed in the lower portions of the source/drain recesses 246. The lower epitaxial source/drain regions 262L are in contact with the lower semiconductor nanostructures 226L and are not in contact with the upper semiconductor nanostructures 226U. Inner spacers 254 electrically insulate the lower epitaxial source/drain regions 262L from the dummy nanostructures 224A, which are replaced with replacement gates in subsequent processes.

The lower epitaxial source/drain regions 262L are epitaxially grown, and have a conductivity type that is suitable for the device type (p-type or n-type) of the lower nanostructure-FETs. When lower epitaxial source/drain regions 262L are n-type source/drain regions, the respective material may include silicon or carbon-doped silicon, which is doped with an n-type dopant such as phosphorous, arsenic, or the like. When lower epitaxial source/drain regions 262L are p-type source/drain regions, the respective material may include silicon or silicon germanium, which is doped with a p-type dopant such as boron, indium, or the like. The lower epitaxial source/drain regions 262L may be in-situ doped, and may be, or may not be, implanted with the corresponding p-type or n-type dopants. During the epitaxy of the lower epitaxial source/drain regions 262L, the upper semiconductor nanostructures 226U may be masked to prevent undesired epitaxial growth on the upper semiconductor nanostructures 226U. After the lower epitaxial source/drain regions 262L are grown, the masks on the upper semiconductor nanostructures 226U may then be removed. As a result of the epitaxy processes used for forming the lower epitaxial source/drain regions 262L, upper surfaces of the lower epitaxial source/drain regions 262L have facets which expand laterally outward beyond sidewalls of the multi-layer stacks 22. In some embodiments, adjacent lower epitaxial source/drain regions 262L remain separated after the epitaxy process is completed. In other embodiments, these facets cause neighboring lower epitaxial source/drain regions 262L of a same FET to merge.

A first contact etch stop layer (CESL) 266 and a first ILD 268 are formed over the lower epitaxial source/drain regions 262L. The first CESL 266 may be formed of a dielectric material having a high etching selectivity from the etching of the first ILD 268, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which may be formed by any suitable deposition process, such as CVD, ALD, or the like. The first ILD 268 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The applicable dielectric material of the first ILD 268 may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), silicon oxide, or the like.

The formation processes may include depositing a conformal CESL layer, depositing a material for the first ILD 268, followed by a planarization process and then an etch-back process. In some embodiments, the planarization process may use a CMP apparatus or method such as described herein for FIGS. 1-16. In some embodiments, the first ILD 268 is etched first, leaving the first CESL 266 unetched. An anisotropic etching process is then performed to remove the portions of the first CESL 266 higher than the recessed first ILD 268. After the recessing, the sidewalls of the upper semiconductor nanostructures 226U are exposed.

Upper epitaxial source/drain regions 262U are then formed in the upper portions of the source/drain recesses 246. The upper epitaxial source/drain regions 262U may be epitaxially grown from exposed surfaces of the upper semiconductor nanostructures 226U. The materials of upper epitaxial source/drain regions 262U may be selected from the same candidate group of materials for forming lower source/drain regions 262L, depending on the desired conductivity type of upper epitaxial source/drain regions 262U. The conductivity type of the upper epitaxial source/drain regions 262U may be opposite the conductivity type of the lower epitaxial source/drain regions 262L. For example, the upper epitaxial source/drain regions 262U may be oppositely doped from the lower epitaxial source/drain regions 262L. The upper epitaxial source/drain regions 262U may be in-situ doped, and/or may be implanted, with an n-type or p-type dopant. Adjacent upper source/drain regions 262U may remain separated after the epitaxy process or may be merged.

After the epitaxial source/drain regions 262U are formed, a second CESL 270 and a second ILD 272 are formed. The materials and the formation methods may be similar to the materials and the formation methods of first CESL 266 and first ILD 268, respectively, and are not discussed in detail herein. The formation process may include depositing the layers for CESL 270 and ILD 272, and performing a planarization process, such as a CMP process, to remove the excess portion of the corresponding layers. In some embodiments, the CMP process may use a CMP apparatus or method such as described herein for FIGS. 1-16. In other embodiments, the planarization process removes the mask layers 240.

In some embodiments, hard masks 273 may be formed on the second ILD 272. The hard masks 273 may be formed, for example, by recessing the second ILD 272 using a suitable etching process, and then depositing the material of the hard masks 273 on the second ILD 272. The hard mask material may be a suitable dielectric material such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, or the like.

The hard mask material may be deposited using a suitable technique, such as ALD, CVD, or the like. A planarization process, such as a CMP process, may be performed to remove excess hard mask material. In some embodiments, the CMP process may use a CMP apparatus or method such as described herein for FIGS. 1-16. In some embodiments, the hard masks 273 may act as CMP stop layers for subsequent planarization processes.

FIGS. 20 through 24 illustrate a replacement gate process to replace the dummy gate stacks 242 and the dummy nanostructures 224A with replacement gate stacks 290. Referring to FIG. 20, the replacement gate process includes first removing the dummy gate stacks 242 and the remaining portions of the dummy nanostructures 224A. The dummy gate stacks 242 are removed in one or more etching processes, so that recesses are defined between the gate spacers 244 and the upper portions of the semiconductor strips 228 are exposed. The remaining portions of the dummy nanostructures 224A are then removed by etching, so that the recesses extend between the semiconductor nanostructures 226. In the etching process, the dummy nanostructures 224A are etched at a faster rate than the semiconductor nanostructures 226, the dielectric isolation layers 256, and the inner spacers 254. The etching may be isotropic. For example, when the dummy nanostructures 224A are formed of silicon-germanium, and the semiconductor nanostructures 226 are formed of silicon, the etch process may include a wet etch process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH₄OH), or the like.

Then, gate dielectrics 278 are deposited in the recesses between the gate spacers 244 and on the exposed semiconductor nanostructures 226. The gate dielectrics 278 are conformally formed on the exposed surfaces of the recesses (the removed gate stacks 242 and the dummy nanostructures 224A) including the semiconductor nanostructures 226 and the gate spacers 244. In some embodiments, the gate dielectrics 278 wrap around all (e.g., four) sides of the semiconductor nanostructures 226. Specifically, the gate dielectrics 278 may be formed on the top surfaces of the semiconductor fins 220′; on the top surfaces, the sidewalls, and the bottom surfaces of the semiconductor nanostructures 226; and on the sidewalls of the gate spacers 244. The gate dielectrics 278 may include an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, combinations thereof, multi-layers thereof, or the like. The gate dielectrics 278 may include a high-dielectric constant (high-k) material having a k-value greater than about 7.0, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

The formation methods of the gate dielectrics 278 may include molecular-beam deposition (MBD), ALD, PECVD, and the like followed by a planarization process (e.g., a CMP) to remove portions of the gate dielectrics 278 above the second ILD 272. Although single-layered gate dielectrics 278 are illustrated, the gate dielectrics 278 may include multiple layers, such as an interfacial layer and an overlying high-k dielectric layer.

As illustrated in FIG. 20, the lower electrode material 274 is formed on the gate dielectrics 278 around the lower semiconductor nanostructures 226L and the upper semiconductor nanostructures 226U. For example, the lower electrode material 274 wraps around the lower semiconductor nanostructures 226L and the upper semiconductor nanostructures 226U at this step in the process. Subsequently, the lower electrode material 274 is removed from the upper semiconductor nanostructures 226U. The lower electrode material 274 may be formed of a metal-containing material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multi-layers thereof, or the like. Although single-layered gate electrodes are illustrated, the lower electrode material 274 may include any number of work function tuning layers, any number of barrier layers, any number of glue layers, and a fill material.

The lower electrode material 274 are formed of material(s) that are suitable for the device type of the lower nanostructure-FETs. For example, the lower electrode material 274 may include one or more work function tuning layer(s) formed of material(s) that are suitable for the device type of the lower nanostructure-FETs. In some embodiments, the lower electrode material 274 includes an n-type work function tuning layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, or the like. In some embodiments, the lower electrode material 274 includes a p-type work function tuning layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, or the like. Additionally or alternatively, the lower electrode material 274 may include a dipole-inducing element that is suitable for the device type of the lower nanostructure-FETs. Acceptable dipole-inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

In FIG. 21, a planarization process is performed to remove upper portions of the lower electrode material 274, in accordance with some embodiments. In some embodiments, upper portions of the lower electrode material 274 and the CESL 270 are removed such that the planarization process stops on the mask layers 273, as shown in FIG. 21. Accordingly, the mask layers 273 may act as CMP stop layers. In other embodiments, the planarization process stops on the CESL 270, and accordingly the CESL 270 acts as a CMP stop layer. In some embodiments, the CMP process may use a CMP apparatus or method such as described herein for FIGS. 1-16. For example, the techniques described herein may allow for monitoring of the removal of the lower electrode material 274 such that the CMP process can be stopped when the mask layers 273 (or the CESL 270) are exposed. In this manner, loss of the mask layers 273 (or the CESL 270) can be reduced. The techniques described herein can allow for more precise stopping of the planarization process and more uniform topography after planarization, which can improve the uniformity and control of the subsequent recessing of the lower electrode material 274, described below. In some cases, the planarization techniques described herein can reduce over-etching or under-etching during recessing of the lower electrode material 274.

In FIG. 22, the lower electrode material 274 is recessed, with the remaining lower electrode material 274 forming the lower gate electrodes 280L. The lower electrode material 274 may be recessed such that top surfaces of the remaining lower electrode material 274 is approximately aligned to the dielectric isolation layers 256. For example, top surfaces of the lower electrode material 274 may be approximately level with the position 277 indicated in FIG. 22, though other positions are possible. The recessing process may include any acceptable etch process, such as a dry etch, a wet etch, the like, or a combination thereof, may be performed to recess the gate electrode layer(s). The etching may be isotropic. Etching the lower gate electrodes 280L may expose the upper semiconductor nanostructures 226U. In some embodiments, the lower gate electrodes 280L wrap around the lower semiconductor nanostructures 226L.

In some embodiments, isolation layers (not explicitly illustrated) may be optionally formed on the lower gate electrodes 280L. The isolation layers act as isolation features between the lower gate electrodes 280L and subsequently formed upper gate electrodes 280U. The isolation layers may be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or the like) and subsequently recessing the dielectric material to expose the upper semiconductor nanostructures 226U.

In FIG. 23, upper electrode material 276 is formed on the isolation layers described above (if present) or on the lower gate electrodes 280L. In some embodiments, the upper electrode material 276 wraps around the upper semiconductor nanostructures 226U. The upper electrode material 276 may be formed of the same candidate materials and candidate processes for forming the lower gate electrodes 280L. The upper electrode material 276 is formed of material(s) that are suitable for the device type of the upper nanostructure-FETs. For example, the upper electrode material 276 may include one or more work function tuning layer(s) formed of material(s) that are suitable for the device type of the upper nanostructure-FETs. Although single-layered upper electrode material 276 is illustrated, the upper electrode material 276 may include any number of work function tuning layers, any number of barrier layers, any number of glue layers, and a fill material.

In FIG. 24, a removal process is performed to remove upper portions of the upper electrode material 276, with the remaining upper electrode material 276 forming the upper gate electrodes 280U. The upper gate electrodes 280U are disposed between and wrap around the upper semiconductor nanostructures 226U. In some embodiments, a planarization process such as a CMP, an etch-back process, combinations thereof, or the like may be utilized. The planarization process may remove the mask layers 273, in some embodiments. After the planarization process, the top surfaces of the upper gate electrodes 280U, the gate dielectrics 278, the second ILD 272, and the gate spacers 244 may be substantially level or coplanar (within process variations). In some embodiments, the CMP process may use a CMP apparatus or method such as described herein for FIGS. 1-16. For example, the techniques described herein may allow for monitoring of the removal of the lower electrode material 274 such that the CMP process can be stopped when the second ILD 272 are exposed. The techniques described herein can allow for more precise stopping of the planarization process and more uniform topography.

Each respective pair of a gate dielectric 278 and a gate electrode 280 (including an upper gate electrode 280U and/or a lower gate electrode 280L) may be collectively referred to as a “gate structure” 290 (including upper gate structures 290U and lower gate structures 290L). Each gate structure 290 extends along three sides (e.g., a top surface, a sidewall, and a bottom surface) of a channel region of a semiconductor nanostructure 226. The lower gate structures 290L may also extend along sidewalls and/or a top surface of a semiconductor fin 220′.

In FIG. 25, additional processing steps are performed on the CFET structure, in accordance with some embodiments. Silicide regions 294 and source/drain contact plugs 296U are formed through the second ILD 272 to electrically couple to the upper epitaxial source/drain regions 262U and/or the lower epitaxial source/drain regions 262L. An etch stop layer (ESL) 304 and a third ILD 306 are the formed. In some embodiments, The ESL 304 may include a dielectric material having a high etching selectivity from the etching of the third ILD 306, such as, aluminum oxide, aluminum nitride, silicon oxycarbide, or the like. The third ILD 306 may be formed using flowable CVD, ALD, or the like, and the material may include PSG, BSG, BPSG, USG, or the like, which may be deposited by any suitable method, such as CVD, PECVD, or the like.

As also shown in FIG. 25, gate masks 292 are formed over the gate structures 290. The formation process may include recessing gate structures 290, filling the resulting recesses with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like, and performing a planarization process to remove the excess portions of the dielectric material over the second ILD 272.

Upper gate contact plugs 308 and source/drain contact plugs 310 are formed to contact the upper gate electrodes 280U and the upper source/drain contact plugs 296U, respectively. The active devices as illustrated are collectively referred to as a device layer 312.

A front-side interconnect structure 314 is formed on the device layer 312. The front-side interconnect structure 314 includes dielectric layers 316 and layers of conductive features 318/320 in the dielectric layers 316. The dielectric layers 316 may include low-k dielectric layers formed of low-k dielectric materials. The dielectric layers 316 may further include passivation layers, which are formed of non-low-k and dense dielectric materials such as Undoped Silicate-Glass (USG), silicon oxide, silicon nitride, or the like, or combinations thereof over the low-k dielectric materials. The dielectric layers 316 may also include polymer layers.

The conductive features 318/320 may include conductive lines 318 and vias 320, which may be formed using damascene processes. Conductive features 318/320 may include metal lines 318 and metal vias 320, which includes diffusion barriers and a copper containing material over the diffusion barriers. There may also be aluminum pads over and electrically connected to the metal lines and vias. Depending on how the respective die is to be packaged, the top surface features among the conductive features 318 may include bond pads, metal pillars, solder regions, and/or the like.

In some embodiments, a backside interconnect structure may be formed. The backside interconnect structure may provide electrical connection with the lower gate stacks 290L and the lower source/drain regions 262L through a backside of the device layer 312 (e.g., a side opposite to the front-side interconnect structure 314). The backside interconnect structure may be similar to the front-side interconnect structure 314 described above the description is not repeated herein. In some embodiments, the connection to the lower gate stacks 290L and the lower source/drain regions 282L be made by contacts (sometimes referred to as contact plugs) and the backside interconnect structure may be omitted. In some embodiments, forming the backside interconnect structure comprises thinning the semiconductor substrate 220 using a planarization process, which may be similar to the CMP apparatus and method described herein for FIGS. 1-16.

In some embodiments, multiple CFET structures are formed on a wafer, which is subsequently singulated into individual dies. The wafer may be similar to the semiconductor substrate 220, in some cases. The singulation process may include a sawing process, a laser process, an etching process, or a combination thereof. The CFET structure described for FIGS. 17-25 is an example, and other configurations or process steps are possible. The CMP apparatus and method described herein can allow for improved uniformity and yield for formation of a CFET structure or for formation of any other suitable structure or device.

Embodiment may achieve advantages. The embodiments described herein can allow for the in situ inspection of a workpiece (e.g., a wafer) during planarization of the workpiece. The planarization may include a polishing process, such as a CMP process. Accordingly, the embodiments described herein may be utilized within a CMP tool or the like. By forming inspection holes extending through the polishing pad, optical inspection systems underneath the polishing pad can inspect the bottom surface of the workpiece during the planarization process. For example, the optical inspection systems can measure thicknesses of a bottom layer of the workpiece, or determine when a bottom layer of the workpiece has been removed. This can allow for more accurate and reliable layer thinning or layer removal. For example, measuring the reflected spectrum of light from the workpiece can allow a CMP tool or operator to determine when a layer (e.g., an etch stop layer or another type of layer) has been partially or fully removed. The planarization process can then be more accurately or quickly stopped (e.g., the workpiece removed from the polishing pad) after the last desired layer has been removed. In some cases, the embodiments described herein can reduce unwanted layer loss or can eliminate the need for a CMP stop layer.

By having the inspection holes include portions of grooves in a top pad, the effects of the inspection holes on the planarization process can be minimized. In this manner, fewer defects may be introduced during planarization. In some embodiments, the polishing pad may include a transparent layer that reduces the effect of slurry during optical inspection. The embodiments described herein can allow for a larger number or density of optical inspection systems, which can allow for more accurate and more detailed inspection of the workpiece during planarization. Many variations of grooves, inspection holes, and optical inspection systems are possible, allowing for improved process flexibility and compatibility with application-specific needs.

In accordance with an embodiment, a system includes a platen configured to hold a polishing pad, wherein the polishing pad includes grooves in a top surface of the polishing pad and openings extending from the grooves to a bottom surface of the polishing pad; a holder configured to hold a workpiece above the polishing pad; and optical inspection devices within the platen, wherein the optical inspection devices are configured to measure a characteristic of a bottom surface of the workpiece through the openings in the polishing pad. In an embodiment, the polishing pad includes a transparent layer extending across the openings. In an embodiment, the characteristic is a thickness of a bottom layer of the workpiece. In an embodiment, the grooves are in concentric circles. In an embodiment, the grooves are in a spiral arrangement. In an embodiment, the optical inspection devices are configured to rotate with the platen. In an embodiment, each optical inspection devices includes a light source and a light sensor. In an embodiment, each opening extends over more than one optical inspection device.

In accordance with an embodiment, an apparatus includes a platen configured to rotate, wherein the platen includes optical inspection systems, wherein each optical inspection system respectively includes a light source and a light sensor; and a polishing pad attached to the platen, wherein the polishing pad includes a first pad that includes first apertures extending through the first pad, wherein each first aperture is aligned to at least one optical inspection system; and a second pad on the first pad, wherein the second pad includes second apertures extending through the second pad, wherein each second aperture is aligned to at least one first aperture; and first grooves in a top side of the second pad opposite the first pad, wherein each first groove extends over at least one second aperture. In an embodiment, the second pad includes second grooves in the top side, wherein the second grooves are separated from the second apertures. In an embodiment, the first apertures and the second apertures have a same width. In an embodiment, the first apertures and the second apertures have different widths. In an embodiment, at least one second aperture extends over multiple optical inspection systems. In an embodiment, the light source is a broadband light source. In an embodiment, the light sensor is a spectrometer.

In accordance with an embodiment, a method includes attaching a polishing pad to a platen, wherein the platen includes light sources and optical detectors, wherein the polishing pad includes holes; placing a wafer on the polishing pad, wherein the wafer includes a gate structure over multiple nanostructures; rotating the polishing pad to polish the wafer; while rotating the polishing pad, emitting light from the light sources through the holes toward the wafer, and, using the optical detectors, detecting light reflected from the wafer through the holes toward the optical detectors; and singulating the wafer into multiple dies. In an embodiment, the method includes, based on the light detected by the optical detectors, determining a thickness of a bottom layer of the wafer. In an embodiment, the method includes, based on the thickness, stopping rotation of the polishing pad. In an embodiment, polishing the wafer includes polishing a surface of the gate structure. In an embodiment, the polishing pad includes grooves aligned to the holes.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein.

Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.