Assignee profile:

SPRINGSOFT INC.

City:

Hsinchu

Country:

Taiwan

Published Applications:

35

Last publication date:

2014-03-06

Patent Grants:

35

Last grant date:

2014-10-28

Top Inventors for applications by SPRINGSOFT INC.

These are the the leading inventors for applications assigned to SPRINGSOFT INC.:

Recent patent applications by SPRINGSOFT INC.

SPRINGSOFT INC. based in Hsinchu, TW has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:

#1 | 2014-03-06 ✅ Patent 8,875,081 granted on 2014-10-28
US20140068542A1
Physics

Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio

#2 | 2013-02-21 ✅ Patent 8,671,383 granted on 2014-03-11
US20130047134A1
Physics

Viewing and debugging HDL designs having SystemVerilog interface constructs

#3 | 2012-10-23 ✅ Patent 8,296,708 granted on 2012-10-23
US13349584
-

Method of constraint-hierarchy-driven IC placement

#4 | 2012-09-20 ✅ Patent 9,053,264 granted on 2015-06-09
US20120239370A1
Physics

What-if simulation methods and systems

#5 | 2012-05-31 ✅ Patent 8,561,000 granted on 2013-10-15
US20120137265A1
Physics

Multiple level spine routing

#6 | 2012-05-31 ✅ Patent 8,561,002 granted on 2013-10-15
US20120137264A1
Physics

Multiple level spine routing

#7 | 2012-04-05 ✅ Patent 8,359,560 granted on 2013-01-22
US20120084744A1
Physics

Methods and systems for debugging equivalent designs described at different design levels

#8 | 2012-03-15 ✅ Patent 8,789,008 granted on 2014-07-22
US20120066659A1
Physics

Methods for generating device layouts by combining an automated device layout generator with a script

#9 | 2011-12-29 ✅ Patent 8,365,132 granted on 2013-01-29
US20110320991A1
Physics

Hierarchial power map for low power design

#10 | 2011-12-08 ✅ Patent 8,359,559 granted on 2013-01-22
US20110302541A1
Physics

Methods and systems for evaluating checker quality of a verification environment

#11 | 2011-11-17 ✅ Patent 8,522,176 granted on 2013-08-27
US20110283247A1
Physics

Method of recording and replaying call frames for the testbench

#12 | 2011-10-13 ✅ Patent 8,255,853 granted on 2012-08-28
US20110251836A1
Physics

Circuit emulation systems and methods

#13 | 2011-08-18 ✅ Patent 8,261,223 granted on 2012-09-04
US20110202897A1
Physics

Hierarchy-based analytical placement method capable of macro rotation within an integrated circuit

#14 | 2011-08-18 ✅ Patent 8,281,280 granted on 2012-10-02
US20110202894A1
Physics

Method and apparatus for versatile controllability and observability in prototype system

#15 | 2011-06-23 ✅ Patent 8,407,647 granted on 2013-03-26
US20110154282A1
Physics

Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio

#16 | 2011-05-05 ✅ Patent 8,336,001 granted on 2012-12-18
US20110107278A1
Physics

Method for improving yield rate using redundant wire insertion

#17 | 2009-11-19 ✅ Patent 7,970,597 granted on 2011-06-28
US20090287468A1
Physics

Event-driven emulation system

#18 | 2009-07-23 ✅ Patent 7,895,027 granted on 2011-02-22
US20090187394A1
Physics

HDL re-simulation from checkpoints

#19 | 2009-04-30 ✅ Patent 7,877,718 granted on 2011-01-25
US20090113367A1
Physics

Analog IC placement using symmetry-islands

#20 | 2009-01-29 ✅ Patent 7,984,410 granted on 2011-07-19
US20090031269A1
Physics

Hierarchy-based analytical placement method for an integrated circuit

#21 | 2008-10-09 ✅ Patent 7,703,054 granted on 2010-04-20
US20080250378A1
Physics

Circuit emulation and debugging method

#22 | 2008-06-26 ✅ Patent 7,603,640 granted on 2009-10-13
US20080155485A1
Physics

Multilevel IC floorplanner

#23 | 2008-04-17 ✅ Patent 7,739,646 granted on 2010-06-15
US20080092099A1
Physics

Analog and mixed signal IC layout system

#24 | 2007-12-13 ✅ Patent 7,779,379 granted on 2010-08-17
US20070288878A1
Physics

Template-based gateway model routing system

#25 | 2007-12-13 ✅ Patent 7,461,310 granted on 2008-12-02
US20070288818A1
Physics

IC functional and delay fault testing

#26 | 2007-02-13 ✅ Patent 7,178,114 granted on 2007-02-13
US10863122
-

Scripted, hierarchical template-based IC physical layout system

#27 | 2007-01-25 ✅ Patent 7,386,823 granted on 2008-06-10
US20070022399A1
Physics

Rule-based schematic diagram generator

#28 | 2006-08-24 ✅ Patent 7,310,786 granted on 2007-12-18
US20060190847A1
Physics

IC compaction system

#29 | 2006-06-22 ✅ Patent 7,257,794 granted on 2007-08-14
US20060136856A1
Physics

Unit-based layout system for passive IC devices

#30 | 2006-04-27 ✅ Patent 7,178,123 granted on 2007-02-13
US20060090152A1
Physics

Schematic diagram generation and display system

#31 | 2006-03-14 ✅ Patent 7,013,457 granted on 2006-03-14
US9682140
-

Prioritized debugging of an error space in program code

#32 | 2006-01-19 ✅ Patent 7,366,652 granted on 2008-04-29
US20060015313A1
Physics

Method of programming a co-verification system

#33 | 2005-12-27 ✅ Patent 6,980,211 granted on 2005-12-27
US10064035
-

Automatic schematic diagram generation using topology information

#34 | 2005-07-19 ✅ Patent 6,920,620 granted on 2005-07-19
US10160690
-

Method and system for creating test component layouts

#35 | 2005-06-16 ✅ Patent 7,283,944 granted on 2007-10-16
US20050131666A1
Physics

Circuit simulation bus transaction analysis

AssigneeID:

10768 ⎘