Semiconductor package having unified semiconductor chips

Enhanced capture pads for through semiconductor vias

Semiconductor device

Flexible routing for chip on board applications

Semiconductor device and fabrication method

Semiconductor packaging structure and method for forming the same

Semiconductor IC packaging methods and structures

Integrated circuit device including a copper pillar capped by barrier layer and method of forming the same

Stud bump structure and method for manufacturing the same

Semiconductor device with conductive vias

Method and system for controlling chip inclination during flip-chip mounting

Semiconductor packaging structure and method

Integrated circuit chips having vertically extended through-substrate vias therein

Method and apparatus for sharing internal power supplies in integrated circuit devices

Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip

Interconnection structure

Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices

Bump interconnection techniques

Glass carrier with embedded semiconductor device and metal layers on the top surface

Semiconductor module

Integrated antennas in wafer level package

Backside bulk silicon MEMS

Bond pad structure and method of manufacturing the same

Electrical connection for chip scale packaging

Al bond pad clean method

Semiconductor device and method for manufacturing thereof

System in package manufacturing method using wafer-to-wafer bonding

Wafer carrier having cavity

TSV formation

Semiconductor device and method of making TSV interconnect structures using encapsulant for structural support

Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate

Embedding thin chips in polymer

Embedded chip packages and methods for manufacturing an embedded chip package

Semiconductor dies with reduced area consumption

Metal bump joint structure

Routing layer for mitigating stress in a semiconductor die

Packaging devices, methods of manufacture thereof, and packaging methods

Bump package and methods of formation thereof

Cylindrical embedded capacitors

System and process for fabricating semiconductor packages

Semiconductor device

Semiconductor device

Cooling channels in 3DIC stacks

Stub minimization for assemblies without wirebonds to package substrate

Semiconductor device and method of forming a PoP device with embedded vertical interconnect units

Self-aligned protection layer for copper post structure

Semiconductor device and a method of manufacturing the same

Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs

Semiconductor device and method of forming conductive ink layer as interconnect structure between semiconductor packages

Semiconductor device

Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability

Illumination device capable of decreasing shadow of lighting effect

Package structure and method for manufacturing package structure

Two-sided-access extended wafer-level ball grid array (eWLB) package, assembly and method

Thermally enhanced package-on-package (PoP)

Semiconductor package and method for fabricating the same

Embedded structures for package-on-package architecture

Semiconductor device with stacked semiconductor chips

Localized high density substrate routing

Three dimensional integrated circuits stacking approach

Apparatus and method for a component package

Semiconductor chip stack having improved encapsulation

Semiconductor device and method of using a standardized carrier in semiconductor packaging

IC wafer having electromagnetic shielding effects and method for making the same

Chip package and method of manufacturing the same

Solid-state image pickup element and solid-state image pickup element mounting structure

Method of fabricating a wafer level chip scale package without an encapsulated via

Microelectronic structures having laminated or embedded glass routing structures for high density packaging

Method for fabricating glass substrate package

Semiconductor devices and methods of fabricating the same

Contact bumps methods of making contact bumps

Multiple die packaging interposer structure and method

Bump structures having an extension

Semiconductor packages, methods of manufacturing semiconductor packages, and systems including semiconductor packages

Direct multiple substrate die assembly

Processes for multi-layer devices utilizing layer transfer

Thermal dissipation through seal rings in 3DIC structure

Thermal dissipation through seal rings in 3DIC structure

Semiconductor device with dummy metal protective structure around semiconductor die for localized planarization of insulating layer

Semiconductor devices having back side bonding structures

Integrated circuit, a chip package and a method for manufacturing an integrated circuit

Integrated circuit device

Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package

Semiconductor package device having passive energy components

Through via structure and method

Structures having a tapering curved profile and methods of making same

Post passivation interconnect structures and methods for forming the same

THREE-DIMENSIONAL SEMICONDUCTOR PACKAGE DEVICE HAVING ENHANCED SECURITY

Microelectronic packages with nanoparticle joining

Semiconductor device with protective layer over exposed surfaces of semiconductor die

Passive devices in package-on-package structures and methods for forming the same

Packages with passive devices and methods of forming the same

Hybrid on-chip and package antenna

Charge sharing testing of through-body-vias

Interconnect assemblies with probed bond pads

Integrated circuit devices including a via structure and methods of fabricating integrated circuit devices including a via structure

Semiconductor device with discrete blocks

Chip to package interface

Semiconductor device and method of forming multi-layered UBM with intermediate insulating buffer layer to reduce stress for semiconductor wafer

Plating structure for wafer level packages

Stress reduction apparatus

Extrusion-resistant solder interconnect structures and methods of forming

Flip-chip package structure and method for an integrated switching power supply

Bridge interconnect with air gap in package assembly

Semiconductor device

Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits

Manufacturing method for micro bump structure

Method of manufacturing semiconductor device

Semiconductor device with pre-molding chip bonding

Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in FO-WLCSP

Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits

Semiconductor device and method of manufacturing the same

Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits

GOLD BONDING IN SEMICONDUCTOR DEVICES USING POROUS GOLD

Semiconductor structure and method of manufacturing the same

Semiconductor package with improved redistribution layer design and fabricating method thereof

Metal pads with openings in integrated circuits

Bump structures for semiconductor package

Interfacial alloy layer for improving electromigration (EM) resistance in solder joints

Three dimensional (3D) fan-out packaging mechanisms

Stacked die power converter

Semiconductor chip and semiconductor package having the same

Chip package and a method for manufacturing a chip package

Method and apparatus for routing die signals using external interconnects

Lead-free solder ball

Methods and apparatus of packaging semiconductor devices

METHOD FOR MAKING A DOUBLE-SIDED FANOUT SEMICONDUCTOR PACKAGE WITH EMBEDDED SURFACE MOUNT DEVICES, AND PRODUCT MADE

Semiconductor device and method of forming RDL using UV-cured conductive ink over wafer level package

Method for manufacturing a metal pad structure of a die, a method for manufacturing a bond pad of a chip, a die arrangement and a chip arrangement

Chip package

Semiconductor device having a copper plug

Semiconductor device with copper wirebond sites and methods of making same

Devices for metallization

Method for self-assembly of substrates and devices obtained thereof

Terminal structure, and semiconductor element and module substrate comprising the same

Terminal structure and semiconductor device

Terminal structure and semiconductor device

Semiconductor package having protective layer with curved surface and method of manufacturing same

Package-on-package semiconductor device

Semiconductor device and electronic device

Method of manufacturing electronic component module and electronic component module

Multi-chip semiconductor apparatus

Microelectronic package having non-coplanar, encapsulated microelectronic devices and a bumpless build-up layer

Pad sidewall spacers and method of making pad sidewall spacers

Stacked microelectronic assembly with TSVS formed in stages with plural active chips

Interconnect substrate with embedded semiconductor device and built-in stopper and method of making the same

Contact pads with sidewall spacers and method of making contact pads with sidewall spacers

Solder on trace technology for interconnect attachment

Bonded structures for package and substrate

Semiconductor package having a recess filled with a molding compound

Semiconductor package for high power devices

EM protected semiconductor die

Semiconductor substrate assembly

Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units

Hybrid wiring board with built-in stopper, interposer and build-up circuitry

Package assembly and methods for forming the same

Interposer system and method

Semiconductor devices including a non-planar conductive pattern, and methods of forming semiconductor devices including a non-planar conductive pattern

Controlled collapse chip connection (C4) structure and methods of forming

Fine Pitch Package-on-Package Structure

Package on package devices and methods of forming same

Semiconductor device and method of manufacturing the same

Package structure and the method to fabricate thereof

Multi-chip stacking of integrated circuit devices using partial device overlap

Semiconductor package and manufacturing method thereof

PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF

Packaging structures and methods with a metal pillar

Integrated system and method of making the integrated system

Multiple surface integrated devices on low resistivity substrates

PASSIVES VIA BAR

Bonding pad for thermocompression bonding, process for producing a bonding pad and component

Chip package and a method for manufacturing a chip package

Reconstituted wafer-level package DRAM

Metal cored solder decal structure and process

Bump on pad (BOP) bonding structure

Embedded package security tamper mesh

Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages

Semiconductor devices having stacked solder bumps with intervening metal layers to provide electrical interconnections

Method of fabricating a chip package

SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF

SEMICONDUCTOR MANUFACTURING METHOD, SEMICONDUCTOR STRUCTURE AND PACKAGE STRUCTURE THEREOF

Power device integration on a common substrate

Semiconductor package and method of fabricating the same

Production of adhesion structures in dielectric layers using photoprocess technology and devices incorporating adhesion structures

Repairing anomalous stiff pillar bumps

Bump structure for yield improvement

Reconstituted wafer package with high voltage discrete active dice and integrated field plate for high temperature leakage current stability

Three-dimensional integrated circuit laminate, and interlayer filler for three-dimensional integrated circuit laminate

Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias

Integrated circuit device having through-silicon-via structure

Semiconductor package and method of fabricating the same

Mounting structure of semiconductor device and method of manufacturing the same

Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections

Semiconductor device and manufacturing method of same

Solder volume compensation with C4 process

Control of silver in C4 metallurgy with plating process

Semiconductor manufacturing method and semiconductor structure thereof

Redistribution layer (RDL) with variable offset bumps

Methods and arrangements relating to semiconductor packages including multi-memory dies

Wafer-level device packaging

Multi-chip package and method of manufacturing the same

Backside processing of semiconductor devices

Stacked fan-out semiconductor chip

SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE USING THE SAME

Semiconductor package and method of fabricating the same

Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods

Method of forming post passivation interconnects

Chip package comprising alignment mark and method for forming the same

Passivation layer for packaged chip

Substrate, method of manufacturing substrate, semiconductor device, and electronic apparatus

Semiconductor device

Semiconductor packages and methods of forming the same

Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material

Integrating through substrate vias from wafer backside layers of integrated circuits

Method of manufacturing semiconductor packaging

Method of forming 3D integrated microelectronic assembly with stress reducing interconnects

3DIC stacking device and method of manufacture

Semiconductor device having silicon interposer on which semiconductor chip is mounted

Method for manufacturing a chip package

Integrated WLUF and SOD process

MICROELECTRONIC STRUCTURE HAVING A MICROELECTRONIC DEVICE DISPOSED BETWEEN AN INTERPOSER AND A SUBSTRATE

CHIP PACKAGES, CHIP ARRANGEMENTS, A CIRCUIT BOARD, AND METHODS FOR MANUFACTURING CHIP PACKAGES

Multiple die packaging interposer structure and method

Semiconductor structure with thin film resistor and terminal bond pad

METHOD TO INHIBIT METAL-TO-METAL STICTION ISSUES IN MEMS FABRICATION

Insulated gate semiconductor device

Method for manufacturing semiconductor device

Method of fabricating wafer level package

Substrate structure and semiconductor package using the same

Method to enable controlled side chip interconnection for 3D integrated packaging system

Integrated circuit package having offset vias

Integrated circuit packages and methods for forming the same

Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection

Semiconductor device and method of manufacturing the same, and wiring substrate and method of manufacturing the same

Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same

SEMICONDUCTOR CHIP WITH EXPANSIVE UNDERBUMP METALLIZATION STRUCTURES

Semiconductor device and method of forming an embedded SOP fan-out package

Hybrid low metal loading flux

Three-dimensional integrated structure comprising an antenna

Method for manufacturing a chip package, a method for manufacturing a wafer level package, a chip package and a wafer level package

Microelectronic assembly tolerant to misplacement of microelectronic elements therein

Integrated circuit packaging system with through silicon via and method of manufacture thereof

Bumpless build-up layer package design with an interposer

Bonding package components through plating

SUBSTRATE STRUCTURE AND PACKAGE STRUCTURE

Electronic device packages having bumps and methods of manufacturing the same

Embedded packages including a multi-layered dielectric layer and methods of manufacturing the same

Current sensing using a metal-on-passivation layer on an integrated circuit die

Electrical interconnection structures including stress buffer layers

LED having vertical contacts redistruted for flip chip mounting

Calibration kits for RF passive devices

Three dimensional flip chip system and method

Die edge contacts for semiconductor devices

Semiconductor package and manufacturing method thereof

CTE ADAPTION IN A SEMICONDUCTOR PACKAGE

Methods and apparatus of packaging semiconductor devices

Reduced stress TSV and interposer structures

Wafer-level flip chip device packages and related methods

Power semiconductor device and method therefor

THREE DIMENSIONAL FLIP CHIP SYSTEM AND METHOD

Semiconductor apparatus comprised of two types of transistors

Semiconductor device

Chip package and method for forming the same

System-level packaging methods and structures

Chip package and method for forming the same

Semiconductor device with redistributed contacts

Reactive bonding of a flip chip package

Coaxial solder bump support structure

Scheme for connector site spacing and resulting structures

Re-distribution Layer Via Structure and Method of Making Same

Interconnect barrier structure and method

Low-temperature flip chip die attach

Semiconductor Constructions and Methods of Forming Semiconductor Constructions

Implementing decoupling devices inside a TSV DRAM stack

Semiconductor constructions and methods of planarizing across a plurality of electrically conductive posts

Stacked through-silicon via (TSV) transformer structure

Chip package and method for forming the same

Physical design symmetry and integrated circuits enabling three dimentional (3D) yield optimization for wafer to wafer stacking

Semiconductor device having through-electrode

Three-dimensional chip stack and method of forming the same

Wafer-level packaging mechanisms

Selective solder bump formation on wafer

Wire-based methodology of widening the pitch of semiconductor chip terminals

Chip package and method for forming the same

Package with metal-insulator-metal capacitor and method of manufacturing the same

Semiconductor device and method of forming guard ring around conductive TSV through semiconductor wafer

Bump structure for stacked dies

CHIP CONNECTION STRUCTURE AND METHOD OF FORMING

Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related semiconductor device packages

Protected solder ball joints in wafer level chip-scale packaging

Ramp-stack chip package with variable chip spacing

Semiconductor die connection system and method

Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV

Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and interconnect structure

Semiconductor package and a substrate for packaging

WSP DIE HAVING REDISTRIBUTION LAYER CAPTURE PAD WITH AT LEAST ONE VOID

WSP DIE WITH OFFSET REDISTRIBUTION LAYER CAPTURE PAD

Semiconductor assemblies and structures

Semiconductor package with stacked semiconductor chips

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME