Method for testing through-silicon-via (TSV) structures

Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die

Bump structure, having concave lateral sides, semiconductor package having the bump structure, and method of forming the bump structure

Electronic device packages including bump buffer spring pads and methods of manufacturing the same

SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE HAVING THE SAME, AND STACKED SEMICONDUCTOR PACKAGE USING THE SEMICONDUCTOR PACKAGE

Structure for monitoring stress induced failures in interlevel dielectric layers of solder bump integrated circuits

Semiconductor package including an antenna formed in a groove within a sealing element

Light emitting device chip scale package

Semiconductor package and methods of formation thereof

Semiconductor device and method of forming reconstituted wafer with larger carrier to achieve more EWLB packages per wafer with encapsulant deposited under temperature and pressure

Package with integrated pre-match circuit and harmonic suppression

3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach

Through silicon via with embedded barrier pad

Semiconductor device and method of forming a thin wafer without a carrier

Through-substrate vias and methods for forming the same

Semiconductor structure with low-melting-temperature conductive regions, and method of repairing a semiconductor structure

Semiconductor device

Through-silicon via resonators in chip packages and methods of assembling same

Connection structure, wiring substrate unit, electronic circuit part unit, and electronic apparatus

Method for chip packaging

Semiconductor device fabrication method capable of scribing chips with high yield

Semiconductor device and method of adaptive patterning for panelized packaging

Electronic component implementing structure intermediate body, electronic component implementing structure body and manufacturing method of electronic component implementing structure body

ELECTRICAL INTERCONNECTION STRUCTURE AND ELECTRICAL INTERCONNECTION METHOD

Methods and apparatus for solder connections

Controlled solder-on-die integrations on packages and methods of assembling same

Pad structure of a semiconductor device, method of manufacturing the pad structure and semiconductor package including the pad structure

Semiconductor Device and Method of Forming Composite Bump-on-Lead Interconnection

Electronic device including a feature in an opening

Cleaning methods and compositions

Semiconductor device fabrication method

Method for thin die-to-wafer bonding

Offset interposers for large-bottom packages and large-die package-on-package structures

Apparatus and method for integration of through substrate vias

Semiconductor device packages and methods

Package on package structures and methods for forming the same

Strain reduced structure for IC packaging

Substrates having bumps with holes, semiconductor chips having bumps with holes, semiconductor packages formed using the same, and methods of fabricating the same

Method for designing a package and substrate layout

Methods and apparatus for package on package devices with reversed stud bump through via interconnections

On-chip capacitors and methods of assembling same

3D packaging with low-force thermocompression bonding of oxidizable materials

Process for direct bonding two elements comprising copper portions and portions of dielectric materials

Etching solution for copper or copper alloy

Semiconductor packages and methods of fabricating the same

Electronic components assembly

Electronic Module

Semiconductor structure and method for manufacturing the same

Semiconductor substrate, semiconductor chip having the same, and stacked semiconductor package

Methods and apparatus of wafer level package for heterogeneous integration technology

Semiconductor package with through silicon via interconnect and method for fabricating the same

Fluxing-encapsulant material for microelectronic packages assembled via thermal compression bonding process

Bottom-up plating of through-substrate vias

Semiconductor device and method of forming the same

Tree based adaptive die enumeration

Method for fabricating a semiconductor device

Package on package structures and methods for forming the same

DIE STACKING WITH COUPLED ELECTRICAL INTERCONNECTS TO ALIGN PROXIMITY INTERCONNECTS

3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias

STACKED SEMICONDUCTOR COMPONENTS WITH UNIVERSAL INTERCONNECT FOOTPRINT

Bonding pad structure with dense via array

Shallow via formation by oxidation

Semiconductor device

ROTATED SEMICONDUCTOR DEVICE FAN-OUT WAFER LEVEL PACKAGES AND METHODS OF MANUFACTURING ROTATED SEMICONDUCTOR DEVICE FAN-OUT WAFER LEVEL PACKAGES

Semiconductor device

Semiconductor package

Semiconductor package

Semiconductor package, package structure and fabrication method thereof

Elongated bumps in integrated circuit devices

SEMICONDUCTOR CHIP DEVICE WITH FRAGMENTED SOLDER STRUCTURE PADS

Packaging device and method of making the same

Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die

Semiconductor device

Plating bath and method

Electromigration-resistant lead-free solder interconnect structures

Method of manufacturing a semiconductor integrated circuit device

System, method, and computer program product for affixing a post to a substrate pad

Inspection apparatus and inspection method for semiconductor device

Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips

Semiconductor device and method of forming micro-vias partially through insulating material over bump interconnect conductive layer for stress relief

Semiconductor device and method of forming conductive layer over metal substrate for electrical interconnect of semiconductor die

GALLIUM ARSENIDE DEVICES WITH COPPER BACKSIDE FOR DIRECT DIE SOLDER ATTACH

Conductive bump structure on substrate and fabrication method thereof

Method for manufacturing fine-pitch bumps and structure thereof

Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation

Semiconductor device and method of singulating semiconductor wafer along modified region within non-active region formed by irradiating energy through mounting tape

Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent Traces

ELECTROMIGRATION-RESISTANT LEAD-FREE SOLDER INTERCONNECT STRUCTURES

Semiconductor devices with stress relief layers

Solid-state device including a conductive bump connected to a metal pattern and method of manufacturing the same

Semiconductor device and method of simultaneous testing of multiple interconnects for electro-migration

Method of manufacturing a semiconductor component

Integrated circuit chip using top post-passivation technology and bottom structure technology

Inductor for post passivation interconnect

Joint structure for substrates and methods of forming

Semiconductor chip and stacked semiconductor package having the same

Semiconductor package and methods of formation thereof

Semiconductor device and method of forming compliant conductive interconnect structure in flipchip package

Methods and Apparatus for Direct Connections to Through Vias

Methods and apparatus for solder on slot connections in package on package structures

Methods and apparatus of guard rings for wafer-level-packaging

Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor die

Electronic system having increased coupling by using horizontal and vertical communication channels

Eutectic bonding of thin chips on a carrier substrate

Method and system for ultra miniaturized packages for transient voltage suppressors

Contact test structure and method

Semiconductor device bonding with stress relief connection pads

Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration

Chip stack structure and method for fabricating the same

Semiconductor constructions

Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability

Self-aligned polymer passivation/aluminum pad

Structures and methods for detecting solder wetting of pedestal sidewalls

Semiconductor component that includes a protective structure

Semiconductor device including a stress buffer material formed above a low-k metallization system

Surface metal wiring structure for an IC substrate

Three-dimensional system-in-package architecture

Metal bonded structure and metal bonding method

TWO-SOLDER METHOD FOR SELF-ALIGNING SOLDER BUMPS IN SEMICONDUCTOR ASSEMBLY

SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

Electrical connections for chip scale packaging

Method for package-on-package assembly with wire bonds to encapsulation surface

Method for chip package

Magnetic attachment structure

Low profile, space efficient circuit shields

Mechanisms for controlling bump height variation

Integrated circuit packaging system with interconnects

Enhanced flip chip structure using copper column interconnect

Mechanisms for forming connectors with a molding compound for package on package

Semiconductor device and method of manufacturing semiconductor device

Semiconductor package with integrated electromagnetic shielding

Semiconductor with through-substrate interconnect

Double-sided vertical semiconductor device with thinned substrate

Mounting structure and mounting method

Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die

Semiconductor package having light-emitting-diode solder-bonded on first and second conductive pads separated by at least 75 UM

Bumping process and structure thereof

Semiconductor devices having conductive via structures and methods for fabricating the same

Flip-chip mounted microstrip monolithic microwave integrated circuits (MMICs)

Wafer-scale package structures with integrated antennas

Semiconductor device and method for manufacturing the same

Method of manufacturing a semiconductor device and wafer

Post-passivation interconnect structure AMD method of forming same

Semiconductor device package having backside contact and method for manufacturing

Semiconductor chip comprising a plurality of contact pads and a plurality of associated pad cells

Interconnect crack arrestor structure and methods

Methods of improving bump allocation for semiconductor devices and semiconductor devices with improved bump allocation

Signal processing device

Semiconductor device and manufacturing method thereof

Reducing stress in multi-die integrated circuit structures

ELECTROMAGNETIC FIELD ASSISTED SELF-ASSEMBLY WITH FORMATION OF ELECTRICAL CONTACTS

Flux residue cleaning system and method

Transfer substrate for forming metal wiring and method for forming metal wiring using said transfer substrate

Method for building vertical pillar interconnect

Bump structural designs to minimize package defects

Methods of stress balancing in gallium arsenide wafer processing

BUMPING PROCESS AND STRUCTURE THEREOF

Integrated Circuit Die And Method Of Fabricating

Semiconductor device

Multi-dimensional integrated circuit structures and methods of forming the same

Carrier, semiconductor package and fabrication method thereof

Low Cost and High Performance Flip Chip Package

Crack-arresting structure for through-silicon vias

Crack stopper on under-bump metallization layer

Semiconductor device and method of manufacturing the same

Multi-chip fan out package and methods of forming the same

Package assembly and method of forming the same

Semiconductor packaging structure and method

Sawing underfill in packaging processes

Backside integration of RF filters for RF front end modules and design structure

Biosensor capacitor

BUMPING PROCESS

Bump pad structure

MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME

Semiconductor package structure and method for manufacturing the same

Semiconductor devices with compliant interconnects

MULTI-CHIP SELF-ALIGNMENT ASSEMBLY WHICH CAN BE USED WITH FLIP-CHIP BONDING

Package on package interconnect structure

Electronic component mounting apparatus and the same method thereof

Semiconductor package

Semiconductor die connection system and method

Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias

Packages and method of forming the same

Enhanced flip chip package

UBM formation for integrated circuits

THERMAL COMPRESSION HEAD FOR FLIP CHIP BONDING

Apparatus and method for placing solder balls

Stackable semiconductor package and manufacturing method thereof

Electronic-component mounted body, electronic component, and circuit board

Semiconductor package with package on package structure

Semiconductor package with a bridge interposer

Bump structure and electronic packaging solder joint structure and fabricating method thereof

Semiconductor device having a through-substrate via

Embedded heat spreader for package with multiple microelectronic elements and face-down connection

ESD protection device

Packages with passive devices and methods of forming the same

PHOTODIODE ARRAYS AND METHODS OF FABRICATION

Integrated compact MEMS device with deep trench contacts

Electronic component and electronic device

Semiconductor device and method of forming extended semiconductor device with fan-out interconnect structure to reduce complexity of substrate

TSV via provided with a stress release structure and its fabrication method

SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME

Semiconductor device and method of forming insulating layer in notches around conductive TSV for stress relief

Manufacturing method of semiconductor device, processing method of semiconductor wafer, semiconductor wafer

Semiconductor package including stacked semiconductor chips and a redistribution layer

Electronics device package and fabrication method thereof

Semiconductor package including flip chip controller at bottom of die stack

Microspring structures adapted for target device cooling

Method for packaging semiconductors at a wafer level

SEMICONDUCTOR DEVICE INCLUDING THROUGH ELECTRODE AND METHOD OF MANUFACTURING THE SAME AND STACKED PACKAGE INCLUDING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP

Integrated circuit packaging system with coupling features and method of manufacture thereof

Stacked Packaging Using Reconstituted Wafers

Integrated circuits with components on both sides of a selected substrate and methods of fabrication

SEMICONDUCTOR STACK PACKAGES AND METHODS OF FABRICATING THE SAME

Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe

Die structure and method of fabrication thereof

Treatment, before the bonding of a mixed Cu-oxide surface, by a plasma containing nitrogen and hydrogen

Method of manufacturing bump

Methods of fabricating fan-out wafer level packages and packages formed by the methods

Chip-to-wafer bonding method and three-dimensional integrated semiconductor device

Semiconductor device and method of forming guard ring around conductive TSV through semiconductor wafer

Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in Fo-WLCSP

Offset of contact opening for copper pillars in flip chip packages

Multi-chip package having a stacked plurality of different sized semiconductor chips, and method of manufacturing the same

Substrate with embedded stacked through-silicon via die

Semiconductor structure having no adjacent bumps between two adjacent pads

Semiconductor device and method of forming UBM structure on back surface of TSV semiconductor wafer

Bump structure design for stress reduction

Post-passivation interconnect structure

Passivation layer for packaged chip

Semiconductor device with bump structure on an interconncet structure

Landing areas of bonding structures

HEATSINK INTERPOSER

Semiconductor package having internal shunt and solder stop dimples

Receiver module and device

Device including two power semiconductor chips and manufacturing thereof

Semiconductor device and method of forming conductive pillars having recesses or protrusions to detect interconnect continuity between semiconductor die and substrate

Package structure and the method to manufacture thereof

Method for forming a reliable solderable contact

Method of processing solder bump by vacuum annealing

Packaging process tools and systems, and packaging methods for semiconductor devices

Semiconductor device including a protective film

UBM structures for wafer level chip scale packaging

Circuit connector apparatus and method therefor

Solderable contact and passivation for semiconductor dies

Semiconductor device

Flip chip package utilizing trace bump trace interconnection

Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migration

TSV structures and methods for forming the same

Semiconductor package structure and manufacturing method thereof

Semiconductor device and method of forming cavity in build-up interconnect structure for short signal path between die

COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT WITH THREE-DIMENSIONALLY FORMED COMPONENTS

Plating process and structure

Semiconductor devices including protected barrier layers

Flip chip package for DRAM with two underfill materials

Semiconductor device having shielded conductive vias

Semiconductor device and method of forming a power MOSFET with interconnect structure to achieve lower RDSON

Method of fabricating a wafer level semiconductor package having a pre-formed dielectric layer

Semiconductor device with means for preventing solder bridges, and method for manufacturing semiconductor device

Semiconductor device manufacturing method, semiconductor device, and semiconductor element

Package-on-package (PoP) structure including stud bulbs and method

Semiconductor device having wiring pad and wiring formed on the same wiring layer

Bump structures for multi-chip packaging

Planarized bumps for underfill control

Semiconductor device and method of forming RDL under bump for electrical connection to enclosed bump

Packaged die for heat dissipation and method therefor

Electrical connection structure

Chip-on-Wafer structures and methods for forming the same

Semiconductor device and manufacturing method thereof

Under bump passive components in wafer level packaging

Adjusting sizes of connectors of package components

Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same

Methods and apparatus of under bump metallization in packaging semiconductor devices

Device having electrodes formed from bumps with different diameters

Conductive structure and method for forming the same

Mechanisms for forming fine-pitch copper bump structures

Semiconductor device and method of forming reconstituted wafer with larger carrier to achieve more eWLB packages per wafer with encapsulant deposited under temperature and pressure

Electroless plating apparatus and electroless plating method

Test structure and method of testing electrical characteristics of through vias

Semiconductor package, semiconductor package manufacturing method and semiconductor device

Packaging structural member

Method for developing a custom device

Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump

Bumps for Chip Scale Packaging

Through-silicon via with low-K dielectric liner

Termination structure for gallium nitride schottky diode

Vertical gallium nitride Schottky diode

Misalignment correction for embedded microelectronic die applications

Low-temperature wafer level processing for MEMS devices

Methods of and semiconductor devices with ball strength improvement

PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF

Post-passivation interconnect structure and method of forming the same

Method of packaging semiconductor die

SEMICONDUCTOR DEVICE INTERCONNECT

Embedded wafer level package for 3D and package-on-package applications, and method of manufacture

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

Flattened substrate surface for substrate bonding

Package on package devices and methods of packaging semiconductor dies

TSV backside processing using copper damascene interconnect technology