Three-dimensional chip-to-wafer integration

Semiconductor device and method of forming thermal interface material and heat spreader over semiconductor die

3D chip package with shielded structures

Multiple die stacking for two or more die

Microelectronic package with stacked microelectronic units and method for manufacture thereof

Packages and methods for forming the same

Semiconductor device and method

WAFER LEVEL CHIP SCALE PACKAGE DEVICE AND MANUFACTURING METHOD THEROF

Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die

Package of electronic device including connecting bump, system including the same and method for fabricating the same

Semiconductor packages including a plurality of upper semiconductor devices on a lower semiconductor device

Methods of forming bump structures that include a protection layer

SEMICONDUCTOR PACKAGE HAVING SOLDER JOINTED REGION WITH CONTROLLED AG CONTENT

Semiconductor package having a contamination preventing layer formed in the semiconductor chip

SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE

ESD protection device

Package-on-package assembly with wire bond vias

Power converters with integrated capacitors

Bond pad structure and fabricating method thereof

Semiconductor device and method of forming conductive pillar having an expanded base

SEMICONDUCTOR APPARATUS

Package-on-package assembly with wire bond vias

Package-on-package assembly with wire bond vias

Wafer-level chip scale package with re-workable underfill

Connector structures of integrated circuits

Process for forming package-on-package structures

Post-passivation interconnect structure

Semiconductor package and method of forming the same

WAFER LEVEL APPLIED RF SHIELDS

Method of fabricating backside-illuminated image sensor

Packaging process tools and packaging methods for semiconductor devices

Semiconductor device and method of forming reconstituted wafer with larger carrier to achieve more eWLB packages per wafer with encapsulant deposited under temperature and pressure

Integrated circuit structure having dies with connectors of different sizes

Semiconductor package having an anti-contact layer

Methods of packaging semiconductor devices and structures thereof

Copper Stud Bump Wafer Level Package

Wafer level chip scale package and method of manufacturing the same

Semiconductor device, electronic device, and semiconductor device manufacturing method

Semiconductor device having multiple bump heights and multiple bump diameters

Semiconductor device having improved contact structure

Bump with protection structure

Metal Features to Reduce Crack-Inducing Stresses in Metallization Stacks

Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die

Electrical connection for chip scale packaging

Method and System for Metal Deposition in Semiconductor Processing

ELECTRONIC PACKAGING CONNECTOR AND METHODS FOR ITS PRODUCTION

Power management applications of interconnect substrates

Method for formation of an electrically conducting through via

Stub minimization for multi-die wirebond assemblies with parallel windows

Stub minimization for assemblies without wirebonds to package substrate

Semiconductor package and method of manufacturing the same

Stub minimization for multi-die wirebond assemblies with parallel windows

Stub minimization for assemblies without wirebonds to package substrate

Integrated circuit package and a method for manufacturing an integrated circuit package

ELECTRONIC ASSEMBLY HAVING MIXED INTERFACE INCLUDING TSV DIE

SEMICONDUCTOR DEVICE

Semiconductor package including an integrated waveguide

Stub minimization for assemblies without wirebonds to package substrate

EMI SHIELDED SEMICONDUCTOR PACKAGE AND EMI SHIELDED SUBSTRATE MODULE

EMI package and method for making same

Device having wirelessly enabled functional blocks

METHODS OF FORMING CONNECTION BUMP OF SEMICONDUCTOR DEVICE

Multi-chip semiconductor package and method of fabricating the same

Structure design for 3DIC testing

Composite layered chip package

INTEGRATED CIRCUIT AND METHOD OF MAKING

Integrated circuit packaging system with encapsulation and method of manufacture thereof

Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF

Interconnection Between Integrated Circuit and Package

Semiconductor device and method for manufacturing semiconductor device

Semiconductor Chips and Semiconductor Packages and Methods of Fabricating the Same

Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die

Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant

Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding

Semiconductor package and method of forming z-direction conductive posts embedded in structurally protective encapsulant

Synchronous buck converter having coplanar array of contact bumps of equal volume

Method for Three Dimensional Integrated Circuit Fabrication

Integrated circuit and method of making

Metal pad structures in dies

Formation of connectors without UBM

Method for assembling a chip in a flexible substrate

Manufacturing method of semiconductor integrated circuit device

Semiconductor package and method for manufacturing the semiconductor package embedded with semiconductor chip

Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant

Solder cap bump in semiconductor package and method of manufacturing the same

Package substrate and semiconductor package including the same

Semiconductor device and method of forming protection and support structure for conductive interconnect structure

Semiconductor device and method of forming protection and support structure for conductive interconnect structure

Integrated circuit packaging system with routable underlayer and method of manufacture thereof

FLASH MEMORY CARD WITHOUT A SUBSTRATE AND ITS FABRICATION METHOD

Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect

Semiconductor device and method of forming conductive protrusion over conductive pillars or bond pads as fixed offset vertical interconnect structure

Semiconductor package and method for manufacturing the semiconductor package

Die bonder and bonding method

METHOD AND APPARATUS FOR CONNECTING INLAID CHIP INTO PRINTED CIRCUIT BOARD

Substrate structure with compliant bump and manufacturing method thereof

Chip package structure and method for manufacturing the same

Mounting method for semiconductor light emitter using resist with openings of different sizes

Semiconductor integrated circuit device and method of manufacturing same

Snubber circuit and method of using bipolar junction transistor in snubber circuit

Snubber circuit and method of using bipolar junction transistor in snubber circuit

Solder mask with anchor structures

TRANSISTOR STRUCTURE AND RELATED TRANSISTOR PACKAGING METHOD THEREOF

Chip packaging structure and manufacturing method for the same

Electrical test structure applying 3D-ICS bonding technology for stacking error measurement

Strain-compensating fill patterns for controlling semiconductor chip package interactions

Semiconductor structure and method for making same

System and method for 3D integrated circuit stacking

Semiconductor package with improved pillar bump process and structure

Packaging methods and structures for semiconductor devices

Packaging methods and structures using a die attach film

SEMICONDUCTOR DEVICE

Substrate structure with compliant bump and manufacturing method thereof

Elongated bump structure in semiconductor device

Flip-chip, face-up and face-down wirebond combination package

Pillar structure having a non-planar surface for semiconductor devices

ROUTING UNDER BOND PAD FOR THE REPLACEMENT OF AN INTERCONNECT LAYER

Integrated circuit packaging system with stiffener and method of manufacture thereof

Semiconductor device and method of forming a low profile dual-purpose shield and heat-dissipation structure

Method for making a sensor device using a graphene layer

Wiring substrate, method for manufacturing wiring substrate, and semiconductor package including wiring substrate

Method for manufacturing a circuit device

Semiconductor devices having through electrodes and methods of fabricating the same

STACKED INTEGRATED CIRCUIT PACKAGES THAT INCLUDE MONOLITHIC CONDUCTIVE VIAS

Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits

Die-to-die gap control for semiconductor structure and method

Configuration of connections in a 3D stack of integrated circuits

Bond pad configurations for controlling semiconductor chip package interactions

Chip with encapsulated sides and exposed surface

Three-dimensional integrated circuit (3DIC) formation process

Self-aligned protection layer for copper post structure

Formation of through-silicon via (TSV) in silicon substrate

STACKED CHIP PACKAGE AND FABRICATION METHOD THEREOF

Methods of fabricating semiconductor chip solder structures

Semiconductor flip-chip system having three-dimensional solder joints

Light-reflective anisotropic conductive adhesive agent, and light emitting device

High density gallium nitride devices using island topology

Method and apparatus for fabricating integrated circuit device using self-organizing function

Bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate

Bond pad structure to reduce bond pad corrosion

Semiconductor dice including at least one blind hole, wafers including such semiconductor dice, and intermediate products made while forming at least one blind hole in a substrate

Package-on-package structures

Semiconductor apparatus, method of manufacturing semiconductor apparatus, and electronic apparatus

Semiconductor devices, package substrates, semiconductor packages, package stack structures, and electronic systems having functionally asymmetric conductive elements

Dummy flip chip bumps for reducing stress

Multiple die in a face down package

Solder Bump Bonding In Semiconductor Package Using Solder Balls Having High-Temperature Cores

Integrated circuit die with low thermal resistance

Chip package and method for forming the same

Semiconductor packaging for a memory device and a fabricating method thereof

MEMS device having chip scale packaging

Through silicon via layout

Fabrication method of packaging substrate having through-holed interposer embedded therein

Method of Multi-Chip Wafer Level Packaging

Semiconductor device

Method of manufacturing capacitor

Conductive routings in integrated circuits using under bump metallization

Semiconductor device having a through-substrate via

SEMICONDUCTOR CHIP INCLUDING BUMP HAVING BARRIER LAYER, AND MANUFACTURING METHOD THEREOF

Semiconductor device

Chip Stack Packages Having Aligned Through Silicon Vias of Different Areas

Semiconductor device, semiconductor package, method for manufacturing semiconductor device, and method for manufacturing semiconductor package

Semiconductor chips having a dual-layered structure, packages having the same, and methods of fabricating the semiconductor chips and the packages

Method for inhibiting growth of intermetallic compounds

Semiconductor package and stack-type semiconductor package having the same

Bump pad structure

Semiconductor device and method of forming a stackable semiconductor package with vertically-oriented discrete electrical devices as interconnect structures

Wafer level package structure and the fabrication method thereof

Semiconductor package with under bump metallization routing

STACKABLE WAFER LEVEL PACKAGES AND RELATED METHODS

Area array quad flat no-lead (QFN) package

Wafer level chip scale package with thick bottom metal exposed and preparation method thereof

Signal delivery in stacked device

Cleaning residual molding compound on solder bumps

Structure and method for power field effect transistor

WAFER LEVEL PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Microelectronic package with stacked microelectronic elements and method for manufacture thereof

Semiconductor device

Semiconductor device

Routing layer for mitigating stress in a semiconductor die

CHIP PACKAGE STRUCTURE

Chip package structure using flexible substrate

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

Integrated inductor

Method of making cavity substrate with built-in stiffener and cavity substrate manufactured thereby

Method of making a die with recessed aluminum die pads

Method and system for forming conductive bumping with copper interconnection

Method of manufacturing semiconductor device

TCE compensation for package substrates for reduced die warpage assembly

Integrated circuit comprising at least an integrated antenna

Liquid epoxy resin composition for semiconductor encapsulation

CHIP PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device and method of forming vertical interconnect in FO-WLCSP using leadframe disposed between semiconductor die

SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE STRUCTURE CONFIGURED BY VERTICALLY STACKING SEMICONDUCTOR DEVICES, AND MANUFACTURING METHOD THEREOF

Semiconductor device and manufacturing method therefor

Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication

Integrated circuit package including a direct connect pad, a blind via, and a bond pad electrically coupled to the direct connect pad

Wafer-level chip scale package

FLIP CHIPS HAVING MULTIPLE SOLDER BUMP GEOMETRIES

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE UNIT, AND SEMICONDUCTOR DEVICE PRODUCTION METHOD

Electronic chip comprising connection pillars and manufacturing method

Coaxial solder bump support structure

Semiconductor devices, packaging methods and structures

Bump structures in semiconductor device and packaging assembly

Metal bump structure

Self-aligning conductive bump structure and method of making the same

Bump structures

Method and device for circuit routing by way of under-bump metallization

Semiconductor device

Chip package having optical-electronic device with plurality of light shielding layers and substrate through-hole with void, and method for forming the same

Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby

Bumping process and structure thereof

Composite layered chip package

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Interconnect pillars with directed compliance geometry

Method for Making a Stackable Package

Semiconductor device and a method of manufacturing the same

Chip package and fabrication method thereof

Techniques and structures for testing integrated circuits in flip-chip assemblies

Solder bump cleaning before reflow

Integrated antennas in wafer level package

Self orienting micro plates of thermally conducting material as component in thermal paste or adhesive

Electronic assembly including die on substrate with heat spreader having an open window on the die

Bond pad configurations for semiconductor dies

Memory module in a package

Memory module in a package

Semiconductor device having through electrode and method of fabricating the same

De-skewed multi-die packages

Solder ball contact susceptible to lower stress

Semiconductor device and method of forming base substrate with cavities formed through etch-resistant conductive layer for bump locking

Semiconductor device with solder bump formed on high topography plated Cu pads

Electronic assembly including an embedded electronic component

Semiconductor device having antenna element and method of manufacturing same

Mechanisms for marking the orientation of a sawed die

SEMICONDUCTOR PACKAGE INCLUDING AN EXTERNAL CIRCUIT ELEMENT

TSV STRUCTURE AND METHOD FOR FORMING THE SAME

RADIO MODULE AND MANUFACTURING METHOD THEREFOR

Semiconductor device for improving electrical and mechanical connectivity of conductive pillers and method therefor

UBM etching methods for eliminating undercut

HYBRID BONDING TECHNIQUES FOR MULTI-LAYER SEMICONDUCTOR STACKS

Semiconductor element-embedded substrate, and method of manufacturing the substrate

Semiconductor package and method of manufacturing the same

Apparatus and methods for forming through vias

Stacked memory layers having multiple orientations and through-layer interconnects

SEMICONDUCTOR STACK PACKAGE APPARATUS

Forming wafer-level chip scale package structures with reduced number of seed layers

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SEMICONDUCTOR CHIP AND FLIP-CHIP PACKAGE COMPRISING THE SAME

Backside illumination sensor having a bonding pad structure and method of making the same

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, WIRING SUBSTRATE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF WIRING SUBSTRATE

Ball-limiting-metallurgy layers in solder ball structures

Method of manufacturing a circuit substrate

Methods of forming a metal pattern

Method of fabricating semiconductor package having substrate with solder ball connections

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A HEAT SPREADER

Microelectronic devices with improved heat dissipation and methods for cooling microelectronic devices

Wafer Level Package and a Method of Forming the Same

System on a chip with interleaved sets of pads

Interconnect barrier structure and method

Multi-component integrated circuit contacts

Stack package having flexible conductors

Bump-on-trace (BOT) structures

Interconnect structure for wafer level package

Conductive connecting member and manufacturing method of same

Electrically conductive paste, and electrically conducive connection member produced using the paste

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

Semiconductor device and a method of manufacturing the same

Semiconductor device and method of forming Fo-WLCSP with discrete semiconductor components mounted under and over semiconductor die

Bump-on-trace structures with wide and narrow portions

Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor Die

Semiconductor device

Backside-illuminated image sensor having a supporting substrate

ELECTRIC JOINT STRUCTURE AND METHOD FOR PREPARING THE SAME

MICRO PIN HYBRID INTERCONNECT ARRAY

Connecting film, and joined structure and method for producing the same

Methods for controlling wafer curvature

METHOD OF FORMING A BOND PAD DESIGN FOR IMPROVED ROUTING AND REDUCED PACKAGE STRESS

Through wafer vias and method of making same

METAL-GRAPHITE FOAM COMPOSITE AND A COOLING APPARATUS FOR USING THE SAME

Bond pad design for improved routing and reduced package stress

Method and apparatus providing integrated circuit having redistribution layer with recessed connectors

Enhanced WLP for superior temp cycling, drop test and high current applications

SEMICONDUCTOR CHIP WITH DUAL POLYMER FILM INTERCONNECT STRUCTURES

Bump structure with barrier layer on post-passivation interconnect

Semiconductor device and method of forming protective coating over interconnect structure to inhibit surface oxidation

Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure

Methods and arrangements relating to semiconductor packages including multi-memory dies

SEMICONDUCTOR CHIP, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE

Wiring board and method of manufacturing the same

Semiconductor device and manufacturing of the semiconductor device

SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING THE SAME

Module substrate, module-substrate manufacturing method, and terminal connection substrate

Semiconductor device and manufacturing method

Chip package and method for forming the same

Semiconductor chip with through hole vias

MICROELECTRONIC DEVICE, STACKED DIE PACKAGE AND COMPUTING SYSTEM CONTAINING SAME, METHOD OF MANUFACTURING A MULTI-CHANNEL COMMUNICATION PATHWAY IN SAME, AND METHOD OF ENABLING ELECTRICAL COMMUNICATION BETWEEN COMPONENTS OF A STACKED-DIE PACKAGE

SEMICONDUCTOR PACKAGE

Reliable packaging and interconnect structures