Flip chip interconnect solder mask

Flip chip interconnect solder mask

Bump structure and process of manufacturing the same

Wafer level chip scale package with reduced stress on solder balls

Enhanced bump pitch scaling

Integrated circuit packaging system with thermal dispersal structures and method of manufacture thereof

Integrated circuit packaging system with encapsulation and underfill and method of manufacture thereof

Solder ball protection structure with thick polymer layer

Stress-aware design for integrated circuits comprising a stress inducing structure and keep out zone

Electronic device and method for producing electronic device

Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via

Low-stress TSV design using conductive particles

Apparatus of manufacturing semiconductor packages and methods of manufacturing semiconductor packages using the same

Chip package structure and manufacturing method thereof

Layered chip package and method of manufacturing same

Layered chip package and method of manufacturing same

Semiconductor device having through silicon vias and manufacturing method thereof

Semiconductor device having a first substrate containing circuit element connected to radiation plate on a cover plate with metal vias

Fan-out microelectronic unit WLP having interconnects comprising a matrix of a high melting point, a low melting point and a polymer material

Semiconductor device structures

Method for producing a protective structure

CHIP-SCALE PACKAGE

Flip chip assembly and process with sintering material on metal bumps

Bonded semiconductor structures and methods of forming same

Semiconductor device having magnetic alignment marks and underfill resin layers

QFN PACKAGE AND MANUFACTURING PROCESS THEREOF

Wiring substrate, semiconductor device and manufacturing method thereof

Chip package structure and manufacturing method thereof

3D integrated microelectronic assembly with stress reducing interconnects

Semiconductor device and method of forming a power MOSFET with interconnect structure silicide layer and low profile bump

Heterostructure containing IC and LED and method for fabricating the same

Multilayer pillar for reduced stress interconnect and method of making same

Apparatus for restricting moisture ingress

Implantable microelectronic device and method of manufacture

Method of manufacturing a semiconductor device

Disabling electrical connections using pass-through 3D interconnects and associated systems and methods

Method for fabricating 3D integrated circuit device using interface wafer as permanent carrier

Power converter, semiconductor device, and method for manufacturing power converter

Back-illuminated distance measuring sensor and distance measuring device

Back-illuminated distance measuring sensor and distance measuring device

Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties

Semiconductor device and method of forming WLCSP structure using protruded MLP

SEMICONDUCTOR PACKAGE AND FABRICATION METHOD OF THE SAME

Conductive pads defined by embedded traces

3D IC packaging structures and methods with a metal pillar

Exposed interconnect for a package on package system

Connector design for packaging integrated circuits

Wafer-level package device

Electrical connection for chip scale packaging

Semiconductor device fabrication method and semiconductor device

Semiconductor device, semiconductor package, and electronic device

Semiconductor device including Schottky barrier diode

Injection molded solder process for forming solder bumps on substrates

Injection molded solder process for forming solder bumps on substrates

ESTIMATION OF PRESENCE OF VOID IN THROUGH SILICON VIA (TSV) BASED ON ULTRASOUND SCANNING

Method of manufacturing semiconductor device

Distributed semiconductor device methods, apparatus, and systems

3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer

STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE

SEMICONDUCTOR PACKAGES

Semiconductor chip having via electrodes and stacked semiconductor chips interconnected by the via electrodes

Pad structure, circuit carrier and integrated circuit chip

Semiconductor device and method of forming EWLB package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around die

Aluminum Bond Pad With Trench Thinning for Fine Pitch Ultra-Thick Aluminum Products

BONDING PAD STRUCTURE AND INTEGRATED CIRCUIT COMPRISING A PLURALITY OF BONDING PAD STRUCTURES

Semiconductor device and method of forming bump structure with multi-layer UBM around bump formation area

Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias

Integrated circuit packaging system with vertical interconnects and method of manufacture thereof

Conductive via structure

Semiconductor device and method of manufacturing semiconductor device

Solder collapse free bumping process of semiconductor device

Method of manufacturing semiconductor device

Multi-die memory device

Light emitting device and system providing white light with various color temperatures

Integrated void fill for through silicon via

Microelectronic devices having conductive through via electrodes insulated by gap regions

Integrated circuit package with discrete components surface mounted on exposed side

Semiconductor structure having offset passivation to reduce electromigration

Electromigration immune through-substrate vias

BONDING PAD STRUCTURE AND INTEGRATED CIRCUIT COMPRISING A PLURALITY OF BONDING PAD STRUCTURES

Semiconductor device and method of manufacturing the same

Semiconductor component with a front side and a back side metallization layer and manufacturing method thereof

Semiconductor devices including stress relief structures

Semiconductor device and method of forming 3D semiconductor package with semiconductor die stacked over semiconductor wafer

Chip package and package wafer with a recognition mark, and method for forming the same

Barrier structure

INTERPOSER FILMS USEFUL IN SEMICONDUCTOR PACKAGING APPLICATIONS, AND METHODS RELATING THERETO

Supplying power to integrated circuits using a grid matrix formed of through-silicon vias

Arrangement for solder bump formation on wafers

Method for manufacturing semiconductor modules

Wafer level IC assembly method

Method for fabricating stacked semiconductor system with encapsulated through wire interconnects (TWI)

EMBEDDED CHIP PACKAGE

Robust FBEOL and UBM structure of C4 interconnects

Integrated circuit packaging system with interconnect and method of manufacture thereof

Semiconductor device and method of singulating thin semiconductor wafer on carrier along modified region within non-active region formed by irradiating energy

FORMATION OF THROUGH-SILICON VIA (TSV) IN SILICON SUBSTRATE

Semiconductor device and a manufacturing method thereof

Die stacking with an annular via having a recessed socket

Doping Minor Elements into Metal Bumps

Chip package and method for forming the same

Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance

Integrated circuit package and packaging methods

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR MODULE USING THE SAME

Semiconductor device

Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device

SEMICONDUCTOR CHIP MODULE AND PLANAR STACK PACKAGE HAVING THE SAME

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

NANOSTRUCTURED COMPOSITE POLYMER THERMAL/ELECTRICAL INTERFACE MATERIAL AND METHOD FOR MAKING THE SAME

Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array

METHOD FOR PRODUCING A TWO-SIDED FAN-OUT WAFER LEVEL PACKAGE WITH ELECTRICALLY CONDUCTIVE INTERCONNECTS, AND A CORRESPONDING SEMICONDUCTOR PACKAGE

Method of manufacturing chip-stacked semiconductor package

STACK PACKAGES HAVING FASTENING ELEMENT AND HALOGEN-FREE INTER-PACKAGE CONNECTOR

Buffer pad in solder bump connections and methods of manufacture

Chip package and fabrication method thereof

Copper pillar bump with non-metal sidewall protection structure and method of making the same

Electronic device packaging structure

Semiconductor structure and fabrication method thereof

Techniques for improving bond pad performance

Method for manufacturing semiconductor device

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP

Semiconductor device and method of embedding TSV semiconductor die within substrate for vertical interconnect in POP

Microelectronic chip, component containing such a chip and manufacturing method

Contact Metal for Hybridization and Related Methods

Chip package with a chip embedded in a wiring body

Integrated circuit device including a copper pillar capped by barrier layer

Solder joint flip chip interconnection having relief structure

Flip-chip Mounting Structure and Flip-chip Mounting Method

SEMICONDUCTOR APPARATUS AND METHOD FOR FABRICATING THE SAME

Filled through-silicon via with conductive composite material

Semiconductor device and method of forming an interconnect structure with conductive material recessed within conductive ring over surface of conductive pillar

Reduced-stress bump-on-trace (BOT) structures

POWER SUPPLY MODULE AND PACKAGING AND INTEGRATING METHOD THEREOF

Multi-die packages incorporating flip chip dies and associated packaging methods

Chip on film type semiconductor package

Semiconductor device and method of forming shielding layer over active surface of semiconductor die

Stacked sensor packaging structure and method

Method of manufacturing nitride semiconductor light emitting element having thick metal bump

Etchant and method for manufacturing semiconductor device using same

Routing layer for mitigating stress in a semiconductor die

Aligned nanotube bearing composite material

Semiconductor device and method of forming IPD in fan-out wafer level chip scale package

Package structures

Flip-chip, face-up and face-down wirebond combination package

Flip-chip, face-up and face-down centerbond memory wirebond assemblies

Multi chip package, manufacturing method thereof, and memory system having the multi chip package

Semiconductor device with a layer including niobium, and/or tantalum overlying a contact pad or a metal layer

STACKED-SUBSTRATE STRUCTURE

Mechanisms for forming copper pillar bumps using patterned anodes

SEMICONDUCTOR PACKAGE

Multi-chip module with stacked face-down connected dies

Method of making a semiconductor device having a functional capping

Stacked chip-on-board module with edge connector

Semiconductor package with embedded spiral inductor

Multi-level options for power MOSFETS

LIGHT-EMITTING DIODE DIE PACKAGES AND ILLUMINATION APPARATUSES USING SAME

Light-emitting diode die packages and illumination apparatuses using same

Package substrate and fabricating method thereof

MOLD ARRAY PROCESS METHOD TO PREVENT EXPOSURE OF SUBSTRATE PERIPHERIES

Memory module and memory system

SEMICONDUCTOR DEVICE

Dicing tape-integrated wafer back surface protective film

Multi-chip package and method of providing die-to-die interconnects in same

Wafer level package having a stress relief spacer and manufacturing method thereof

Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation

Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution

REINFORCED VIA FARM INTERCONNECT STRUCTURE, A METHOD OF FORMING A REINFORCED VIA FARM INTERCONNECT STRUCTURE AND A METHOD OF REDESIGNING AN INTEGRATED CIRCUIT CHIP TO INCLUDE SUCH A REINFORCED VIA FARM INTERCONNECT STRUCTURE

SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION

Die arrangements containing an inductor coil and methods of manufacturing a die arrangement containing an inductor coil

Light-emitting diode die packages and illumination apparatuses using same

LIGHT EMITTING DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Wafer level packaging of electronic devices

Integrated circuit with test circuit

Etchant and method for manufacturing semiconductor device using same

On-chip RF shields with backside redistribution lines

SEMICONDUCTOR DEVICE

Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device

Solder ball contact susceptible to lower stress

Semiconductor device and method for fabricating the same

Semiconductor device and method of manufacturing the same

Integrated Circuit Package Security Fence

Semiconductor device with through silicon via and alignment mark

Method for manufacturing semiconductor device

Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods

Solid-state imaging device having penetration electrode formed in semiconductor substrate

FASTENING AND ELECTROCONDUCTIVE CONNECTING OF A CHIP MODULE TO A CHIP CARD

HEAT CONDUCTION FOR CHIP STACKS AND 3-D CIRCUITS

Methods for packaging microelectronic devices and microelectronic devices formed using such methods

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Via network structures and method therefor

Methods of forming bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods

METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS

Semiconductor device

Methods for forming a semiconductor structure

Semiconductor die having fine pitch electrical interconnects

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Selective electromigration improvement for high current C4s

Method of making a semiconductor device comprising a land grid array flip chip bump system with short bumps

Semiconductor device having plural stacked chips

RELIABLE SOLDER BUMP COUPLING WITHIN A CHIP SCALE PACKAGE

Semiconductor device and method of forming thermally conductive layer between semiconductor die and build-up interconnect structure

Miniature Microwave Component for Surface-Mounting

Voltage switchable dielectric for die-level electrostatic discharge (ESD) protection

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Interposer having an inductor

Flip chip semiconductor device

Semiconductor packages

Reducing warpage for fan-out wafer level packaging

Method of fabricating a semiconductor chip with supportive terminal pad

Semiconductor device and method of forming pad layout for flipchip semiconductor die

Integrated circuit packaging system with collapsed multi-integration package and method of manufacture thereof

Integrated circuit packaging system with step mold and method of manufacture thereof

Configurable interposer

Semiconductor packaging process using through silicon vias

Semiconductor device having a pad-disposition restriction area

Apparatuses and methods to enhance passivation and ILD reliability

WAFER BUMPING USING PRINTED UNDER BUMP METALIZATION

Semiconductor device, method of manufacturing the same, and method of manufacturing wiring board

Semiconductor Device and Method of Forming High Routing Density Interconnect Sites on Substrate

Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation

Integrated circuit packaging system with an interposer substrate and method of manufacture thereof

IC wafer having electromagnetic shielding effects and method for making the same

Semiconductor device and method of forming leadframe with notched fingers for stacking semiconductor die

FLIP-CHIP LED PACKAGING AND MANUFACTURING THEREOF

Build-up printed wiring board substrate having a core layer that is part of a circuit

Semiconductor device and method of manufacturing the same

DEVICE SUBSTRATE AND METHOD FOR MANUFACTURING SAME

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

IC devices having TSVS including protruding tips having IMC blocking tip ends

Power module for an automobile

Power device with bottom source electrode

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC SYSTEM USING THE SAME

DEVICE INCLUDING A SEMICONDUCTOR CHIP

WIRE WRAP COMPOSITIONS AND METHODS RELATING THERETO

COVERLAY COMPOSITIONS AND METHODS RELATING THERETO

THERMALLY AND DIMENSIONALLY STABLE POLYIMIDE FILMS AND METHODS RELATING THERETO

Stacked semiconductor component having through wire interconnect (TWI) with compressed wire

Semiconductor device and method of manufacturing the same

Air-gap C4 fluidic I/O interconnects and methods of fabricating same

Integrated circuit package system with stackable devices and a method of manufacture thereof

Solder bump interconnect

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor device and method for manufacturing the same

Chip package and method for forming the same

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device and method for manufacturing semiconductor device

Thin film transistor compositions, and methods relating thereto

Circuit board and method for manufacturing circuit board

Semiconductor Load Board

ASSEMBLIES COMPRISING A POLYIMIDE FILM AND AN ELECTRODE, AND METHODS RELATING THERETO

ETCHING LIQUID FOR ETCHING SILICON SUBSTRATE REAR SURFACE IN THROUGH SILICON VIA PROCESS AND METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP HAVING THROUGH SILICON VIA USING THE ETCHING LIQUID

Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint

Package 3D interconnection and method of making same

Inner-layer heat-dissipating board, multi-chip stack package structure having the inner layer heat-dissipating board and fabrication method thereof

Active matrix substrate

SEMICONDUCTOR PACKAGE INCLUDING CONNECTING MEMBER HAVING CONTROLLED CONTENT RATIO OF GOLD

Solder ball for semiconductor packaging and electronic member using the same

Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate

Flip chip package

Semiconductor device and method of forming stress relief layer between die and interconnect structure

Semiconductor device and fabrication method thereof

Interconnections for fine pitch semiconductor devices and manufacturing method thereof

Polymer and solder pillars for connecting chip and carrier

Semiconductor packages and methods of packaging semiconductor devices

Method for manufacturing semiconductor device

Electronic component and method of manufacturing electronic component

Heat radiation material, electronic device and method of manufacturing electronic device

Integrated circuit package with molded cavity

SEMICONDUCTOR DEVICE AND NOISE SUPPRESSING METHOD

Semiconductor devices including a through-substrate conductive member with an exposed end

Semiconductor device having stacked substrates with protruding and recessed electrode connection

Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of Fo-WLCSP

Semiconductor device and method of forming conductive THV and RDL on opposite sides of semiconductor die for RDL-to-RDL bonding

Semiconductor device and method of forming bond wires between semiconductor die contact pads and conductive TOV in peripheral area around semiconductor die

Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer

Ni plating of a BLM edge for Pb-free C4 undercut control

Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier

Semiconductor device and method of forming a wafer level package structure using conductive via and exposed bump

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

Integrated circuits including conductive structures through a substrate and methods of making the same

Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openings and Projections

Mosfet package

Routing method for flip chip package and apparatus using the same

Methods of fabricating semiconductor devices

Bond pad structure

Semiconductor device and method of forming multi-layered UBM with intermediate insulating buffer layer to reduce stress for semiconductor wafer

Joining electrode, method of manufacturing the same, semiconductor device, and method of manufacturing the same

Semiconductor device and method of forming WLCSP structure using protruded MLP

WAFER CHIP SCALE PACKAGE CONNECTION SCHEME

Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process

Chip package with plank stack of semiconductor dies

Semiconductor-on-insulator with back side connection

Electroconductive bonding material, method for bonding conductor, and method for manufacturing semiconductor device

DEVICE MOUNTING BOARD AND METHOD OF MANUFACTURING THE SAME, SEMICONDUCTOR MODULE, AND MOBILE DEVICE

Self orienting micro plates of thermally conducting material as component in thermal paste or adhesive

Semiconductor device and manufacturing method therefor

Passivation layer for semiconductor device packaging

On-Chip RF shields with front side redistribution lines