Michael Fee

Cache line hold state for multiprocessing computing systems

Cache management using cache scope designation

Controller address contention assumption

Controller address contention assumption

EXECUTING MULTIPLE DATA REQUESTS OF MULTIPLE-CORE PROCESSORS

Executing an atomic primitive in a multi-core processor system

Method and processor system for executing a TELT instruction to access a data item during execution of an atomic primitive

Multiprocessor cache buffer management

Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry

Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry

Bypassing an encoded latch on a chip during a test-pattern scan

Bypassing an encoded latch on a chip during a test-pattern scan

Eliminate corrupted portions of cache during runtime

Designated cache data backup during system operation

Eliminate corrupted portions of cache during runtime

Eliminate corrupted portions of cache during runtime

Multiprocessor cache buffer management

Maintaining order with parallel access data streams

Configuration based cache coherency protocol selection

Recovery improvement for quiesced systems

Recovery improvement for quiesced systems

Quiesce handling in multithreaded environments

Quiesce handling in multithreaded environments

Monitoring processing time in a shared pipeline

Bitline deletion

Bitline deletion

EDRAM refresh in a high performance cache architecture

Optimizing EDRAM refresh rates in a high performance cache architecture

Preemptive in-pipeline store compare resolution

Handling corrupted background data in an out of order execution environment

Multiple level linked LRU priority

Memory system for error checking fetch and store data

Dynamic pipeline cache error correction

DYNAMIC RE-ALLOCATION OF CACHE BUFFER SLOTS

Error detection and recovery in a shared pipeline

Monitoring processing time in a shared pipeline

Diagnostic data collection and storage put-away station in a multiprocessor system

Method for optimizing sequential data fetches in a computer system

Preemptive in-pipeline store compare resolution

Dynamically altering a pipeline controller mode based on resource availability

On demand allocation of cache buffer slots

Dynamic trailing edge latency absorption for fetch data forwarded from a shared data/control interface

Clock-based debugging for embedded dynamic random access memory element in a processor core

Optimizing EDRAM refresh rates in a high performance cache architecture

eDRAM refresh in a high performance cache architecture

Managing dataflow in a temporary memory

Dynamic data transfer control method and apparatus for shared SMP computer systems

Method for Stabilizing Asynchronous Interfaces

Computer system apparatus for stabilizing asynchronous interfaces

Late data launch for a double data rate elastic interface

Double data rate chaining for synchronous DDR interfaces

Method for resource sharing in a multiple pipeline environment

Early directory access of a double data rate elastic interface