Inventor profile of:

David Asher

City:

Sutton, Massachusetts

Country:

United States

Published Applications:

17

Last publication date:

2023-07-20

Top Assignees for applications by David Asher

The entities that hold a legal rights for patent applications filed by inventor Asher David:

Recent patent applications by Asher David

David Asher from Sutton, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-07-20
US20230229595A1
Physics

Low latency inter-chip communication mechanism in a multi-chip processing system

#2 | 2022-07-05
US16862705
Physics

Differential cache block sizing for computing systems

#3 | 2021-12-02
US20210374057A1
Physics

Low latency inter-chip communication mechanism in a multi-chip processing system

#4 | 2020-08-06
US20200250088A1
Physics

Low latency inter-chip communication mechanism in multi-chip processing system

#5 | 2020-03-26
US20200097292A1
Physics

Managing low-level instructions and core interactions in multi-core processors

#6 | 2018-12-27
US20180373635A1
Physics

Managing cache partitions based on cache usage information

#7 | 2018-10-11
US20180293114A1
Physics

Managing fairness for lock and unlock operations using operation prioritization

#8 | 2018-10-11
US20180293113A1
Physics

Managing lock and unlock operations using active spinning

#9 | 2018-10-11
US20180293100A1
Physics

Managing lock and unlock operations using traffic prioritization

#10 | 2018-10-11
US20180293070A1
Physics

Managing lock and unlock operations using operation prediction

#11 | 2017-08-03
US20170220477A1
Physics

Method and apparatus for determining metric for selective caching

#12 | 2016-09-15
US20160267209A1
Physics

Verification of a multichip coherence protocol

#13 | 2016-05-19
US20160140061A1
Physics

Managing buffered communication between cores

#14 | 2016-05-19
US20160140060A1
Physics

Managing buffered communication between sockets

#15 | 2016-05-19
US20160140047A1
Physics

Translation lookaside buffer management

#16 | 2015-10-22
US20150302133A1
Physics

System and method for automated functional coverage generation and management for IC design protocols

#17 | 2015-06-04
US20150154341A1
Physics

Systems and methods for specifying. modeling, implementing and verifying IC design protocols

InventorID:

1182977 ⎘