Rodney E. Hooker

Cache memory budgeted by ways based on memory access type

Processor with memory controller including dynamically programmable functional unit

Sanitize-aware DRAM controller

Dynamic powering of cache memory by ways within multiple set groups based on utilization trends

Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests

Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests

Processor with an expandable instruction set architecture for dynamically configuring execution resources

Conversion system for a processor with an expandable instruction set architecture for dynamically configuring execution resources

Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources

Prefetching with level of aggressiveness based on effectiveness by memory access type

Set associative cache memory with heterogeneous replacement policy

Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type

Cache replacement policy that considers memory access type

Cache memory budgeted by chunks based on memory access type

Pattern detector for detecting hangs

Logic analyzer for detecting hangs

Conditional pattern detector for detecting hangs

Cache memory diagnostic writeback

CACHE SYSTEM WITH A PRIMARY CACHE AND AN OVERFLOW FIFO CACHE

Microprocessor with arm and X86 instruction length decoders

Fully associative cache memory budgeted by memory access type

Cache system with a primary cache and an overflow cache that use different indexing schemes

ASYMMETRIC PROCESSOR WITH CORES THAT SUPPORT DIFFERENT ISA INSTRUCTION SUBSETS

Dynamically updating hardware prefetch trait to exclusive or shared in multi-memory access agent system

Dynamically updating hardware prefetch trait to exclusive or shared at program detection

Dynamic system configuration based on cloud-collaborative experimentation

Dynamically configurable system based on cloud-collaborative experimentation

Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry

Processor that recovers from excessive approximate computing error

Processor with approximate computing execution unit that includes an approximation control register having an approximation mode flag, an approximation amount, and an error threshold, where the approximation control register is writable by an instruction set instruction

Processor that performs approximate computing instructions

Fractional use of prediction history storage for operating system routines

Fingerprint units comparing stored static fingerprints with dynamically generated fingerprints and reconfiguring processor settings upon a fingerprint match

Inter-core communication via uncore RAM

Microprocessor with boot indicator that indicates a boot ISA of the microprocessor as either the X86 ISA or the ARM ISA

Selective accumulation and use of predicting unit history

Communicating prefetchers that throttle one another

Asymmetric multi-core processor with native switching mechanism

Uncore microcode ROM

Bounding box prefetcher

Communicating prefetchers in a microprocessor

Microprocessor that translates conditional load/store instructions into variable number of microinstructions

Conditional store instructions in an out-of-order execution microprocessor

Conditional load instructions in an out-of-order execution microprocessor

PREFETCHING OF NEXT PHYSICALLY SEQUENTIAL CACHE LINE AFTER CACHE LINE THAT INCLUDES LOADED PAGE TABLE ENTRY

Deadlock/livelock resolution using service processor

Conditional non-branch instruction prediction

Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)

Efficient data prefetching in the presence of load hits

Efficient data prefetching in the presence of load hits

Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor

Efficient conditional ALU instruction in read-port limited register file microprocessor

EMULATION OF EXECUTION MODE BANKED REGISTERS

Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor

Generating constant for microinstructions from modified immediate field during instruction translation

Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline

Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA

Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline

Heterogeneous ISA microprocessor with shared hardware ISA registers

Load multiple and store multiple instructions in a microprocessor that emulates banked registers

Prefetching of next physically sequential cache line after cache line that includes loaded page table entry

Multi-modal data prefetcher

Combined L2 cache and L1D cache prefetcher

Bounding box prefetcher

Bounding box prefetcher with reduced warm-up penalty on memory block crossings

Multi-core processor with external instruction execution rate heartbeat

Executing repeat load string instruction with guaranteed prefetch microcode to prefetch into cache for loading up to the last value in architectural register

Avoiding memory access latency by returning hit-modified when holding non-modified data

Apparatus and method for detection and correction of denormal speculative floating point operand

Fast REP STOS using grabline operations

Efficient pseudo-LRU for colliding accesses

Store-to-load forwarding based on load/store address computation source information comparisons

Microprocessor with ALU integrated into store unit

Microprocessor with ALU integrated into load unit

Microprocessor with repeat prefetch indirect instruction

DATA PREFETCHER WITH MULTI-LEVEL TABLE FOR PREDICTING STRIDE PATTERNS

Efficient data prefetching in the presence of load hits

DYNAMIC FLOATING POINT REGISTER PRECISION CONTROL

OUT-OF-ORDER EXECUTION MICROPROCESSOR WITH REDUCED STORE COLLISION LOAD REPLAY REDUCTION

Out-of-order execution microprocessor with reduced store collision load replay reduction

Out-of-order execution microprocessor with reduced store collision load replay by making an issuing of a load instruction dependent upon a dependee instruction of a store instruction

Microprocessor that refrains from executing a mispredicted branch in the presence of an older unretired cache-missing load instruction

Guaranteed prefetch instruction

Data cache with modified bit array

Data cache with modified bit array

Low power high speed load-store collision detector

Prefetching of next physically sequential cache line after cache line that includes loaded page table entry

Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register

Microprocessor with fused store address/store data microinstruction

Microprocessor cache line evict array

MICROPROCESSOR THAT PERFORMS STORE FORWARDING BASED ON COMPARISON OF HASHED ADDRESS BITS

Microprocessor with multiple operating modes dynamically configurable by a device driver based on currently running applications

Microprocessor that performs speculative tablewalks

Microprocessor with microarchitecture for efficiently executing read/modify/write memory operand instructions

Microprocessor with private microcode RAM

Apparatus and method for extending data modes in a microprocessor

Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor

Apparatus and method for selective control of results write back

Mechanism for extending the number of registers in a microprocessor

Non-temporal memory reference control mechanism