Inventor profile of:

Ranjith KUMAR

City:

Beaverton, Oregon

Country:

United States

Published Applications:

14

Last publication date:

2025-07-10

Top Assignees for applications by Ranjith KUMAR

The entities that hold a legal rights for patent applications filed by inventor KUMAR Ranjith:

Recent patent applications by KUMAR Ranjith

Ranjith KUMAR from Beaverton, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-07-10
US20250225306A1
Physics

MULTI VERSION LIBRARY CELL HANDLING AND INTEGRATED CIRCUIT STRUCTURES FABRICATED THEREFROM

#2 | 2024-10-31
US20240362391A1
Physics

MULTI VERSION LIBRARY CELL HANDLING AND INTEGRATED CIRCUIT STRUCTURES FABRICATED THEREFROM

#3 | 2023-02-16
US20230046755A1
Electricity

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

#4 | 2022-05-12
US20220149075A1
Electricity

Multi version library cell handling and integrated circuit structures fabricated therefrom

#5 | 2022-01-27
US20220028779A1
Electricity

Integrated circuit device with crenellated metal trace layout

#6 | 2021-06-03
US20210167066A1
Electricity

Metal space centered standard cell architecture to enable higher cell density

#7 | 2021-02-11
US20210043755A1
Electricity

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

#8 | 2020-11-12
US20200357823A1
Electricity

Multi version library cell handling and integrated circuit structures fabricated therefrom

#9 | 2020-10-01
US20200311332A1
Physics

Pin must-connects for improved performance

#10 | 2020-09-03
US20200279069A1
Physics

Power shared cell architecture

#11 | 2020-08-06
US20200251464A1
Electricity

Standard cell architecture with power tracks completely inside a cell

#12 | 2019-10-10
US20190312023A1
Electricity

Integrated circuit device with crenellated metal trace layout

#13 | 2019-08-15
US20190252525A1
Electricity

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

#14 | 2018-07-19
US20180204932A1
Electricity

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

InventorID:

2248404 ⎘