Austin, Texas
United States
94
2023-09-28
The entities that hold a legal rights for patent applications filed by inventor Andre Thomas:
Thomas Andre from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Magnetoresistive stack/structure and methods therefor
#2 | 2023-03-30Methods of forming magnetoresistive devices and integrated circuits
#3 | 2021-04-22Methods of forming magnetoresistive devices and integrated circuits
#4 | 2020-09-10Methods of forming magnetoresistive devices and integrated circuits
#5 | 2020-07-23Shared spin-orbit-torque write line in a spin-orbit-torque MRAM
#6 | 2020-07-23In-plane spin orbit torque magnetoresistive stack/structure and methods therefor
#7 | 2019-10-15Bitline control in differential magnetic memory
#8 | 2019-07-18Circuit for wordline autobooting in memory and method therefor
#9 | 2019-07-18Feed forward bias system for MTJ voltage control
#10 | 2019-06-27ECC word configuration for system-level ECC compatibility
#11 | 2019-05-28Dual-edge trigger asynchronous clock generation and related methods
#12 | 2019-05-23WRITE VERIFY PROGRAMMING OF A MEMORY DEVICE
#13 | 2019-05-16Short detection and inversion
#14 | 2019-03-21BURST LENGTH DEFINED PAGE SIZE AND RELATED METHODS
#15 | 2019-03-21METHODS AND DEVICES FOR HEALING RESET ERRORS IN A MAGNETIC MEMORY
#16 | 2019-02-07Magnetoresistive device design and process integration with surrounding circuitry
#17 | 2018-10-16Magnetoresistive device design and process integration with surrounding circuitry
#18 | 2018-09-20Delayed write-back in memory
#19 | 2018-05-03Short detection and inversion
#20 | 2018-03-06Selection circuit with autobooting for magnetic memory and methods therefor
#21 | 2017-11-23Nonvolatile logic and security circuits
#22 | 2017-11-02Delayed write-back in memory
#23 | 2017-10-19Self-referenced read with offset current in a memory
#24 | 2017-09-14Write verify programming of a memory device
#25 | 2017-07-18Magnetoresistive device design and process integration with surrounding circuitry
#26 | 2017-06-22Word line auto-booting in a spin-torque magnetic memery having local source lines
#27 | 2017-04-13ECC word configuration for system-level ECC compatibility
#28 | 2017-03-30Circuit and method for controlling MRAM cell bias voltages
#29 | 2017-03-23Memory system with timing overlap mode for activate and precharge operations
#30 | 2017-03-23Non-destructive write/read leveling
#31 | 2017-03-09Short detection and inversion
#32 | 2017-03-02Memory device with page emulation mode
#33 | 2017-02-21Memory device with reduced test time
#34 | 2017-01-24Memory device with sampled resistance controlled write voltages
#35 | 2016-12-01Memory controller and method for interleaving DRAM and MRAM accesses
#36 | 2016-10-20Self-referenced read with offset current in a memory
#37 | 2016-10-18Magnetic memory having two transistors and two magnetic tunnel junctions per memory cell
#38 | 2016-09-22Method for writing to a magnetic tunnel junction device
#39 | 2016-09-22Method of writing to a spin torque magnetic random access memory
#40 | 2016-09-01Nonvolatile logic and security circuits
#41 | 2016-09-01Boosted supply voltage generator and method therefore
#42 | 2016-08-09Magnetoresistive device design and process integration with surrounding circuitry
#43 | 2016-06-23Word line auto-booting in a spin-torque magnetic memory having local source lines
#44 | 2016-06-16Boosted supply voltage generator for a memory device and method therefore
#45 | 2016-06-09Non-destructive write/read leveling
#46 | 2016-04-14Memory device with timing overlap mode and precharge timing circuit
#47 | 2016-04-12Word line supply voltage generator for a memory device and method therefore
#48 | 2016-04-07Self-referenced sense amplifier for spin-torque MRAM
#49 | 2016-04-07Method of writing to a spin torque magnetic random access memory
#50 | 2016-03-31Short detection and inversion
#51 | 2016-03-31Write verify programming of a memory device
#52 | 2016-03-31Memory device with shared amplifier circuitry
#53 | 2016-03-31ECC word configuration for system-level ECC compatibility
#54 | 2016-03-24Expanded error correction codes
#55 | 2016-03-10Response to tamper detection in a memory device
#56 | 2016-02-11Circuit and method for accessing a bit cell in a spin-torque MRAM
#57 | 2016-02-11Circuit and method for controlling MRAM cell bias voltages
#58 | 2016-01-28Hybrid read scheme for spin torque MRAM
#59 | 2016-01-21Memory controller and method for interleaving DRAM and MRAM accesses
#60 | 2016-01-05Word line driver circuit
#61 | 2015-12-10Tamper detection and response in a memory device
#62 | 2015-12-10Method of reading and writing to a spin torque magnetic random access memory with error correcting code
#63 | 2015-09-17Nonvolatile logic and security circuits
#64 | 2015-09-10Word line auto-booting in a spin-torque magnetic memory having local source lines
#65 | 2015-09-10Assisted local source line
#66 | 2015-09-10Burst length defined page size
#67 | 2015-08-27Method of writing to a spin torque magnetic random access memory
#68 | 2015-07-23Circuit and method for spin-torque MRAM bit line and source line voltage regulation
#69 | 2015-07-16Memory device with reduced on-chip noise
#70 | 2015-05-07Memory device with timing overlap mode
#71 | 2015-04-23Method for writing to a magnetic tunnel junction device
#72 | 2015-04-14Word line driver circuit
#73 | 2015-02-26Non-destructive write/read leveling
#74 | 2015-01-29Self-referenced sense amplifier for spin torque MRAM
#75 | 2015-01-15Memory device with page emulation mode
#76 | 2015-01-01Method of writing to a spin torque magnetic random access memory
#77 | 2014-12-18Methods and devices for healing reset errors in a magnetic memory
#78 | 2014-08-14Response to tamper detection in a memory device
#79 | 2014-08-14Tamper detection and response in a memory device
#80 | 2014-04-17Memory device with reduced on-chip noise
#81 | 2014-04-17Memory device with timing overlap mode
#82 | 2013-11-21Circuit and method for controlling MRAM cell bias voltages
#83 | 2013-10-17Self-referenced sense amplifier for spin torque MRAM
#84 | 2013-06-20Circuit and method for spin-torque MRAM bit line and source line voltage regulation
#85 | 2013-05-23Write driver circuit and method for writing to a spin-torque MRAM
#86 | 2013-05-23Hybrid read scheme for spin torque MRAM
#87 | 2013-05-23Data-masked analog and digital read for resistive memories
#88 | 2012-12-06MRAM field disturb detection and recovery
#89 | 2012-08-02Method of reading and writing to a spin torque magnetic random access memory with error correcting code
#90 | 2012-08-02Method of writing to a spin torque magnetic random access memory
#91 | 2012-06-28Memory array having local source lines
#92 | 2012-06-21Memory controller and method for interleaving DRAM and MRAM accesses
#93 | 2011-12-01Structures and methods for a field-reset spin-torque MRAM
#94 | 2009-11-26Memory circuit with sense amplifier
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