Leuven
Belgium
31
2024-03-21
The entities that hold a legal rights for patent applications filed by inventor Badaroglu Mustafa:
Mustafa Badaroglu from Leuven, BE has applied for patents for these inventions. The list has both pending applications and granted patents:
PORT LANDING-FREE LOW-SKEW SIGNAL DISTRIBUTION WITH BACKSIDE METALLIZATION AND BURIED RAIL
#2 | 2023-07-27Trench power rail in cell circuits to reduce resistance and related power distribution networks and fabrication methods
#3 | 2023-04-13ACCUMULATOR FOR DIGITAL COMPUTATION-IN-MEMORY ARCHITECTURES
#4 | 2023-03-02PARALLEL DEPTH-WISE PROCESSING ARCHITECTURES FOR NEURAL NETWORKS
#5 | 2023-02-16PARTIAL SUM MANAGEMENT AND RECONFIGURABLE SYSTOLIC FLOW ARCHITECTURES FOR IN-MEMORY COMPUTATION
#6 | 2023-02-02Digital compute in memory
#7 | 2023-02-02FOLDING COLUMN ADDER ARCHITECTURE FOR DIGITAL COMPUTE IN MEMORY
#8 | 2023-01-26HYBRID MACHINE LEARNING ARCHITECTURE WITH NEURAL PROCESSING UNIT AND COMPUTE-IN-MEMORY PROCESSING ELEMENTS
#9 | 2022-12-08Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM arrays for multiple operations per column
#10 | 2018-04-26Semiconductor device having a gap defined therein
#11 | 2017-06-29Nanowire device with reduced parasitics
#12 | 2017-05-18Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices
#13 | 2017-04-13Magnetic tunnel junction (MTJ) device array
#14 | 2017-04-13METHOD AND APPARATUS FOR SOURCE-DRAIN JUNCTION FORMATION IN A FINFET WITH IN-SITU DOPING
#15 | 2017-02-02Adjacent device isolation
#16 | 2016-10-06Self-aligned structure
#17 | 2016-09-01Adjacent device isolation
#18 | 2016-08-18Reduced height M1 metal lines for local on-chip routing
#19 | 2016-08-04Magnetic tunnel junction (MTJ) device array
#20 | 2016-06-23Sub-fin device isolation
#21 | 2016-05-26Contact wrap around structure
#22 | 2016-05-12SEMICONDUCTOR PACKAGE WITH INCORPORATED INDUCTANCE ELEMENT
#23 | 2016-03-24Method and apparatus for source-drain junction formation in a FinFET with in-situ doping
#24 | 2016-02-18DEVICE INCLUDING CAVITY AND SELF-ALIGNED CONTACT AND METHOD OF FABRICATING THE SAME
#25 | 2015-09-17Reduced height M1 metal lines for local on-chip routing
#26 | 2015-09-10Semiconductor device having a gap defined therein
#27 | 2013-01-03Test circuit for testing through-silicon-vias in 3D integrated circuits
#28 | 2010-09-09Devices comprising delay line for applying variable delay to clock signal
#29 | 2008-01-31Method for determining a pulse position in a signal
#30 | 2007-02-15Method and apparatus for minimizing the influence of a digital sub-circuit on at least partially digital circuits
#31 | 2005-09-06Method, apparatus and computer program product for determination of noise in mixed signal systems
5446 ⎘