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Inventor profile of:

Lorenzo Bedarida

City:

Vimercate

Country:

Italy

Published Applications:

Last publication date:

2026-05-14

Top Assignees for applications by Lorenzo Bedarida

The entities that hold a legal rights for patent applications filed by inventor Bedarida Lorenzo:

ATMEL CORPORATION 19 San Jose, CA United States
STMICROELECTRONICS S.R.L. 2 Agrate Brianza, Italy
MICROCHIP TECHNOLOGY INCORPORATED 1 Chandler, AZ United States

Recent patent applications by Bedarida Lorenzo

Lorenzo Bedarida from Vimercate, IT has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-05-14

US20260134927A1

Physics

DUAL READ MODE NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE

#2 | 2026-05-14

US20260133792A1

Physics

ALGORITHMS FOR UPDATING SOFTWARE CODE IN FLASH MEMORY DURING SYSTEM OPERATION

#3 | 2026-04-23

US20260114299A1

Electricity

MULTI-CHIPLET SEMICONDUCTOR DEVICE WITH REDUNDANT DATA LINE

#4 | 2025-09-25

US20250301667A1

Electricity

SEMICONDUCTOR DEVICE WITH NON-PLANAR MOSFET DEVICE DIE AND PLANAR MOSFET DEVICE DIE

#5 | 2019-07-25

US20190228831A1

Physics

Memory device, memory address decoder, system, and related method for memory attack detection

#6 | 2016-12-29

US20160380596A1

Electricity

Sense amplifier

#7 | 2016-07-14

US20160204746A1

Electricity

Sense amplifier

#8 | 2013-12-05

US20130322185A1

Physics

Memory decoder circuit

#9 | 2010-06-17

US20100149896A1

Physics

Sense amplifier

#10 | 2010-01-21

US20100014370A1

Physics

Precharge and evaluation phase circuits for sense amplifiers

#11 | 2009-04-30

US20090109754A1

Physics

Non-volatile memory array architecture with joined word lines

#12 | 2008-07-17

US20080170455A1

Physics

Compensated current offset in a sensing circuit

#13 | 2008-07-17

US20080170454A1

Physics

Sense amplifier with stages to reduce capacitance mismatch in current mirror load

#14 | 2008-07-17

US20080170442A1

Physics

Column leakage compensation in a sensing circuit

#15 | 2008-07-17

US20080170441A1

Physics

Sense architecture

#16 | 2008-07-10

US20080164948A1

Electricity

Biasing current to speed up current mirror settling time

#17 | 2006-08-03

US20060170490A1

Physics

Fast dynamic low-voltage current mirror with compensated error

#18 | 2006-08-03

US20060170489A1

Physics

Fast dynamic low-voltage current mirror with compensated error

#19 | 2006-06-29

US20060140030A1

Physics

System for performing fast testing during flash reference cell setting

#20 | 2006-04-20

US20060083060A1

Physics

Flexible OTP sector protection architecture for flash memories

#21 | 2005-11-08

US10328721

Autotesting method of a memory cell matrix, particularly of the non-volatile type

#22 | 2005-10-13

US20050226051A1

Physics

Fast dynamic low-voltage current mirror with compensated error

#23 | 2005-09-01

US20050189983A1

Electricity

High precision digital-to-analog converter with optimized power consumption

#24 | 2005-04-07

US20050073355A1

Electricity

High precision digital-to-analog converter with optimized power consumption

#25 | 2005-03-29

US10622804

Apparatus and method for a configurable mirror fast sense amplifier

#26 | 2005-02-08

US9717938

Non-volatile memory device with burst mode reading and corresponding reading method

InventorID:

556064 ⎘