AUSTIN, Texas
United States
75
2014-09-25
The entities that hold a legal rights for patent applications filed by inventor CASES MOISES:
MOISES CASES from AUSTIN, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MINIMIZING PLATING STUB REFLECTIONS IN A CHIP PACKAGE USING CAPACITANCE
#2 | 2014-05-08Through-hole-vias in multi-layer printed circuit boards
#3 | 2013-01-31Manufacturing a printed circuit board with reduced dielectric loss
#4 | 2012-12-27Pre-distortion based impedence discontinuity remediation for via stubs and connectors in printed circuit board design
#5 | 2012-08-09Through-hole-vias in multi-layer printed circuit boards
#6 | 2012-08-02Through-hole-vias in multi-layer printed circuit boards
#7 | 2012-07-19Generating an optimized analytical business transformation
#8 | 2012-06-28Controlling plating stub reflections in a chip package
#9 | 2012-02-09Mitigation of plating stub resonance by controlling surface roughness
#10 | 2012-01-05Managing and Providing Healthcare Services
#11 | 2011-12-15Printed circuit board with reduced dielectric loss
#12 | 2011-11-24Electrical design space exploration
#13 | 2011-11-03Measuring SDRAM control signal timing
#14 | 2011-06-30Space solution search
#15 | 2011-06-23Receiver signal probing using a shared probe point
#16 | 2011-06-16Locating short circuits in printed circuit boards
#17 | 2011-06-09Reducing plating stub reflections in a chip package using resistive coupling
#18 | 2011-06-02Cable for high speed data communications
#19 | 2011-05-05Packages and Methods for Mitigating Plating Stub Effects
#20 | 2011-03-31Through hole-vias in multi-layer printed circuit boards
#21 | 2011-03-17REDUCING CROSS-TALK IN HIGH SPEED CERAMIC PACKAGES USING SELECTIVELY-WIDENED MESH
#22 | 2011-01-11Off-die termination module with a spring loaded pin in a DIMM socket
#23 | 2011-01-11Off-die termination of memory module signal lines
#24 | 2010-11-25Transmission cable with spirally wrapped shielding
#25 | 2010-10-07Airflow optimization and noise reduction in computer systems
#26 | 2010-09-16Testing an electrical component
#27 | 2010-09-09Swarm intelligence for electrical design space modeling and optimization
#28 | 2010-06-03OPTIMIZATION OF DATA DISTRIBUTION AND POWER CONSUMPTION IN A DATA CENTER
#29 | 2010-05-13Dynamically managing power consumption of a computer with graphics adapter configurations
#30 | 2010-05-06Cable for high speed data communications
#31 | 2010-04-22Workflow management in a global support organization
#32 | 2010-04-22Mitigation of plating stub resonance by controlling surface roughness
#33 | 2010-03-25Minimizing plating stub reflections in a chip package using capacitance
#34 | 2010-03-11ELECTROMAGNETIC BAND GAP TUNING USING UNDULATING BRANCHES
#35 | 2010-03-04Intelligent problem tracking electronic system for optimizing technical support
#36 | 2010-01-21Identifying an optimized test bit pattern for analyzing electrical communications channel topologies
#37 | 2009-12-17Printed circuit board with reduced signal distortion
#38 | 2009-12-10SOLUTION EFFICIENCY OF GENETIC ALGORITHM APPLICATIONS
#39 | 2009-11-26Technical support routing among members of a technical support group
#40 | 2009-10-22Generating an optimized analytical business transformation
#41 | 2009-09-17Cable For High Speed Data Communications
#42 | 2009-07-02Method and apparatus for jitter compensation in receiver circuits using nonlinear dynamic phase shifting technique based on bit history pattern
#43 | 2009-07-02Cable for high speed data communications
#44 | 2009-06-04Workflow control in a resource hierarchy
#45 | 2009-04-30Reducing noise coupling in high speed digital systems
#46 | 2009-04-30Method for reducing noise coupling in high speed digital systems
#47 | 2009-04-28Method and apparatus to electrically qualify high speed PCB connectors
#48 | 2009-04-23Method for validating printed circuit board materials for high speed applications
#49 | 2009-04-09STRUCTURE FOR PROVIDING A DUPLICATE TEST SIGNAL OF AN OUTPUT SIGNAL UNDER TEST IN AN INTEGRATED CIRCUIT
#50 | 2009-04-09Providing A Duplicate Test Signal Of An Output Signal Under Test In An Integrated Circuit
#51 | 2009-03-26Apparatus, system, and method for integrated component testing
#52 | 2009-03-26Electromagnetic morphing apparatus for hot pluggable architected systems
#53 | 2009-02-19METHOD AND SYSTEM FOR REDUCING VIA STUB RESONANCE
#54 | 2009-02-19Method for performing memory diagnostics using a programmable diagnostic memory module
#55 | 2009-02-19Programmable diagnostic memory module
#56 | 2009-01-29Managing organizational resources
#57 | 2009-01-22Method and apparatus for repeatable drive strength assessments of high speed memory DIMMs
#58 | 2009-01-20High-speed cable having increased current return uniformity and method of making same
#59 | 2009-01-20Conductor cable having a high surface area
#60 | 2009-01-15SELF-HEALING NOISE DISPERSION SYSTEM FOR HIGH PERFORMANCE MULTIDROP SYSTEMS
#61 | 2009-01-06Bi-directional universal serial bus booster circuit
#62 | 2009-01-01DESIGN STRUCTURE FOR A COMPUTER MEMORY SYSTEM WITH A SHARED MEMORY MODULE JUNCTION CONNECTOR
#63 | 2008-12-18Cable for high speed data communications
#64 | 2008-12-04BUS ARCHITECTURE
#65 | 2008-10-23Pre-distortion based impedence discontinuity remediation for via stubs and connectors in printed circuit board design
#66 | 2008-10-23Noise Reduction Among Conductors
#67 | 2008-07-01Bi-directional universal serial bus booster circuit
#68 | 2008-06-26MULTI-PATH REDUNDANT ARCHITECTURE FOR FAULT TOLERANT FULLY BUFFERED DIMMS
#69 | 2008-06-12On-chip probing apparatus
#70 | 2008-05-15Apparatus, system, and method for dynamic phase equalization in a communication channel
#71 | 2007-11-08Multi-memory module circuit topology
#72 | 2007-09-06Learning a predicted voltage to supply an electronic device based on dynamic voltage variation
#73 | 2007-08-02High-speed routing composite material
#74 | 2007-01-11Apparatus and method for achieving thermal management through the allocation of redundant data processing devices
#75 | 2006-12-14Apparatus, system, and method for modifying memory voltage and performance based on a measure of memory device stress
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