James W. Adkisson

Heterojunction bipolar transistors with an inverted crystalline boundary in the base layer

Heterojunction bipolar transistors with multiple emitter fingers and undercut extrinsic base regions

Heterojunction bipolar transistors with a controlled undercut formed beneath the extrinsic base

Switchable filters and design structures

Contact module for optimizing emitter and contact resistance

Methods of tuning current ratio in a current mirror for transistors formed with the same FEOL layout and a modified BEOL layout

Switchable filters and design structures

Switchable filters and design structures

Backside integration of RF filters for RF front end modules and design structure

Implementing stress in a bipolar junction transistor

Replacement emitter for reduced contact resistance

FIELD EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED DOUBLE GATES ON BULK SILICON SUBSTRATE, METHODS OF FORMING, AND RELATED DESIGN STRUCTURES

BIPOLAR TRANSISTOR WITH EXTRINSIC BASE REGION AND METHODS OF FABRICATION

Contact module for optimizing emitter and contact resistance

Switchable filters and design structures

Switchable filters and design structures

Bipolar transistor with extrinsic base region and methods of fabrication

Tsv wafer with improved fracture strength

Switchable filters and design structures

Bipolar junction transistors with reduced base-collector junction capacitance

Methods of forming a TSV wafer with improved fracture strength

Tunable filter structures and design structures

Backside integration of RF filters for RF front end modules and design structure

Field effect transistor (FET) with self-aligned double gates on bulk silicon substrate, methods of forming, and related design structures

Switchable filters and design structures

Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening

NANOPARTICLES FOR MAKING SUPERCAPACITOR AND DIODE STRUCTURES

Method to bridge extrinsic and intrinsic base by selective epitaxy in BiCMOS technology

Semiconductor device and method of forming the device by forming monocrystalline semiconductor layers on a dielectric layer over isolation regions

Pixel sensor cell with hold node for leakage cancellation and methods of manufacture and design structure

COLLECTOR-UP BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY

Collector-up bipolar junction transistors in BiCMOS technology

Bipolar junction transistors with reduced base-collector junction capacitance

Graphene field effect transistor

Method to bridge extrinsic and intrinsic base by selective epitaxy in BiCMOS technology

Method of manufacturing switchable filters

Transistor having a monocrystalline center section and a polycrystalline outer section, and narrow in-substrate collector region for reduced base-collector junction capacitance

Method of manufacturing switching filters and design structures

Backside integration of RF filters for RF front end modules and design structure

Method of manufacturing switchable filters

Anti-reflection structures for CMOS image sensors

SAW FILTER HAVING PLANAR BARRIER LAYER AND METHOD OF MAKING

ASYMMETRIC ANTI-HALO FIELD EFFECT TRANSISTOR

Method of manufacturing a film bulk acoustic resonator with a loading element

Graphene field effect transistor

Graphene field effect transistor

Bipolar transistor with a raised collector pedestal for reduced capacitance

Bipolar transistor with a collector having a protected outer edge portion for reduced based-collector junction capacitance and a method of forming the transistor

Tunable filter structures and design structures

Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening

Metal insulator metal (MIM) capacitor structure

Passivated through wafer vias in low-doped semiconductor substrates

Anti-reflection structures for CMOS image sensors

CMOS imager photodiode with enhanced capacitance

Self-dicing chips using through silicon vias

Bond pad for wafer and package for CMOS imager

Pixel sensor cell with hold node for leakage cancellation and methods of manufacture and design structure

CMOS pixel sensor cells with poly spacer transfer gates and methods of manufacture

ISOLATION WITH OFFSET DEEP WELL IMPLANTS

Methods for forming anti-reflection structures for CMOS image sensors

Charge Carrier Barrier for Image Sensor

CMOS image sensor with reduced dark current

Isolation with offset deep well implants

Anti-reflection structures for CMOS image sensors

Methods of forming silicide strapping in imager transfer gate device

High efficiency CMOS image sensor pixel employing dynamic voltage supply

On demand circuit function execution employing optical sensing

CMOS imager photodiode with enhanced capacitance

Bond pad for wafer and package for CMOS imager

Pixel sensor cell with frame storage capability

Pixel sensor cell with frame storage capability

Methods for forming anti-reflection structures for CMOS image sensors

Anti-reflection structures for CMOS image sensors

Fully-depleted low-body doping field effect transistor (FET) with reverse short channel effects (SCE) induced by self-aligned edge back-gate(s)

Pixel sensor with reduced image lag

CMOS image sensor with reduced dark current

High efficiency CMOS image sensor pixel employing dynamic voltage supply

Modifying layout of IC based on function of interconnect and related circuit and design structure

Low lag transfer gate device

Low lag transfer gate device

Stacked imager package

Lateral diffusion field effect transistor with asymmetric gate dielectric profile

DUAL WORK FUNCTION HIGH VOLTAGE DEVICES

Semiconductor chip scale package incorporating through-vias electrically connected to a substrate and other vias that are isolated from the substrate, and method of forming the package

CHARGE CARRIER BARRIER FOR IMAGE SENSOR

Pixel sensor cell having a pinning layer surrounding collection well regions for collecting electrons and holes

Method of forming a pixel sensor cell for collecting electrons and holes

Pixel sensor cell for collecting electrons and holes

Pixel sensor cell for collecting electrons and holes

Flip FERAM cell and method to form same

High surface area aluminum bond pad for through-wafer connections to an electronic package

Silicide strapping in imager transfer gate device

CMOS imager array with recessed dielectric

Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof

CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom

Stacked imager package

Stacked imager package

Bond pad for wafer and package for CMOS imager

ANTI-FUSE STRUCTURE OPTIONALLY INTEGRATED WITH GUARD RING STRUCTURE

Method of adding fabrication monitors to integrated circuit chips