Penryn, California
United States
38
2020-12-24
The entities that hold a legal rights for patent applications filed by inventor Eilert Sean:
Sean Eilert from Penryn, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Autonomous memory architecture
#2 | 2019-01-03Methods and systems for parsing and executing instructions to retrieve data using autonomous memory
#3 | 2018-11-08Memory device for a hierarchical memory architecture
#4 | 2018-01-25Autonomous memory architecture
#5 | 2017-12-07METHODS AND SYSTEMS FOR AUTONOMOUS MEMORY SEARCHING
#6 | 2017-08-03Memory device for a hierarchical memory architecture
#7 | 2015-12-24Memory device for a hierarchical memory architecture
#8 | 2015-12-03Transactional memory
#9 | 2015-08-06Error control in memory storage systems
#10 | 2015-07-23Autonomous memory subsystem architecture
#11 | 2015-06-04Packet processor receiving packets containing instructions, data, and starting location and generating packets containing instructions and data
#12 | 2015-02-19Methods and systems for autonomous memory searching
#13 | 2015-01-29Resting blocks of memory cells in response to the blocks being deemed to fail
#14 | 2014-11-27Apparatuses, systems, devices, and methods of replacing at least partially non-functional portions of memory
#15 | 2014-05-08Error control in memory storage systems
#16 | 2014-02-13Apparatuses, systems, devices, and methods of replacing at least partially non-functional portions of memory
#17 | 2013-12-05Error detection or correction of a portion of a codeword in a memory device
#18 | 2013-12-03Full chip wear leveling in memory device
#19 | 2013-08-06Error detection or correction of a portion of a codeword in a memory device
#20 | 2012-12-06Apparatuses, systems, devices, and methods of replacing at least partially non-functional portions of memory
#21 | 2012-11-01Hierarchical memory architecture to connect mass storage devices
#22 | 2012-08-30Error control in memory storage systems
#23 | 2012-08-02Transactional memory
#24 | 2012-05-31Preserving data integrity in a memory system
#25 | 2011-05-17Writing to non-volatile memory during a volatile memory refresh cycle
#26 | 2011-05-03Selective refresh of single bit memory cells
#27 | 2011-03-17Autonomous memory architecture
#28 | 2011-03-17Autonomous memory subsystem architecture
#29 | 2010-12-16Memory device for a hierarchical memory architecture
#30 | 2010-09-30Hierarchical memory architecture to connect mass storage devices
#31 | 2010-09-30Hierarchical memory architecture with a phase-change memory (PCM) content addressable memory (CAM)
#32 | 2010-09-30Hierarchical memory architecture using a concentrator device
#33 | 2010-09-30HIERARCHICAL MEMORY ARCHITECTURE WITH AN INTERFACE TO DIFFERING MEMORY FORMATS
#34 | 2009-10-01WIRELESS PROGRAMMING OF NON-VOLATILE MEMORY WITH NEAR-FIELD UHF COUPLING
#35 | 2008-06-19Method and apparatus of cache assisted error detection and correction in memory
#36 | 2008-05-29Memory architecture for separation of code and data in a memory device
#37 | 2007-05-31Multi-interfaced memory
#38 | 2006-10-19Monitoring the threshold voltage of frequently read cells
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