Thilo Scheiper

Reduced threshold voltage-width dependency in transistors comprising high-K metal gate electrode structures

LATE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS

Metal gate structure for semiconductor devices

Semiconductor device comprising a stacked die configuration including an integrated peltier element

Methods for fabricating integrated circuits having gate to active and gate to gate interconnects

Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Canyon gate transistor and methods for its fabrication

Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material

SOI semiconductor device comprising a substrate diode and a film diode formed by using a common well implantation mask

Methods of performing highly tilted halo implantation processes on semiconductor devices

Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Semiconductor device with strain-inducing regions and method thereof

SUBSTRATE DIODE FORMED BY ANGLED ION IMPLANTATION PROCESSES

Field effect transistors for a flash memory comprising a self-aligned charge storage region

Workfunction metal stacks for a final metal gate

Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts

METHODS OF FORMING FEATURES ON AN INTEGRATED CIRCUIT PRODUCT USING A NOVEL COMPOUND SIDEWALL IMAGE TRANSFER TECHNIQUE

METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED ELECTRICAL PARAMETER VARIATION

Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage

MULTIPLE STEP IMPLANT PROCESS FOR FORMING SOURCE/DRAIN REGIONS ON SEMICONDUCTOR DEVICES

Methods of Forming Device Level Conductive Contacts to Improve Device Performance and Semiconductor Devices Comprising Such Contacts

Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process

Semiconductor device with strain-inducing regions and method thereof

Canyon gate transistor and methods for its fabrication

Superior integrity of high-k metal gate stacks by forming STI regions after gate metals

Methods for fabricating integrated circuits having gate to active and gate to gate interconnects

Methods of Forming Highly Scaled Semiconductor Devices Using a Reduced Number of Spacers

Methods of forming metal silicide regions on semiconductor devices using different temperatures

Methods of forming stressed silicon-carbon areas in an NMOS transistor

Methods of forming an anode and a cathode of a substrate diode by performing angled ion implantation processes

Semiconductor device with work function adjusting layer having varied thickness in a gate width direction and methods of making same

Semiconductor device with dual metal silicide regions and methods of making same

Methods of forming a semiconductor device with recessed source/design regions, and a semiconductor device comprising same

Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask

Full silicidation prevention via dual nickel deposition approach

Method of forming contacts for devices with multiple stress liners

Method of forming spacers that provide enhanced protection for gate electrode structures

Dual Cavity Etch for Embedded Stressor Regions

Method of increasing the germanium concentration in a silicon-germanium layer and semiconductor device comprising same

SHORT CHANNEL TRANSISTOR WITH REDUCED LENGTH VARIATION BY USING AMORPHOUS ELECTRODE MATERIAL DURING IMPLANTATION

High-k metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning

Stabilization of Metal Silicides in PFET Transistors by Incorporation of Stabilizing Species in a Si/Ge Semiconductor Material

Superior integrity of high-k metal gate stacks by capping STI regions

Complementary stress liner to improve DGO/AVT devices and poly and diffusion resistors

High-K Metal Gate Electrode Structures Formed by a Replacement Gate Approach Based on Superior Planarity of Placeholder Materials

Stress Memorization Technique Using Gate Encapsulation

Drive current increase in field effect transistors by asymmetric concentration profile of alloy species of a channel semiconductor alloy

SOI semiconductor device comprising a substrate diode and a film diode formed by using a common well implantation mask

Self-aligned fin transistor formed on a bulk substrate by late fin etch

Transistor comprising an embedded sigma shaped sequentially formed semiconductor alloy

Strain Enhancement in Transistors Comprising an Embedded Strain-Inducing Semiconductor Material by Alloy Species Condensation

Patterning of a Stressed Dielectric Material in a Contact Level Without Using an Underlying Etch Stop Layer

Sacrificial spacer approach for differential source/drain implantation spacers in transistors comprising a high-k metal gate electrode structure

Low-diffusion drain and source regions in CMOS transistors for low power/high performance applications

Semiconductor device substrate with embedded stress region, and related fabrication methods

Reduced threshold voltage-width dependency in transistors comprising high-k metal gate electrode structures

Polysilicon Resistors Formed in a Semiconductor Device Comprising High-K Metal Gate Electrode Structures

Increased Charge Carrier Mobility in Transistors by Providing a Strain-Inducing Threshold Adjusting Semiconductor Material in the Channel

Strain Engineering in Three-Dimensional Transistors Based on a Strained Channel Semiconductor Material

Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage

Semiconductor device comprising a stacked die configuration including an integrated Peltier element

Self-aligned multiple gate transistor formed on a bulk substrate

Stress memorization with reduced fringing capacitance based on silicon nitride in MOS semiconductor devices

Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach

Field effect transistors for a flash memory comprising a self-aligned charge storage region

Strain memorization in strained SOI substrates of semiconductor devices

Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials

Transistor Comprising a Buried High-K Metal Gate Electrode Structure

Contact bars with reduced fringing capacitance in a semiconductor device

Semiconductor element comprising a low variation substrate diode

ADJUSTMENT OF TRANSISTOR CHARACTERISTICS BASED ON A LATE WELL IMPLANTATION

Replacement gate approach based on a reverse offset spacer applied prior to work function metal deposition

Enhanced integrity of a high-K metal gate electrode structure by using a sacrificial spacer for cap removal

High-K metal gate electrode structures formed at different process stages of a semiconductor device

Predoped semiconductor material for a high-K metal gate electrode structure of P- and N-channel transistors

Enhanced confinement of sensitive materials of a high-K metal gate electrode structure

Transistor including a high-K metal gate electrode structure formed on the basis of a simplified spacer regime

Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement

Performance enhancement in transistors comprising high-k metal gate stack by an early extension implantation

Work function adjustment in high-k gate stacks for devices of different threshold voltage

REDUCING THE SERIES RESISTANCE IN SOPHISTICATED TRANSISTORS BY EMBEDDING METAL SILICIDE CONTACT REGIONS RELIABLY INTO HIGHLY DOPED SEMICONDUCTOR MATERIAL

High-K metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning

Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer

TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED PRIOR TO DRAIN/SOURCE REGIONS ON THE BASIS OF A SUPERIOR IMPLANTATION MASKING EFFECT

Work function adjustment in high-k gate stacks including gate dielectrics of different thickness

Short channel transistor with reduced length variation by using amorphous electrode material during implantation

Recessed drain and source areas in combination with advanced silicide formation in transistors

Method for forming double gate and tri-gate transistors on a bulk substrate