Allen, Texas
United States
44
2019-06-06
The entities that hold a legal rights for patent applications filed by inventor PENDHARKAR Sameer P.:
Sameer P. PENDHARKAR from Allen, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Hybrid active-field gap extended drain MOS transistor
#2 | 2019-02-14Integrated trench capacitor
#3 | 2018-04-19Structures to avoid floating resurf layer in high voltage lateral devices
#4 | 2018-04-05Integrated high-side driver for P-N bimodal power device
#5 | 2018-03-15Integrated trench capacitor
#6 | 2017-09-14Integrated high-side driver for P-N bimodal power device
#7 | 2017-08-03Diluted drift layer with variable stripe widths for power transistors
#8 | 2017-05-04Poly sandwich for deep trench fill
#9 | 2017-03-23P-N bimodal transistors
#10 | 2017-01-10P-N bimodal conduction resurf LDMOS
#11 | 2016-11-24Hybrid active-field gap extended drain MOS transistor
#12 | 2016-11-17Diluted drift layer with variable stripe widths for power transistors
#13 | 2016-10-27High breakdown n-type buried layer
#14 | 2016-10-20Poly sandwich for deep trench fill
#15 | 2016-09-01Structures to avoid floating RESURF layer in high voltage lateral devices
#16 | 2016-08-30Diluted drift layer with variable stripe widths for power transistors
#17 | 2016-08-30Deep trench with self-aligned sinker
#18 | 2016-08-04Implant profiling with resist
#19 | 2016-05-26Poly sandwich for deep trench fill
#20 | 2016-03-31High voltage multiple channel LDMOS
#21 | 2015-11-26Transistor having double isolation with one floating isolation
#22 | 2015-10-29High breakdown N-type buried layer
#23 | 2015-07-02High voltage multiple channel LDMOS
#24 | 2015-07-02Implant profiling with resist
#25 | 2014-09-11Hybrid active-field gap extended drain MOS transistor
#26 | 2012-06-28High voltage diode with reduced substrate injection
#27 | 2012-04-26Stacked ESD clamp with reduced variation in clamp voltage
#28 | 2012-04-26Low resistance LDMOS with reduced gate charge
#29 | 2012-04-26Hybrid active-field gap extended drain MOS transistor
#30 | 2011-07-28High voltage SCRMOS in BiCMOS process technologies
#31 | 2011-07-28High voltage SCRMOS in BiCMOS process technologies
#32 | 2011-03-31Isolation trench with rounded corners for BiCMOS process
#33 | 2010-02-11High voltage diode with reduced substrate injection
#34 | 2010-02-11Low cost high voltage power FET and fabrication
#35 | 2010-02-11Bi-directional DMOS with common drain
#36 | 2010-02-11Buried floating layer structure for improved breakdown
#37 | 2009-12-31Methods of forming drain extended transistors
#38 | 2009-04-16Isolation trench with rounded corners for BiCMOS process
#39 | 2008-12-04System and method for making a LDMOS device with electrostatic discharge protection
#40 | 2008-11-27LDMOS transistor double diffused region formation process
#41 | 2008-04-10Method of using electrical test structure for semiconductor trench depth monitor
#42 | 2007-10-25Drive circuit and drain extended transistor for use therein
#43 | 2006-08-31Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process
#44 | 2006-08-24System and method for making a LDMOS device with electrostatic discharge protection
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