Time alignment of polar transmitter

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Application Ser. No. 60/822,357, entitled TIME ALIGNMENT OF A POLAR TRANSMITTER, filed on Aug. 14, 2006, which is incorporated by reference herein for all purposes. This application is related to U.S. patent application Ser. No. 10/265,215, entitled DIRECT SYNTHESIS TRANSMITTER, the disclosure of which is incorporated herein by reference for all purposes.

FIELD OF THE INVENTION

The present invention relates generally to radio transmitters using polar modulation.

BACKGROUND OF THE INVENTION

Phase modulation schemes are very effective and are therefore widely used in communication systems. A simple example of a phase modulation scheme is quaternary phase shift keying (QPSK). This modulation scheme maps two-bit digital data to one of four phase offsets as shown in FIG. 1a. Ideally, the trajectory of the complex signal intersects these symbols at periodic points in time. In practice, pulse-shaping filters—needed to constrain the frequency spectrum of the signal—introduce some variations as illustrated by FIG. 1b.

FIG. 2 shows a typical QPSK (or I/Q) modulator used to generate the complex phase-modulated signal. This technique relies on orthogonal signal vectors to realize the phase offsets—an inherently linear technique, since it depends solely on the matching of these orthogonal signals.

The I/Q modulator provides a straightforward approach to generating phase-modulated signals. But, it's also possible to generate the phase-modulated signals using a polar transmitter such as the one shown in FIG. 3. This approach reduces circuitry, lowers power consumption, and potentially supports multiple modulation formats. It separately applies the phase and amplitude signals with precise alignment to realize the complex QPSK modulation. Unfortunately, several factors make this alignment very difficult. It would therefore be advantageous to be able to precisely align the phase and amplitude modulation signals.

SUMMARY OF THE INVENTION

In summary, the invention relates to a system and method for effecting precise time alignment of modulation signals applied within a polar transmitter.

A particular aspect of the invention is directed to a polar transmitter system including a direct synthesis modulator and a signal alignment module. The direct synthesis modulator is operative to generate an output signal based upon a reference signal. During this generation process the direct synthesis modulator is responsive to an amplitude modulation control signal and a frequency modulation control signal. A signal alignment module is configured to apply the amplitude modulation control signal and the frequency modulation control signal to the direct synthesis modulator in accordance with a defined timing relationship. The amplitude modulation control signal and the frequency modulation control signal are based upon an input amplitude modulation signal and an input phase or frequency modulation signal, respectively.

In another aspect the invention pertains to a signal alignment module for use with a polar transmitter. The alignment module includes a first latch arrangement which latches an input amplitude modulation signal and a second latch arrangement which latches an input phase or frequency modulation signal. A triggering network provides a first timing signal to the first latch arrangement and a second timing signal to the second latch arrangement. The triggering network also establishes a defined time offset between the first timing signal and the second timing signal.

A further aspect of the invention may be embodied in an alignment apparatus for use with a polar transmitter system. The alignment apparatus includes a signal alignment module configured to apply an amplitude modulation control signal and a frequency modulation control signal to the polar transmitter in accordance with a defined timing relationship. A time alignment network, operatively coupled between an output of the polar transmitter system and the signal alignment module, sets the defined timing relationship.

The present invention is also directed to an apparatus for adjusting signal time alignment within a polar transmitter system. The apparatus includes a signal alignment module operative to apply control signals to the polar transmitter system. The apparatus further includes a time alignment network for setting a timing relationship imposed upon the control signals by the signal alignment module. The time alignment network includes: a signal source unit coupled to the signal alignment module, a receiver coupled to an output of the polar transmitter system, and a control network coupled between an output of the receiver and the signal alignment module.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and the attendant advantages of the embodiments described herein will become more readily apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein:

FIG. 1a shows a constellation diagram that illustrates how QPSK maps two-bit digital data to one of four offsets;

FIG. 1b illustrates the trajectory of the complex signal for QPSK modulation;

FIG. 2 shows a diagram of a typical I/Q modulator;

FIG. 3 shows a simplified diagram of a polar transmitter;

FIG. 4 shows a PLL that is used to synthesize a radio frequency carrier signal;

FIG. 5 shows a mathematical model of the PLL shown in FIG. 3;

FIG. 6 shows an integration filter;

FIG. 7a shows one embodiment of a fractional-N PLL using a □□ modulator;

FIG. 7b illustrates the frequency response of the fractional-N PLL shown in FIG. 7a;

FIG. 8a illustrates one embodiment of a fractional-N PLL that supports direct frequency or phase modulation;

FIG. 8b illustrates the frequency response of the direct phase/frequency modulator shown in FIG. 7a;

FIG. 9 illustrates the envelope variation for filtered QPSK modulation;

FIG. 10a shows a simplified diagram of an amplitude modulation system using a variable gain amplifier;

FIG. 10b shows a simplified diagram of an amplitude modulation system using a switched power amplifier, controlled by a dc-dc regulator;

FIG. 10c shows a simplified diagram of an amplitude modulation system using feedback to linearize its response;

FIG. 11a illustrates the spectral regrowth in an EDGE polar transmitter due to 10 nSec timing error;

FIG. 11b illustrates the spectral regrowth in an WCDMA polar transmitter due to 2.5 nSec timing error;

FIG. 12a illustrates the performance sensitivity of the EDGE polar transmitter to timing errors;

FIG. 12b illustrates the performance sensitivity of the WCDMA polar transmitter to timing errors;

FIG. 13a shows a polar transmitter with timing alignment of the AM and FM signals using a delay-locked loop, in accordance with the present invention;

FIG. 13b shows a polar transmitter with timing alignment of the AM and FM signals using digital delay, in accordance with the present invention;

FIG. 14a shows a diagram of a system for adjusting the time alignment of polar transmitters, in accordance with the present invention;

FIG. 14b illustrates the symbol pattern used to enhance timing errors as part of the alignment system of FIG. 14a, in accordance with the present invention;

FIG. 14c illustrates the complex signal trajectory associated with the symbol pattern shown in FIG. 14b and part of the alignment system of FIG. 14a, in accordance with the present invention;

FIG. 14d shows a diagram of the digital signal source that generates the test signal associated with the alignment system of FIG. 14a, in accordance with the present invention;

FIG. 14e shows a diagram of an alternate system for adjusting the time alignment of polar transmitters, in accordance with the present invention;

FIG. 15a illustrates the frequency spectrum of a polar transmitter driven by the signal source described by FIGS. 14b-c and part of alignment system of FIG. 14a, in accordance with the present invention;

FIG. 15b illustrates the frequency spectrum of a polar transmitter driven by the signal source described by FIGS. 14b-c and part of alignment system of FIG. 14a, with a timing error of 2.5 nSec, in accordance with the present invention;

FIG. 16 illustrates the convergence of the alignment adjustment system of FIG. 14a; and

FIG. 17a-d illustrate other examples of symbol patterns, similar to FIG. 14b, that also enhance the timing error as part of the alignment system of FIG. 14a, in accordance with the present invention.

DETAILED DESCRIPTION

Referring again to the transmitter architecture of FIG. 3, a direct synthesis modulator or “polar transmitter” consists of a phase-locked loop (PLL) having a phase/frequency modulation capability followed by an amplitude modulation network.

FIG. 4 shows a block diagram of a phase-locked loop (PLL), which is used to synthesize a radio frequency carrier. It consists of a voltage-controlled oscillator (VCO), feedback counter (counter), phase/frequency detector (P/FD), charge pump (CP), and integration filter (LPF). This feedback system is further described by the mathematical model shown in FIG. 5.

The phase-locked loop uses feedback to minimize the phase difference between a very accurate reference signal and its output signal. As such, it produces an output signal at a frequency given by
f_VCO=Nf_REF
where f_vco is the frequency of the VCO output signal, N is the value of the feedback counter, and f_REF is the frequency of the reference signal.

The voltage-controlled oscillator produces an output signal at a frequency set by the control voltage v_ctrl according to
v_out(t)=A cos(ω_ot+K_vco∫v_ctrl(t)dt)
where ω_o is the free-running frequency of the oscillator and K_vco is its associated gain. The gain K_vco describes the relationship between the excess phase of the carrier Φ_out and the control voltage v_ctrl with

Φ out ⁡ ( s ) v ctrl ⁡ ( s ) = K vco s
where K_vco is in radians/V. The VCO drives the feedback counter, which simply divides the output phase Φ_out by N. When the phase-locked loop is stable, the phase detector and charge pump circuits generate an output signal i_CP that is proportional to the phase difference Δθ between the two signals applied to the phase detector. The output signal i_CP can therefore be expressed as

i CP ⁡ ( s ) = K pd ⁢ Δθ ⁡ ( s ) 2 ⁢ π
where K_pd is in A/radians and Δθ is in radians. A simple integration filter, comprising resistor R₁ and capacitors C₁-C₂ as shown in FIG. 6, transforms the output signal i_CP to the control voltage v_ctrl as follows

v ctrl ⁡ ( s ) = i out ⁡ ( s ) ⁢ Z ⁡ ( s ) = i out ⁡ ( s ) ⁢ ( sR 1 ⁢ C 1 + 1 s 2 ⁢ R 1 ⁢ C 1 ⁢ C 2 + s ⁡ ( C 1 + C 2 ) )
where a zero (at 1/R₁C₁) has been added to stabilize the second order system and the capacitor C₂ has been included to reduce any ripple on the control voltage. Combining the above relations yields the closed-loop response of the system to an input signal

T 1 ⁡ ( s ) = NK PD ⁢ K VCO ⁢ Z ⁡ ( s ) sN + K PD ⁢ K VCO ⁢ Z ⁡ ( s ) .

In a PLL, the feedback counter value N effectively sets the output frequency. In practice, its digital structure restricts N to integer numbers. As a result, the frequency resolution (or frequency step size) of an integer-N PLL is nominally set by f_REF. Fortunately, it's possible to dramatically decrease the effective frequency step by manipulating the value of N to yield a non-integer average value. This is the concept of the fractional-N PLL.

A fractional-N PLL that uses a ΔΣ modulator to develop non-integer values of N is shown in FIG. 7a. The ΔΣ modulator advantageously pushes spurious energy (created by the changing values of the feedback counter) to higher frequencies where it can be more effectively attenuated by the PLL's integration filter. It can be shown that the effective value of N is simply the average value described by

N = ∑ x = 1 P ⁢ ⁢ N ⁡ [ x ] P
where M[x] is the sequence of feedback counter values. This expands to
N[x]=N_int+n[x]
where N_int is the integer part and n[x] is the fractional part of N[x]. The ΔΣ modulator generates the sequence n[x] that satisfies

∑ x = 1 P ⁢ ⁢ n ⁡ [ x ] P = k M
where k is the input to the ΔΣ modulator with resolution M.

It's possible to use a fractional-N PLL as a very efficient phase/frequency modulator. That's because signals applied to the ΔΣ modulator's input control and actually modulate the frequency of the VCO according to
f_vco=f_c+Δf(t)=(N_int+n[x])f_REF
where Δf(t) is the frequency modulation equal to

Δ ⁢ ⁢ f ⁡ ( t ) = ( n ⁡ [ x ] - k M ) ⁢ f REF = FM ⁢ ⁢ f REF
and FM is the applied modulation signal. In practice, the modulation is shaped by the PLL response described by transfer function T₁(s). The PLL's response generally limits the bandwidth of the system so as to attenuate the ΔΣ modulator's quantization noise. This is illustrated in FIG. 7b.

To overcome this bandwidth limitation, a second high-frequency modulation path is added to the phase-locked loop and VCO as shown in FIG. 8a. The resulting two-point frequency modulation system now displays a second and complimentary transfer function given by

T 2 ⁡ ( s ) = sNK FM sN + K PD ⁢ K VCO ⁢ Z ⁡ ( s ) ⁢ v FM
where K_FM is the gain of the VCO port at which the v_FM modulating signal is applied. Ideally, the two expressions combine to yield a flat and uniform response as illustrated in FIG. 8b. This occurs when
FMf_REF=K_FMv_FM

The modulation applied to the fractional-N PLL and VCO adjusts the frequency of the output signal of the VCO, not its phase. To shift the phase of the output signal of the VCO, the phase modulation signal θ(t) must be differentiated with

f ⁡ ( t ) = ⅆ ⅆ t ⁡ [ f c ⁢ t + θ ⁡ ( t ) ] = f c + ⅆ θ ⁡ ( t ) ⅆ t
where f_c is the carrier frequency. Since the phase signal is formed digitally and then converted to analog form, a simple difference circuit is used to compute the derivative of the discrete phase data θ(x)
dθ(x+1)=θ(x+1)−dθ(x)
where x is the sample index and dθ(x) is the difference or derivative.

The fractional-N PLL and VCO generate a constant amplitude, phase/frequency-modulated signal centered at the carrier radio frequency. This allows the signal to be amplified using very efficient, compressed amplifiers. Unfortunately, the desired complex transmit signal typically shows envelop variations as illustrated by FIG. 9. As such, it becomes necessary to modulate the envelope of the phase/frequency-modulated signal to faithfully form the transmit signal.

There exist several methods to impress the amplitude modulation onto the VCO output signal. FIG. 10a shows one approach using a simple variable gain amplifier (VGA). It consists of a buffer amplifier, variable gain amplifier, filter, and power amplifier. The buffer isolates the variable gain amplifier from the VCO. This is important because the input impedance of the VGA changes with its gain. Without the isolation, the input impedance changes would pull the VCO's oscillation frequency and create distortion. Ideally, the VGA produces an output described by
s(t)=A(t)sin [2π(f_c+FM)t]
where A(t) is the amplitude modulation and is always positive. This approach—known as small-signal polar modulation or polar lite—eases design but requires a linear power amplifier. It also minimizes the time delay and associated alignment error between the phase/frequency modulator and the amplitude modulator. In most situations, the TXF filter is included to attenuate receive band noise.

FIG. 10b shows a second approach. It includes a buffer, driver amplifier, filter, and switched power amplifier supplied by a dc-dc regulator. In this approach, the amplitude modulation is applied through a dc-dc regulator. The dc-dc regulator produces an output level V₊ that tracks the AM signal and consequently restricts the power amplifier's signal swing. It follows that the power amplifier switches between its saturation voltage V_sat and 2V₊ with
s(t)□A(t){1+sign(sin [2π(f_c+FM)t])}+V_sat
A driver amplifier boosts the amplitude of the phase/frequency modulated signal to ensure the switched PA fully switches even at high AM and V₊ levels. In practice, the switching operation of the PA produces multiple harmonics that must be attenuated by the its output matching network. To minimize noise, the dc-dc regulator typically uses large capacitors which unfortunately slow the response to the amplitude modulation input. The TXF filter is used to attenuate any wideband noise that could fold in band due to the amplifier's switching response.

FIG. 10c shows a third method for amplitude modulation. It consists of a buffer, variable gain amplifier, power amplifier, and feedback network to control the transmitter's output. The feedback network linearizes the response to the amplitude modulation signal A(t). However, as with any feedback network, its behavior—and particularly its delay—depends on the loop parameters which unfortunately vary. This means the required offset to align the amplitude modulation to the phase/frequency modulation also varies.

Ideally, the amplitude modulation precisely aligns to the phase/frequency modulation, avoiding spectral regrowth and EVM degradation. Even small timing errors affect the frequency spectrum of the complex transmit signal. This is illustrated in FIG. 11a for an EDGE polar system with 10 nSec of timing error. The issue becomes more critical for WCDMA as shown in FIG. 11b. Here, the timing error is only 2 nSec.

Timing errors also distort the transmitted signal and thereby affect the ability of a receiver to properly detect the message data. This effect is measured by the error vector magnitude (EVM). The sensitivity of the modulation system to timing error varies with the symbol rate—making WCDMA systems (3.84 Mcps) much more sensitive than EDGE systems (270 ksps). FIG. 12a shows the sensitivity of EDGE polar transmitters to timing error. FIG. 12b shows the sensitivity of WCDMA polar transmitters to timing error.

Fortunately, the system shown in FIG. 13a can align the amplitude modulation to the phase/frequency modulation. Although the system of FIG. 13a is shown as receiving input amplitude modulation (AM) and frequency modulation (FM) signals, it may also receive an input phase-modulated signal in lieu of an FM signal. In this case a simple difference circuit (not shown) is used to compute the derivative of the input phase data. As shown, the system of FIG. 13(a) includes a signal alignment module which independently adjusts the timing of the AM and FM input digital data using two latches and a delay locked loop, thereby producing time-aligned AM and FM modulation control data. The delay locked loop generates an output signal with selectable delay.

FIG. 13b shows another method to generate time-aligned AM and FM modulation control data based upon the input AM and FM digital data. In this approach the signal alignment module operates digitally to adjust the delay of the input AM signal through a delay equalizer or programmable filter.

The delay is selected using the time alignment network shown in FIG. 14a. It generates a test signal that reveals polar modulation timing errors using a simple receiver. The receiver monitors the received signal and adjusts the timing alignment until the signal energy is nulled. The result is near perfect alignment. It is noted that in WCDMA-based embodiments, the transmit signal connects directly to the receiver in the time alignment network through a duplex filter (not shown). In GSM/EDGE-based embodiments, the transmit signal is routed to the receiver using either a switch or RF coupler (not shown).

The test signal is applied and the AM/FM timing is aligned when the transmitter is first activated. In practice, this is sufficient since any delay changes should be small. If needed, the calibration can be repeated in any empty transmission slot.

The alignment network exploits a special class of complex transmit signals that enhance timing errors. This special class of complex transmit signals simply isolates amplitude and phase changes. FIG. 14b shows an example. It's described by the sequences
I=[r₁,0,0,−r₂,−r₁,0,0,r₂] and Q=[0,r₂,r₁,0,0,−r₂,−r₁,0]
where r₁>r₂. These sequences generate a signal that changes amplitude moving from odd symbols to even symbols and changes phase moving from even symbols to odd symbols.

The digital signal source interpolates the special complex transmit signal to smooth the frequency and amplitude modulation signals. This results in the complex signal trajectory illustrated in FIG. 14c. The interpolation operation is part of the signal source detailed in FIG. 14d. This operation effectively up-samples the I/Q data and then filters these signals to limit their bandwidth. The resulting data streams are then converted to polar format, FM and AM. Ideally, this signal is unaffected by the low pass filters typically included in the polar transmitter to attenuate wideband noise and D/A converter image signals.

FIG. 14e shows an alternative approach to align the AM and FM signals. It is based on the digital delay concept of FIG. 13b.

The frequency spectrum produced by the polar transmitter operating at a carrier frequency of 825 MHz and with the complex pattern of FIG. 14b is shown in FIG. 15a. It generates several frequency tones separated by 1.5 MHz, equal one-half the symbol rate. FIG. 15b shows the same polar transmitter with 2.5 nSec of timing error. The frequency tone at 821.5 MHz grew more than 30 dB. Furthermore, this tone rises as the timing error increases.

The radio receiver, configured to track the 821.5 MHz tone, easily detects the level. It in turn drives the controller to increase/decrease the offset of the delay from the delay-locked loop by selecting different output signals. The parabolic shape of FIG. 16 guarantees convergence to the optimal timing for the AM and FM signals.

The signal source makes detection of the timing error easy. It relies on a newly-defined class of complex transmit signals that simply isolates amplitude and phase changes. Since this is a class of signals, multiple variations are possible, including, but not limited to, FIGS. 14a and 17a-d.

The alignment network properly adjusts the polar transmitter to minimize spectral regrowth and EVM degradation due to timing errors.

The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the specific details are not required in order to practice the invention. In other instances, well-known circuits and devices are shown in block diagram form in order to avoid unnecessary distraction from the underlying invention. Thus, the foregoing descriptions of specific embodiments of the present invention are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, obviously many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the following Claims and their equivalents define the scope of the invention.