Data storage in analog memory cells with protection against programming interruption

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Patent Application 61/086,164, filed Aug. 5, 2008, U.S. Provisional Patent Application 61/086,541, filed Aug. 6, 2008, and U.S. Provisional Patent Application 61/093,461, filed Sep. 2, 2008, whose disclosures are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates generally to memory devices, and particularly to methods and systems for protecting data stored in memory devices against programming interruption.

BACKGROUND OF THE INVENTION

Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. This analog value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into intervals, each interval corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.

Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible programming levels. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible programming levels.

Several techniques are known in the art for protecting data stored in analog memory cell devices against power interruptions and programming failures. For example, U.S. Patent Application Publication 2007/0143531, whose disclosure is incorporated herein by reference, describes a method for power loss recovery for bit alterable memory. A bit alterable memory device includes status bits for a colony of memory cells. The state of each status bit may be changed depending on the programming state of the non-volatile bit alterable memory. The status bits are examined to determine the write status of two separate colonies of memory cells in the event of a power loss. The information gathered from the status bits is used by a power loss recovery mechanism to determine whether the data written to a plurality of memory cell colonies is partially written.

As another example, U.S. Pat. No. 6,988,175, whose disclosure is incorporated herein by reference, describes a method for managing page-based data storage media such as Flash media. New data are written to the storage medium in a manner that precludes corruption of old data if the writing of the new data is interrupted. Specifically, risk zones are defined by identifying, for each page, the other pages whose data are put at risk of corruption if writing to the page is interrupted. A page, which otherwise would be the target of a write operation, is not written if any of the pages in its risk zone contain data that could be corrupted if the write operation is interrupted.

U.S. Pat. No. 7,420,847, whose disclosure is incorporated herein by reference, describes a non-volatile memory device that is able to recover data in the event of a program failure without having to maintain a copy of the data until the write is completed. In some embodiments, the data is recovered by logically combining the verify data for the (failed) write process maintained in data latches with the results of one or more read operations to reconstitute the data.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a method for data storage, including:

storing first data in analog memory cells using a first programming operation, which writes to the memory cells respective analog values representing respective bit values of the first data; and

storing in the analog memory cells second data in addition to the first data using a second programming operation, which modifies the respective analog values of the memory cells so as to represent bit value combinations of the first and second data,

wherein the first and second programming operations are defined such that, at all times during the second programming operation, the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell.

In some embodiments, the first and second programming operations are defined such that the analog values that are potentially reached during the second programming operation by the memory cells that store a first bit value of the first data are contained in a first range, and the analog values that are potentially reached during the second programming operation by the memory cells that store a second bit value of the first data, different from the first bit value, are contained in a second range that does not overlap the first range.

In an embodiment, following an interruption in the second programming operation, the first data is reconstructed by reading the analog values from the memory cells using a read threshold positioned between the first and second ranges.

In a disclosed embodiment, storing the first and second data includes evaluating a condition with respect to the analog memory cells and, based on the condition, selecting to store the first and second data using one of a first version of the programming operations, in which at all times during the second programming operation the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell, and a second version of the programming operations that is different from the first version. In an embodiment, evaluating the condition includes assessing whether the first and second data originate from different data items. In another embodiment, evaluating the condition includes performing at least one action selected from a group of actions consisting of:

assessing a size of a data item to be stored in the analog memory cells;

identifying a pattern indicating an end of the data item to be stored in the analog memory cells; and

assessing an elapsed time since a previous programming operation.

In still another embodiment, the condition is evaluated after the first data was stored using the second version and before storing the second data, and, upon selecting the first version, the analog values of at least some of the analog memory cells are adjusted to match the first version of the programming operations.

In an embodiment, the analog memory cells are included in a memory device, selection of the one of the first and second version is performed by circuitry that communicates with the memory device over an interface, and the selected version is reported to the memory device via the interface.

In some embodiments, the first programming operation represents a given bit value of the first data by analog values that are higher than the analog values representing the other bit value of the first data, and storing the second data includes applying the second programming operation to the memory cells holding the given bit value of the first data, and subsequently applying the second programming operation to the memory cells holding the other bit value of the first data.

There is additionally provided, in accordance with an embodiment of the present invention, a data storage apparatus, including:

a plurality of analog memory cells; and

circuitry, which is configured to store first data in a group of the analog memory cells using a first programming operation, which writes to the memory cells respective analog values representing respective bit values of the first data, and to store in the group of the analog memory cells second data in addition to the first data using a second programming operation, which modifies the respective analog values of the memory cells so as to represent bit value combinations of the first and second data, wherein the first and second programming operations are defined such that, at all times during the second programming operation, the analog value of each memory cell in the group remains unambiguously indicative of the respective bit value of the first data stored in that memory cell.

There is also provided, in accordance with an embodiment of the present invention, a data storage apparatus, including:

an interface, which is operative to communicate with a memory device including a plurality of analog memory cells; and

circuitry, which is configured to store first data in a group of the analog memory cells using a first programming operation, which writes to the memory cells respective analog values representing respective bit values of the first data, and to store in the group of the analog memory cells second data in addition to the first data using a second programming operation, which modifies the respective analog values of the memory cells so as to represent bit value combinations of the first and second data, wherein the first and second programming operations are defined such that, at all times during the second programming operation, the analog value of each memory cell in the group remains unambiguously indicative of the respective bit value of the first data stored in that memory cell.

The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention;

FIG. 2 is a diagram that schematically illustrates programming levels in a group of multi-level analog memory cells, in accordance with an embodiment of the present invention;

FIGS. 3 and 4 are flow charts that schematically illustrate methods for programming analog memory cells, in accordance with embodiments of the present invention; and

FIG. 5 is a flow chart that schematically illustrates a method for reading analog memory cells, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Overview

Analog memory cell devices store data by programming the memory cells to assume certain programming levels that represent the data. If the programming operation is disrupted, such as due to power failure, the stored data may be lost or corrupted. Multi-Level Cell (MLC) devices, which store multiple data bits in each memory cell, are particularly sensitive to programming interruption.

In many practical cases, different bits in a given multi-level cell may belong to different data items and may be stored at different times. For example, a given data file may be stored in the Least Significant Bits (LSB) of a certain group of multi-level memory cells, and another file may be stored in the Most Significant Bits (MSB) of these memory cells at a later time. In known memory devices, if the MSB programming operation is interrupted, the analog values (e.g., threshold voltages) of the cells are distorted and this distortion usually corrupts both the LSB and MSB. While corruption of the currently-written data (the MSB) may be permissible in some applications, corruption of the LSB (which often belongs to another data item and may have been written at a much earlier time) is highly undesirable.

Embodiments of the present invention that are described hereinbelow provide improved methods and systems for storing data in multi-level analog memory cells. These methods and systems reduce the effects of programming interruptions by confining possible corruption to the currently-written data, and ensuring that data written to other bits of the memory cells in previous programming operations is not lost.

In some embodiments, a group of multi-level memory cells, e.g., a word line, is programmed using at least two programming operations. The first programming operation programs first bits of the memory cells (e.g., the LSBs). The second programming operation programs second bits of the memory cells (e.g., the MSBs) in addition to the first bits, i.e., after the first bits are already programmed. In other words, the second programming operation shifts the analog values of the memory cells from one constellation of programming levels to another. In a typical application, programming is performed using an iterative Program and Verify (P&V) sequence.

In the resilient programming schemes described herein, the programming operations are designed so that at any time during the second programming operation, the analog value of each memory cell remains unambiguously indicative of the first bit value stored in that memory cell. As a result, if the second programming operation is interrupted for any reason, the data stored in the first programming operation will still be recoverable.

In an example embodiment, the programming levels of a four-level Flash device are positioned such that, during the entire P&V sequence that programs the MSB, the threshold voltage of each memory cell remains in a range that is uniquely associated with the LSB value stored in that cell. If the MSB programming sequence is interrupted at any point in time, the threshold voltage of each memory cell at the time of interruption will fall in the range that corresponds to the correct LSB value. The LSB values can be recovered by positioning one or more read thresholds between the ranges.

Several examples of interruption-resilient programming schemes, as well as methods for designing programming operations that achieve such resilience, are described herein. In some embodiments, a resilient programming scheme is applied selectively, i.e., only to selected groups of memory cells. The decision whether or not to apply a resilient programming scheme may depend, for example, on whether different bits in the cell group in question store data from the same data item or from different data items.

Unlike some known protection schemes that copy and back-up the first data before the second data is programmed, the methods and systems described herein achieve resilience by appropriate positioning of the programming levels. Since the disclosed techniques do not need to copy or back-up data, they enable increased programming speed and reduced programming complexity in comparison with known solutions.

System Description

FIG. 1 is a block diagram that schematically illustrates a memory system 20, in accordance with an embodiment of the present invention. System 20 can be used in various host systems and devices, such as in computing devices, cellular phones or other communication terminals, removable memory modules (“disk-on-key” devices), Solid State Disks (SSD), digital cameras, music and other media players and/or any other system or device in which data is stored and retrieved.

System 20 comprises a memory device 24, which stores data in a memory cell array 28. The memory array comprises multiple analog memory cells 32. In the context of the present patent application and in the claims, the term “analog memory cell” is used to describe any memory cell that holds a continuous, analog value of a physical parameter, such as an electrical voltage or charge. Array 32 may comprise analog memory cells of any kind, such as, for example, NAND, NOR and Charge Trap Flash (CTF) Flash cells, phase change RAM (PRAM, also referred to as Phase Change Memory—PCM), Nitride Read Only Memory (NROM), Ferroelectric RAM (FRAM), magnetic RAM (MRAM) and/or Dynamic RAM (DRAM) cells.

The charge levels stored in the cells and/or the analog voltages or currents written into and read out of the cells are referred to herein collectively as analog values or storage values. Although the embodiments described herein mainly address threshold voltages, the methods and systems described herein may be used with any other suitable kind of storage values.

System 20 stores data in the analog memory cells by programming the cells to assume respective memory states, which are also referred to as programming levels. The programming levels are selected from a finite set of possible levels, and each level corresponds to a certain nominal storage value. For example, a 2 bit/cell MLC can be programmed to assume one of four possible programming levels by writing one of four possible nominal storage values into the cell.

Memory device 24 comprises a reading/writing (R/W) unit 36, which converts data for storage in the memory device to analog storage values and writes them into memory cells 32. In alternative embodiments, the R/W unit does not perform the conversion, but is provided with voltage samples, i.e., with the storage values for storage in the cells. When reading data out of array 28, R/W unit 36 converts the storage values of memory cells 32 into digital samples having a resolution of one or more bits. Data is typically written to and read from the memory cells in groups that are referred to as pages. In some embodiments, the R/W unit can erase a group of cells 32 by applying one or more negative erasure pulses to the cells.

The storage and retrieval of data in and out of memory device 24 is performed by a Memory Signal Processor (MSP) 40. MSP 40 comprises an interface 44 for communicating with memory device 24, and a signal processing unit 48, which processes the data that is written into and read from device 24. In some embodiments, unit 48 encodes the data for storage using a suitable Error Correction Code (ECC) and decodes the ECC of data retrieved from the memory. In some embodiments, unit 48 produces the storage values for storing in the memory cells and provides these values to R/W unit 36. Alternatively, unit 48 provides the data for storage, and the conversion to storage values is carried out by the R/W unit internally to the memory device. Alternatively to using an MSP, the methods described herein can be carried out by any suitable type of memory controller that applies ECC to the data.

MSP 40 communicates with a host 52, for accepting data for storage in the memory device and for outputting data retrieved from the memory device. MSP 40, and in particular unit 48, may be implemented in hardware. Alternatively, MSP 40 may comprise a microprocessor that runs suitable software, or a combination of hardware and software elements.

The configuration of FIG. 1 is an exemplary system configuration, which is shown purely for the sake of conceptual clarity. Any other suitable memory system configuration can also be used. Elements that are not necessary for understanding the principles of the present invention, such as various interfaces, addressing circuits, timing and sequencing circuits and debugging circuits, have been omitted from the figure for clarity.

In the exemplary system configuration shown in FIG. 1, memory device 24 and MSP 40 are implemented as two separate Integrated Circuits (ICs). In alternative embodiments, however, the memory device and the MSP may be integrated on separate semiconductor dies in a single Multi-Chip Package (MCP) or System on Chip (SoC), and may be interconnected by an internal bus. Further alternatively, some or all of the MSP circuitry may reside on the same die on which the memory array is disposed. Further alternatively, some or all of the functionality of MSP 40 can be implemented in software and carried out by a processor or other element of the host system. In some embodiments, host 44 and MSP 40 may be fabricated on the same die, or on separate dies in the same device package.

Memory cells 32 of array 28 are typically arranged in a grid having multiple rows and columns. Each cell 32 typically comprises a floating gate Metal-Oxide Semiconductor (MOS) transistor. A certain amount of electrical charge (electrons or holes) can be stored in a particular cell by applying appropriate voltage levels to the transistor gate, source and drain. The value stored in the cell can be read by measuring the threshold voltage of the cell, which is defined as the minimal voltage that needs to be applied to the gate of the transistor in order to cause the transistor to conduct. The read threshold voltage is indicative of the charge stored in the cell.

In a typical configuration of array 28, the gates of the transistors in each row are connected by word lines, and the sources of the transistors in each column are connected by bit lines. The array is typically divided into multiple pages, i.e., groups of memory cells that are programmed and read simultaneously. Pages are sometimes sub-divided into sectors. In some embodiments, each page comprises an entire row of the array. In alternative embodiments, each row (word line) can be divided into two or more pages. For example, in some devices each row is divided into two pages, one comprising the odd-order cells and the other comprising the even-order cells. In a typical implementation, a two-bit-per-cell memory device may have four pages per row, a three-bit-per-cell memory device may have six pages per row, and a four-bit-per-cell memory device may have eight pages per row.

Erasing of cells is usually carried out in blocks that contain multiple pages. Typical memory devices may comprise several thousand erasure blocks. In a typical two-bit-per-cell MLC device, each erasure block is on the order of 32 word lines, each comprising several thousand cells. Each word line of such a device is often partitioned into four pages (odd/even order cells, least/most significant bit of the cells). Three-bit-per cell devices having 32 word lines per erasure block would have 192 pages per erasure block, and four-bit-per-cell devices would have 256 pages per block. Alternatively, other block sizes and configurations can also be used.

Some memory devices comprise two or more separate memory cell arrays, often referred to as planes. Since each plane has a certain “busy” period between successive write operations, data can be written alternately to the different planes in order to increase programming speed.

R/W unit 36 typically programs memory cells 32 using an iterative Program and Verify (P&V) process. In such a process, the R/W unit applies a sequence of programming pulses to a group of memory cells, e.g., to a certain word line in array 28. Following each programming iteration, the R/W unit compares the threshold voltages of the memory cells to one or more verification thresholds. Each verification threshold corresponds to a certain programming state of the cells, which represents a certain data value. A memory cell whose threshold voltage is higher than the applicable verification threshold is regarded as programmed successfully, i.e., as a cell that reached its intended programming level. In the next iteration, programming continues for only those cells that have not yet reached their intended threshold voltages, i.e., for the cells whose threshold voltages are smaller than the applicable verification thresholds.

Typically, the amplitude of the programming pulses increases from pulse to pulse. The average increase in the threshold voltage of the cells in response to a programming pulse is referred to herein as a program step size, or Increment Step Pulse Program (ISPP). As can be appreciated, after the P&V process is completed, the threshold voltages of the cells belonging to a certain programming level will be distributed over the interval [V, V+ISPP], wherein V denotes the verification threshold of the programming level. A small ISPP produces a relatively narrow threshold voltage distribution, at the expense of slower programming. A high ISPP produces wider distributions but faster programming. (Note that in practice, a small fraction of the cells may have threshold voltages that deviate slightly from the interval [V, V+ISPP]. In other words, the threshold voltage distribution of a given programming level may have residual “tails” slightly below V and/or slightly above V+ISPP.)

FIG. 2 is a diagram that schematically illustrates programming levels in a group of multi-level analog memory cells 32, in accordance with an embodiment of the present invention. The example of FIG. 2 refers to a group of four-level memory cells, e.g., the cells along a given word line, each storing two data bits. The two data bits in each memory cell are referred to as a Least Significant Bit (LSB) and a Most Significant Bit (MSB). This notation, however, is used purely as a way to refer to the different bits and does not imply any order of importance between them.

R/W unit 36 in device 24 stores data in these four-level memory cells using two types of programming operations. The first operation programs the LSBs of the cells. The second operation programs the MSBs of the cells after the LSBs have already been programmed. The programming operations modify the threshold voltages of the cells, so as to cause the threshold voltage of each cell to reach the level that represents the data to be stored therein.

A curve 56 at the top of FIG. 2 shows the distribution of threshold voltages of the memory cells before programming begins, i.e., when the cells are erased. Typically although not necessarily, erased cells are associated with negative threshold voltages.

The first programming operation programs the LSBs of the cells. The LSBs are programmed by applying programming pulses to the memory cells that are to store LSB=“0”. Memory cells that are to store LSB=“1” are not programmed. After LSB programming, a curve 60A shows the threshold voltage distribution in the cells that store LSB=“1”, and a curve 60B shows the threshold voltage distribution in the cells that store LSB=“0”.

The second programming operation programs the MSBs of the cells, after the LSBs have already been programmed. After MSB programming, each cell assumes one of four possible programming levels, which represent the four possible LSB/MSB combinations. The threshold voltage distributions of the four programming levels are shown by curves 64A . . . 64D at the bottom of FIG. 2. As can be seen in the figure, a cell that stores LSB=“1” and whose MSB=“1” (distribution 64A) is not subjected to programming pulses in the MSB programming operation. A cell that stores LSB=“1” and whose MSB=“0” is subjected to programming pulses that move its threshold voltage from distribution 60A to distribution 64B. A cell that stores LSB=“0” and whose MSB=“0” is subjected to programming pulses that move its threshold voltage from distribution 60B to distribution 64C. A cell that stores LSB=“0” and whose MSB=“1” is subjected to programming pulses that move its threshold voltage from distribution 60B to distribution 64D.

The threshold voltage distribution of a given programming level depends on the verification threshold of that programming level, and on the programming step size (ISPP). For example, distribution 64B lies in the interval [V10, V10+ISPP]. Similarly, distribution 64C lies in the interval [V00, V00+ISPP].

Programming Level Design for Resilience Against Programming Interruptions

In some cases, the second programming operation (i.e., MSB programming) may be interrupted before it is completed. Programming interruption may be caused, for example, by a disruption of the electrical power supply to device 24, by hardware failure or for any other reason. Power loss to device 24 may occur, for example, when a user of a Disk-on-Key (DoK) device unplugs the device during active storage, or when a removable Solid State Disk (SSD) unit is removed during operation.

In such scenarios, it is highly desirable to prevent programming interruptions from corrupting the data stored in the LSBs of the cells, and to confine any possible corruption or data loss to the currently-programmed MSB data. This requirement is particularly important when the LSB data and MSB data belong to different data items, e.g., to different files.

In some embodiments of the present invention, the programming levels used in device 24 are positioned so as to prevent LSB corruption in the event of interruption of MSB programming. Positioning of the programming levels may involve setting of verification thresholds and/or ISPP values that are used in the LSB and MSB programming operations. In order to prevent MSB programming interruption from corrupting the LSB data, the programming levels in device 24 are designed to meet the following guideline: During the entire MSB programming sequence, the threshold voltage of each memory cell remains in an interval that is uniquely indicative of LSB bit value stored in that cell. In other words, if the MSB programming sequence is interrupted at any point in time, the threshold voltage of each memory cell at the time of interruption will be unambiguously indicative of the LSB bit value stored in that cell.

The above-mentioned condition will now be demonstrated with reference to the programming scheme of FIG. 2. In this example, the MSB programming interruption occurs when some of the memory cells may be in transition from distribution 60A to distribution 64B, some cells may be in transition from distribution 60B to distribution 64C, and other cells may be in transition from distribution 60B to distribution 64D. The exact threshold voltage of a given memory cell at the time of MSB programming interruption may be unknown, but is expected to be larger than its smallest possible initial value (the lower edge of the LSB distribution from which MSB programming started) and smaller than its largest possible final value (the upper edge of the intended MSB distribution).

Consider, for example, a cell that was initially programmed with LSB=“0” and is in the process of programming with MSB=“0”, i.e., a cell that is transitioning from distribution 60B to distribution 64C. If the MSB programming of this cell is interrupted before completion, the threshold voltage of the cell is likely to lie somewhere between V0 (the lower edge of distribution 60B) and V00+ISPP (the higher edge of distribution 64C).

Note that in the scheme of FIG. 2, the threshold voltage of any memory cell whose LSB=“0” remains in the interval V_TH>V0 during the entire MSB programming sequence, regardless of the intended MSB value. The threshold voltage of any memory cell whose LSB=“1”, on the other hand, remains in the interval V_TH<V10+ISPP during the entire MSB programming sequence, regardless of the intended MSB value. Since V10+ISPP<V0, the two intervals do not overlap.

In other words, if the threshold voltage of a given memory cell meets V_TH>V0 following MSP programming interruption, then the cell can be safely regarded as storing LSB=“0”. If the threshold voltage meets V_TH<V10+ISPP following the interruption, then the cell can be regarded as storing LSB=“1”. Thus, the LSB data values can be recovered from the memory cells even though their threshold voltages are distorted by the MSP programming interruption. As noted above, the position and width of the threshold voltage distributions of the different LSB and MSB programming levels are determined by the chosen values of the verification thresholds and ISPP. In some embodiments, R/W unit 36 sets these parameters, or any suitable subset of the parameters, to meet with the above-mentioned condition.

In some embodiments, following MSP programming interruption, R/W unit 36 retrieves the LSB data values from the memory cells by positioning a read threshold 72A in a region 68 (given by V10+ISPP<V_TH<V0), which differentiates between the two above-mentioned intervals. Unit 36 compares the threshold voltages of the memory cells to read threshold 72A. Cells whose threshold voltages are lower than read threshold 72A are regarded as storing LSB=“1”, and cells whose threshold voltages are higher than read threshold 72A are regarded as storing LSB=“0”. Thus, using the disclosed technique, the LSB data can be retrieved with high reliability even though the subsequent MSB programming operation was disrupted. In some embodiments, read threshold 72A is different from a normal read threshold 72B that would be used for LSB readout under normal conditions (i.e., with no interruption).

The design scheme described above can be generalized to other kinds of MLC, such as eight-level or sixteen-level cells. Consider, for example, a group of eight-level, 3 bits/cell MLC. The three bits stored in each cell are denoted LSB, Center Significant Bit (CSB) and MSB. In this example, mapping of bits to programming levels at the different programming stages is performed according to the following table (in increasing order of threshold voltage):

	Programming
	stage	Programming level order
	After LSB	1, 0
	programming
	After LSB + CSB	11, 10, 00, 01
	programming
	After	111, 110, 100, 101, 001, 000, 010, 011
	LSB + CSB + MSB
	programming

The ISPP values for programming the LSB, CSB and MSB are denoted ISPP1, ISPP2 and ISPP3, respectively. The verification threshold used for programming a given programming level x is denoted Vx (e.g., the verification threshold of level L10 is denoted V10).

R/W unit 36 may set suitable verification thresholds and ISPP values, which ensure that the data stored in the LSBs of the cells is still recoverable in the event of CSB programming interruption, and that CSB data is still recoverable in the event of MSB programming interruption. For example, setting V10+ISPP2<V0 ensures that the LSB data is not corrupted by CSB programming interruption. Setting V110+ISPP3<V10, V101+ISPP3<V00 and V000+ISPP3<V01 ensures that CSB data is not corrupted by MSB programming interruption. Similar conditions can be defined for sixteen-level, four bits/cell MLC, and for any other suitable type of MLC.

In an alternative embodiment, the above-mentioned constraints can be relaxed by splitting the second programming operation into stages that are carried out in succession. For example, in the four-level scheme of FIG. 2, the second programming operation can be split into the two following stages (the first programming operation is unchanged):

• • Program the cells in level 60B to level 64C or level 64D, depending on their MSB values.
  • Only after completing the previous step, program the cells in level 60A to level 64A or level 64B, depending on their MSB values.

When this order of operation is maintained, it is possible to reconstruct the LSB value of a given cell upon programming interruption at any given time, even if V10+ISPP>V00. This principle can be generalized in a straightforward manner to any other suitable MLC configuration, e.g., eight-level or sixteen-level cells.

In other words, when the first programming operation represents one bit value (e.g., LSB=“0”) using threshold voltages that are higher than the threshold voltages used for representing the other bit value (e.g., LSB=“1”), the second programming operation can be split into successive stages:

• • Program the memory cells that were programmed by the first programming operation to the high threshold voltages.
  • Only after completing the previous step, program the memory cells that were programmed by the first programming operation to the low threshold voltages.

In some embodiments, the above-mentioned programming order is implemented internally to the memory device and is transparent to the memory controller or MSP. Alternatively, the MSP may program a page while causing the memory device to carry out this scheme, e.g., by sending appropriate subset masks of the page. This sort of programming, however, increases the number of write operations and may reduce programming speed.

The embodiments described herein are example embodiments, which were chosen purely for the sake of conceptual clarity. Any other suitable MLC programming scheme in which, during the entire duration of a given programming operation, the cell analog values remain unambiguously indicative of the previously-stored data, can also be used.

Selective Application of Resilient Programming Scheme

In some cases, applying the interruption-resilient programming schemes described above reduces the utilization of the available threshold voltage range of the memory cells, and may therefore degrade other performance aspects of the memory device (e.g., storage density, storage reliability or programming speed). In some embodiments, memory device 24 applies the resilient programming schemes only in selected groups of memory cells (e.g. selected word lines) in which data protection is of particular value or need. For example, R/W unit 36 may hold two alternative sets of verification thresholds and/or ISPP values. One set, which is referred to as a resilient set, is applied when protection against programming interruption is desired. The other set, which is referred to as a normal set, is applied otherwise, so as not to compromise performance unless necessary.

Memory device 24 or MSP 40 may apply any suitable criteria for deciding whether to program a given group of memory cells using the resilient or the normal programming scheme. The description that follows assumes that selection of the appropriate programming scheme is performed by the MSP. In these embodiments, the MSP and the memory device support a suitable command interface, using which the MSP instructs the memory device to apply the selected programming scheme. In alternative embodiments, however, the decision may be taken internally to the memory device, e.g., by unit 36.

Typically, the decision depends on whether the data stored in different MLC bits belongs to the same data item (e.g., a file) or to different data items. When different MLC bits store data belonging to the same data item, protecting some bits against programming interruption of other bits may be of little value. When different MLC bits store data from different data items, on the other hand, protection may be important.

Programming scheme selection may depend, for example, on the size of the data item to be programmed. This sort of criterion assumes that a large data item is likely to occupy multiple MLC bits (e.g., an entire word line or more). When the data item is relatively small, on the other hand, there is high likelihood that different bits in the word line will store data from a different data item. The size of the data item can sometimes be extracted from the write command sent to the memory device. For example, the Open NAND Flash Interface (ONFI) specifications define Block Abstracted (BA) programming commands, which specify the number of sectors to be programmed.

As another example, the MSP may identify data patterns that indicate the end of a data item (e.g., End-of-File indication or File Close command). As yet another example, the MSP may estimate or measure the time period that elapsed since the previous programming operation to the word line in question. A simpler scheme may estimate or measure the time that elapsed since the last programming operation to the entire block or to the entire memory device. A long elapsed time is likely to indicate that the next programming operation is associated with a different data item.

Further alternatively, the MSP may evaluate any other suitable condition to decide whether to apply the interruption-resilient programming scheme or a normal programming scheme to a given group of cells. Note that these decision criteria can be used for selectively applying any suitable protection method, and not necessarily the methods described herein.

FIG. 3 is a flow chart that schematically illustrates a method for programming analog memory cells 32, in accordance with an embodiment of the present invention. The method begins with MSP 40 accepting data for storage from host 52, at a data input step 80. The MSP checks whether protection against programming interruption is desired for this data, at a protection checking step 84. For example, the MSP may assess whether the word line in which this data is to be stored holds data from a single data item or from multiple data items, e.g., using the criteria described above.

If resilience against programming interruption is not necessary (e.g., if the MSP determines that the word line is likely to hold data from only a single data item), the MSP selects the normal programming scheme, at a normal selection step 88. Otherwise (e.g., if the word line is likely to hold data from multiple data items), the MSP selects a resilient programming scheme, at a resilient selection step 92. Unit 36 then applies the verification thresholds and/or ISPP values of the selected programming scheme, and programs the memory cells using the applied scheme, at a programming step 96.

The method of FIG. 3 assumes that the programming scheme selection is performed before beginning to program the word line in question. In some cases, however, the need to use a resilient programming scheme arises when the word line is already partially programmed, e.g., after LSB programming. This situation is typical, for example, when the decision is taken based on the elapsed time since the previous programming operation. In such cases, the MSP may switch to the resilient programming scheme at a later stage.

FIG. 4 is a flow chart that schematically illustrates a method for programming analog memory cells 32, in accordance with an embodiment of the present invention. The method begins with MSP 40 and memory device 24 programming the memory cells of a given word line using the normal programming scheme, at a normal writing step 100. At some stage, when the word line is partially programmed, the MSP checks whether it is desired to revert to the resilient programming scheme, at a resilience checking step 104. If no trigger to switch to the resilient scheme arises, the method loops back to step 100 above and programming continues using the normal scheme.

If, on the other hand, the MSP determines that subsequent programming should be performed using the resilient scheme, the MSP re-programs the memory cells to reach the programming levels of the resilient scheme, at a re-programming step 108. The re-programming operation typically adjusts the threshold voltages of the cells using slightly higher verification thresholds, so as to satisfy the above-described conditions that ensure resilience against programming interruption. From this stage, programming continues using the resilient programming scheme.

FIG. 5 is a flow chart that schematically illustrates a method for reading analog memory cells 32, in accordance with an embodiment of the present invention. The method of FIG. 5 can be used for reading data from multi-level cells, which have been programmed using the programming methods of FIGS. 3 and 4 above. The method begins with MSP 40 accepting a request from host 52 to retrieve certain data, at a read request step 110.

The MSP checks whether the data in question was stored using the normal programming scheme or using the resilient programming scheme, at a scheme checking step 114.

If the normal programming scheme was used, MSP 40 sets one or more read thresholds, which are suitable for reading cells that were programmed using the normal programming scheme, at a normal read setting step 118. Otherwise, i.e., if the resilient programming scheme was used, the MSP sets a different set of one or more read thresholds, which are suitable for reading cells that were programmed using the resilient programming scheme, at a resilient read setting step 122. R/W unit 36 reads the memory cells in question using the selected read thresholds, at a reading step 126. The reconstructed data is provided to the MSP, which sends the data to the host in response to the read request.

It will be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.