Inductor over-current protection using a volt-second value representing an input voltage to a switching power converter

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. §119(e) and 37 C.F.R. §1.78 of U.S. Provisional Application No. 61/251,784, filed Oct. 15, 2009, and entitled “Volt-Second Protection”,” which is incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to the field of signal processing, and, more specifically, to a system and method that includes inductor over-current protection in a switching power converter based on one or more non-inductor-current signals.

2. Description of the Related Art

Switching power converters convert supplied power into a form and magnitude that is useful for numerous electronic products including cellular telephones, computing devices, personal digital assistants, televisions, other switching power converters, and lamps, such as light emitting diode and gas discharge type lamps. For example, alternating current (AC)-to-direct current (DC) switching power converters are often configured to convert AC voltages from an AC voltage source into DC voltages. DC-to-DC switching power converters are often configured to convert DC voltages of one level from a DC voltage source into DC voltages of another level. Switching power converters are available in many types, such as boost-type, buck-type, boost-buck type, and Cúk type converters. The switching power converters are controlled by a controller that controls one or more power regulation switches. Switching of the power regulation switch controls the link voltage of the switching power converter and, in some embodiments, also controls power factor correction.

FIG. 1 represents a power control system 100, which includes a switching power converter 102 and a controller 110. Voltage source 104 supplies an alternating current (AC) input voltage V_IN to a full, diode bridge rectifier 106. The rectifier 106 can be separate from the switching power converter 102, as shown, or part of the switching power converter 102. The voltage source 104 is, for example, a public utility, and the AC input voltage V_IN is, for example, a 60 Hz/110 V line voltage in the United States of America or a 50 Hz/220 V line voltage in Europe. The rectifier 106 rectifies the input voltage V_IN and supplies a rectified, time-varying, line input voltage V_X to the switching power converter.

The switching power converter includes a power regulation switch 108, and the power control system 100 also includes a controller 110 to control power regulation switch 108. Switch 108 is an n-channel, metal oxide semiconductor field effect transistor (FET). In other embodiments, switch 108 is a bipolar junction transistor or an insulated gate bipolar junction transistor. Controller 110 generates a gate drive control signal CS₀ to control the switching period and “ON” (conduction) time of switch 108. Controlling the switching period and “ON” time of switch 108 provides power factor correction and regulates the link voltage V_LINK. Switch 108 regulates the transfer of energy from the line input voltage V_X through inductor 112 to link capacitor 114. The inductor current i_L ramps ‘up’ when switch 108 is “ON”, and diode 116 prevents link capacitor 114 from discharging through switch 108. When switch 108 is OFF, diode 116 is forward biased, and the inductor current i_L ramps down as the current i_L recharges link capacitor 114. The time period during which the inductor current i_L ramps down is referred to as an “inductor flyback period”. The switching power converter 102 also includes a low pass, electromagnetic interference (EMI) filter 118 to filter any high frequency signals from the line input voltage V_X. The EMI filter 118 consists of inductor 120 and capacitor 122.

Link capacitor 114 supplies stored energy to load 117. Load 117 can be any type of load such as another switching power converter, light source, or any other electronic device. The capacitance of link capacitor 114 is sufficiently large so as to maintain a substantially constant output, link voltage V_LINK, as established by controller 110. The link voltage V_LINK remains substantially constant during constant load conditions. However, as load conditions change, the link voltage V_LINK changes. The controller 110 responds to the changes in link voltage V_LINK and adjusts the control signal CS₀ to restore a substantially constant link voltage V_LINK as quickly as possible.

Controller 110 maintains control of the inductor current i_L to ensure safe operation of switching power converter 102. Numerous fault conditions can occur that can cause the inductor current i_L to exceed normal operating limitations. For example, ringing in the EMI filter 118 can cause the inductor current i_L to exceed normal operating conditions. “Ringing” refers to oscillations of a signal around a nominal value of the signal. Ringing can be associated with sharp (i.e. high frequency component) transitions. To maintain control of the inductor current i_L, switching power converter 102 includes an inductor current sense resistor 124 connected in series with switch 108 to sense the inductor current i_L. The inductor current i_L causes an inductor current signal in the form of inductor current sense voltage V_iL—sense to develop across inductor sense resistor 124. The inductor current sense voltage V_iL—sense is directly proportional to the inductor current i_L when switch 108 is ON. Controller 110 monitors the inductor current sense voltage V_iL—sense to determine if inductor current i_L exceeds typical operating limitations and responds to an atypically large inductor current i_L by deasserting the control signal CS₀. Deasserting control signal CS₀ causes switch 108 to turn OFF, thereby attempting to prevent any further increase of the inductor current i_L.

Controller 110 controls switch 108 and, thus, controls power factor correction and regulates output power of the switching power converter 102. The goal of power factor correction technology is to make the switching power converter 102 appear resistive to the voltage source 104. Thus, controller 110 attempts to control the inductor current i_L so that the average inductor current i_L is linearly and directly related to the line input voltage V_X. Prodić, Compensator Design and Stability Assessment for Fast Voltage Loops of Power Factor Correction Rectifiers, IEEE Transactions on Power Electronics, Vol. 22, No. 5, September 2007, pp. 1719-1729 (referred to herein as “Prodić”), describes an example of controller 110. The controller 110 supplies a pulse width modulated (PWM) control signal CS₀ to control the conductivity of switch 108. The values of the pulse width and duty cycle of control signal CS₀ generally depend on feedback signals, namely, the line input voltage V_X, the link voltage V_LINK, and inductor current sense voltage V_iL—sense.

FIG. 2 depicts inductor current i_L and control signal CS₀ timing diagrams 200 during a period TT of switch control signal CS₀. Referring to FIGS. 1 and 2, for the time period t₁, controller 110 generates a pulse 202 of control signal CS₀ that causes switch 108 to conduct. When switch 108 conducts, the inductor current i_L ramps up. The time period t₁ is the pulse width (PW) of control signal CS₀ for period TT of control signal CS₀. When the pulse of control signal CS₀ ends at the end of time period t₁, the inductor current i_L begins to ramp down. The inductor current i_L ramps down to 0 at the end of time period t₂. Time period t₂ is an inductor flyback period. The time period t₃ represents the elapsed time between (i) the inductor flyback period for period TT and (ii) the next pulse of control signal CS₀. To operate switching power converter 102 in discontinuous current mode (DCM), controller 110 ensures that the time period t₃ is non-zero. In other words, to operate in DCM, the inductor current i_L must ramp down to 0 prior to the next pulse 204 of control signal CS₀.

To monitor the inductor current i_L when energy is being transferred to the inductor 112 during time t₂ (FIG. 2), controller 110 monitors inductor current sense voltage inductor current sense voltage V_iL—sense. The inductor current sense voltage V_iL—sense provides a direct one-to-one tracking of the inductor current i_L when energy is being transferred to the inductor 112. To ensure that switching power converter 102 operates in DCM, switching power converter 102 includes a secondary coil 126 that develops a voltage signal V_L corresponding to the inductor current i_L. Comparator 128 determines if voltage signal V_L is greater than 0V. The comparator 128 generates an output signal FLYBACK. When signal FLYBACK is a logical 0, switching power converter 102 is in an inductor flyback period. When signal FLYBACK is a logical 1, switching power converter 102 is not in an inductor flyback period. A logical “1” is, for example, a 3.3V. Thus, in one embodiment, when signal FLYBACK is a logical 1, a 3.3V signal is applied to terminal 130 of controller 110. Controller 110 receives the signal FLYBACK through terminal 130 and uses the signal FLYBACK to ensure that control signal CS₀ does not begin a new pulse 204 until the inductor flyback period is over. Thus, controller 110 is able to maintain switching power converter 102 in DCM.

Sensing the inductor current i_L across inductor current sense resistor 124 results in power losses equal to i_L²R, and “R” is the resistance value of inductor current sense resistor 124. Generally the value of “R” is chosen so that the losses associated with sensing the inductor current across inductor current sense resistor 124 are at least approximately 0.5-1% loss in total efficiency. However, when operating at above 90% efficiency, a 1% energy loss represents at least 10% of the losses. Additionally, controller 110 includes two extra terminals 130 and 132 to respectively sense inductor current sense voltage V_iL—sense and signal FLYBACK. Extra terminals for an integrated circuit embodiment of controller 110 add extra cost to controller 110.

SUMMARY OF THE INVENTION

In one embodiment of the present invention, an apparatus includes a controller. The controller is configured to detect an over-current condition of an inductor current in a switching power converter using at least one non-inductor-current signal.

In another embodiment of the present invention, an apparatus includes a controller. The controller is configured to detect an over-current condition of an inductor current in a switching power converter without using a signal generated using a resistor in series with a power regulation switch of the switching power converter.

In one embodiment of the present invention, a method includes detecting an over-current condition of an inductor current in a switching power converter using a non-inductor-current signal.

In another embodiment of the present invention, a power supply includes a switching power converter. The switching power converter includes a reference terminal, an input terminal to receive an input voltage, an inductor coupled to the input terminal, a power regulation switch coupled between the inductor and the reference terminal, a capacitor coupled to the switch, the inductor, and the reference terminal, and an output terminal coupled to the capacitor to provide a link voltage. The power supply further includes a controller. The controller is configured to detect an over-current condition of an inductor current in the switching power converter using a non-inductor-current signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the several figures designates a like or similar element.

FIG. 1 (labeled prior art) depicts a power control system.

FIG. 2 (labeled prior art) depicts switching power converter control signal and inductor current timing diagrams.

FIG. 3 depicts a power control system with inductor over-current and discontinuous current mode (DCM) protection with non-resistive based inductor current feedback.

FIG. 4 depicts an embodiment of a controller for the power control system of FIG. 3.

FIG. 5 depicts timing diagrams of a switch control signal of the controller of FIG. 4 and a volt-second over-current detection and protection related signals.

FIG. 6 depicts an embodiment of a switch control signal generator of the controller of FIG. 4.

FIG. 7 depicts an embodiment of an inductor over-current and DCM protection module.

FIG. 8 depicts an embodiment of an inductor over-current and DCM protection algorithm for the controller of FIG. 4.

FIGS. 9A and 9B depict another embodiment of an inductor over-current and DCM protection module.

DETAILED DESCRIPTION

A power control system includes a switching power converter and a controller. The controller is configured to detect an over-current condition of an inductor current in the switching power converter using at least one non-inductor-current signal. An inductor current signal is a signal that represents an inductor current and varies directly with the inductor current. For example, inductor current sense voltage V_iL—sense (FIG. 1) is an inductor current signal because inductor current sense voltage V_iL—sense represents the inductor current and varies directly as the inductor current i_L varies. A “non-inductor-current signal” is a signal that does not represent and does not vary directly with the inductor current. In at least one embodiment, the switching power converter does not have a resistor or resistor network to sense the inductor current. In at least one embodiment, the controller is configured to detect an over-current condition of an inductor current in a switching power converter without using a signal generated using a resistor in series with a power regulation switch of the switching power converter. In at least one embodiment, the controller indirectly determines a state of the inductor current using at least one non-inductor-current signal.

In at least one embodiment, an inductor over-current condition represents a condition when the inductor current exceeds a predetermined threshold value. For example, in at least one embodiment, an inductor over-current condition can arise when energy is being transferred to an inductor of the switching power converter via an inductor current. Electromagnetic interference (EMI) filter interactions, such as ringing in the EMI filter, and other conditions can cause the inductor current to exceed a safe operating level. Sudden rises in the inductor current can also cause an inductor over-current condition. Sudden rises in the inductor current can be difficult to detect. Consequently, the controller can miscalculate timing of a power regulation switch control signal and inadvertently cause the switching power converter to enter into continuous conduction mode (CCM). Entering CCM can result in unintended, potentially damaging output voltages and input currents.

In at least one embodiment, by monitoring at least one non-inductor-current signal, the controller can protect the switching power converter from damaging conditions such as an excessive inductor current and CCM operation by a DCM power control system. In at least one embodiment, the controller monitors two non-inductor-current signals: (i) an input signal representing an input voltage to the switching power converter and (ii) a link voltage signal representing a link (i.e. output) voltage of the switching power converter. In at least one embodiment, when energy is transferred to the inductor from an input voltage source, an accumulation of samples of the input voltage signal is directly proportional to the inductor current. The accumulation of the input voltage signal can be measured in volt-second terms and compared to a predetermined threshold volt-second value to determine if an inductor over-current condition exists. In at least one embodiment, if the inductor over-current condition exists, the controller takes remedial action, such as decreasing the amount of current flowing into the inductor. In at least one embodiment, the controller decreases the amount of current flowing into the inductor by turning the power regulation switch “OFF”, i.e. causing the power regulation switch to stop conducting.

In another embodiment, the final value of the input signal accumulation represents an initial accumulator value during an inductor flyback time. During the inductor flyback time, the current accumulator value A(n)_VS—OVR is determined by subtracting a difference between (i) the current link voltage V_LINK′(n) and (ii) the current input voltage signal V_X′(n) from the previous accumulator value A(n−1)_VS—OVR, i.e. A(n)_VS—OVR=A(n−1)_VS—OVR [V_LINK′(n)−V_X′(n)]. When the current accumulator value A(n)_VS—OVR is less than or equal to zero, the inductor flyback period is over, i.e. the inductor current is zero. The controller prevents the power regulation switch from conducting until the current accumulator value A(n)_VS—OVR is zero, and, thus, prevents the switching power converter from operating in CCM.

FIG. 3 depicts a power control system 300 that includes a switching power converter 302 and a controller 304. The switching power converter 302 is configured as a boost-type switching power converter but can be any other type of switching power converter including a buck converter, buck-boost converter, and a Cúk converter. In at least one embodiment, the switching power converter 302 functions in the same manner as switching power converter 102 except that switching power converter 302 does not include an inductor current sense resistor or any other feature to provide an inductor current signal to controller 304. Thus, in at least one embodiment, controller 304 is configured to detect an over-current condition of inductor current i_L in switching power converter 302 without using a signal generated using a resistor (such as inductor sense resistor 124 of FIG. 1) in series with power regulation switch 310. The particular mode in which controller 304 operates switching power converter 302 is a matter of design choice. For example, in at least one embodiment, controller 304 operates switching power converter 302 in discontinuous conduction mode (DCM). In other embodiments, controller 304 operates switching power converter 302 in continuous conduction mode (CCM) or critical conduction mode (CRM). The rectifier 106 can be separate from the switching power converter 302, as shown, or part of the switching power converter 302.

The controller 304 includes an inductor over-current module 306. Using at least one non-inductor-current signal, the inductor over-current module 306 determines whether an inductor over-current condition exists in switching power converter 302. In the embodiment of power control system 300, input voltage signal V_X′ represents the input voltage Vx, and link voltage signal V_LINK′ represents the link voltage V_LINK. In at least one embodiment, input voltage signal Vx′ and link voltage signal V_LINK are scaled versions of respective input voltage Vx and link voltage V_LINK. In at least one embodiment, the input voltage signal Vx′ and link voltage signal V_LINK′ are two non-inductor-current signals used by the inductor over-current module 306 to detect an inductor over-current condition. The particular scaling is a matter of design choice. By using non-inductor-current signals to detect an inductor over-current condition, in at least one embodiment, switching power converter 302 does not include an inductor current sense resistor such as inductor current sense resistor 120.

In at least one embodiment, inductor overcurrent module 306 utilizes the input signal V_X′ to determine an over-current condition exists corresponding to the inductor current i_L reaching a level that could damage switching power converter 302 and/or load 117. In at least one embodiment, inductor overcurrent module 306 utilizes both the input voltage signal V_X′ and the link voltage signal V_LINK′ to determine an over-current condition corresponding to the inductor current i_L being non-zero prior to when controller 304 would normally generate a next pulse of duty cycle modulated, switch control signal CS₁. If the controller 302 generates a pulse of switch control signal CS₁ prior to the inductor current i_L reaching zero at the end of the inductor flyback time, the switching power converter will enter CCM. Entering CCM when the controller 302 normally controls the switching power converter 302 in DCM can cause the controller 302 to make erroneous calculations when generating the switch control signal CS₁. The resulting switch control signal CS₁ could alter a desired link voltage V_LINK, cause instability in controller 304, cause abnormally high inductor current i_L values, and, thus, potentially damage to the switching power converter 302 and/or load 117.

The inductor over-current module 306 generates an over-current condition signal VS_OVR and provides the over-current condition signal VS_OVR to switch control signal generator 308. In at least one embodiment, in response to detecting an inductor over-current condition, inductor over-current module 306 generates the over-current condition signal VS_OVR to indicate the over-current condition. As subsequently discussed in more detail, the switch control signal generator 308 responds to the over-current condition signal VS_OVR by generating control signal CS₁ to resolve the inductor over-current condition.

The particular type(s) of inductor over-current condition(s) detectable by inductor over-current module 306 is(are) a matter of design choice. In at least one embodiment, inductor over-current module 306 detects an abnormally high inductor current i_L and a non-zero inductor current i_L that could cause the switching power converter 302 to operate in CCM.

Switch control generator 308 generates switch control signal CS₁ to control conductivity of power regulation switch 310. The type of power regulation switch 310 is a matter of design choice. In at least one embodiment, switch 310 is an n-channel MOSFET. In other embodiments, switch 310 is a bipolar junction transistor or an insulated gate bipolar junction transistor. The particular configuration of switch control generator 308 is also a matter of design choice. In at least one embodiment, switch control generator 308 includes both hardware and software (including firmware) to generate control signal CS₁. In at least one embodiment, in non-inductor over-current conditions, switch control generator 308 generates switch control signal CS₁ to operate power regulation switch 310 and thereby provide power factor correction and regulation of link voltage V_LINK as illustratively described in U.S. patent application Ser. No. 11/967,269, entitled “Power Control System Using a Nonlinear Delta-Sigma Modulator with Nonlinear Power Conversion Process Modeling,” inventor John L. Melanson, and filed on Dec. 31, 2007 (referred to herein as “Melanson I”). Melanson I is hereby incorporated by reference in its entirety. During detected inductor current over-current conditions, inductor over-current module 306 utilizes the over-current condition signal VS_OVR to, for example, modify the switch control signal CS₁.

FIG. 4 depicts controller 400, which represents one embodiment of controller 304. FIG. 5 represents exemplary control signal CS₁ and values of volt-second accumulator value A(n)_VS—OVR timing diagrams 500 for n=0 to N−1. “N” represents a number of samples of volt-second accumulator values A(n)VS_OVR during a period of switch control signal CS₁. As subsequently discussed in more detail, the volt-second accumulator value A(n)_VS—OVR represents the n^th sample of the inductor current i_L of switching power converter 400 based on non-inductor-current signals input voltage signal V_X′ and link voltage signal V_LINK′. “TT” and “TT′” represent respective periods of switch control signal CS₁, t₁ and t₁′ represent time durations of respective pulses of switch control signal CS₁, t₂ and t₂′ represent respective inductor flyback times of switching power converter 400, and t₃ represents a time period between an end of the inductor flyback time and a beginning of a next pulse of switch control signal CS₁. “VS_OVR—TH^” represents a threshold value of volt-second accumulator value A(n)_VS—OVR.

Referring to FIGS. 4 and 5, controller 400 includes respective analog-to-digital converters (ADCs) 402 and 404 that respectively convert the input voltage signal V_X′ and link voltage signal V_LINK′ into respective digital values V_X′(n) and V_LINK′(n). “n” is an index representing a current sample, “n−1” represents an immediately preceding sample. Respective low pass filters (LPFs) 406 and 408 respectively low pass filter digital signal values V_X′(n) and V_LINK′(n) to generate respective digital signal values V_X″(n) and V_LINK″(n). The particular design of the ADCs 402 and 404 and LPFs 406 and 408 is a matter of design choice.

In at least one embodiment, the ADCs 402 and 404 are designed to have a response time sufficient to sample and digitize values of the input voltage signal V_X′ and the link voltage signal V_LINK′ that can cause any type of inductor over-current condition addressed by inductor over-current module 410 within the t₁ and t₂ time periods. In at least one embodiment, time period t₁ is less than or equal to 10 microseconds (μs) and greater than or equal to 500 nanoseconds (ns), i.e. 500 ns≦t₁≦10 μs. In at least one embodiment, the bandwidth of link voltage V_LINK is controlled by capacitance C_LINK of link capacitor 114, and the bandwidth of the input voltage V_X is controlled by the capacitance C_RECT of filter capacitor 118. In at least one embodiment, for a 110V input voltage V_X, the sampling frequency of ADCs 402 and 404 is 1.3 MHz. In at least one embodiment, the sampling frequencies of ADCs 402 and 404 are set independently and are respectively 1.875 MHz and 0.725 MHz. An exemplary value of the capacitance C_LINK is 100ρF, and an exemplary capacitance value of C_RECT is 0.47ρF.

The digital signal processor (DSP) 412 determines pulse widths and periods of switch control signal CS₁ and provides the pulse width and period data in pulse width and period signal PWP. Pulse width and period signal PWP can be one or more distinct signals, e.g. separate pulse width and period control signals, that indicate the pulse width and period of switch control signal CS₁. In at least one embodiment, DSP 412 determines the pulse width and period signal PWP as described in Melanson I. From Melanson I, the pulse width and period signal PWP of DSP 412 would consist of a pulse width control signal Q_PW(n) and a period control signal Q_P(n). The particular configuration of DSP 412 is a matter of design choice. In at least one embodiment, DSP 412 is configured as an integrated circuit. In at least one embodiment, DSP 412 accesses and executes software stored in optional memory 414. In at least one embodiment, DSP 412 is implemented using discrete logic components.

A switch control signal generator 416 generates control signal CS₁ based on the information in the pulse width and period signal PWP received from DSP 412 and an over-current condition signal VS_OVR. As subsequently described in more detail, the inductor over-current module 410 generates the over-current condition signal VS_OVR. In at least one embodiment, if over-current condition signal VS_OVR does not indicate an inductor over-current condition, the switch control signal generator 416 generates the control signal CS₁ as described in Melanson I. In at least one embodiment, if over-current condition signal VS_OVR indicates an inductor over-current condition, switch control signal generator 416 modifies control signal CS₁. In at least one embodiment, switch control signal generator 416 modifies control signal CS₁ by ending a pulse or delaying generation of a pulse of control signal CS₁ until the over-current condition is resolved.

The inductor over-current module 410 receives the two non-inductor current input signals V_X′(n) and V_LINK′(n) and, based on the information in the input signals V_X′(n) and V_LINK′(n), determines whether one or more types of inductor over-current conditions exist. The particular configuration of the inductor over-current module 410 is a matter of design choice. In at least one embodiment, inductor over-current module 410 is configured as an integrated circuit. In at least one embodiment, controller 400 includes a processor, such as DSP 412, that executes code stored in optional memory 414 to implement the functions of inductor over-current module 410. In at least one embodiment, inductor over-current module 410 is implemented using logic components as described in more detail with reference to the over-current protection module 700 of FIG. 7.

FIG. 5 depicts a switch control signal generator 600, which represents one embodiment of switch control signal generator 416. The duty cycle module 802 generates a duty cycle modulation control signal DCM_S in response to the pulse width and period information provided by pulse width and period signal PWP. The duty cycle modulation control signal DCM_S represents the value of control signal CS₁ as determined by DSP 412. An inverter 604 inverts over-current condition signal VS_OVR to generate VS_OVR. Logic AND gate 606 performs a logic AND operation on the inverted over-current condition signal VS_OVR and the duty cycle modulation control signal DCM_S. The output of logic AND gate 606 is the switch control signal CS₁. The generation of output signal VS_OVR is discussed in more detail with reference to FIGS. 4, 5, 6, 7, and 8.

The following describes the states and effects thereof of the inverted over-current condition signal VS_OVR and the duty cycle modulation control signal DCM_S:

• • VS_OVR=0: If inverted over-current condition signal VS_OVR is a logical 0, the inductor current i_L is either above a normal operating range and is high enough to cause potential damage to switching power converter 302 and/or load 117 or over-current response process 800 prevents entering CCM by delaying a next pulse of switch control signal CS₁ until the possibility of CCM operation is over.
  • VS_OVR=1: If inverted over-current condition signal VS_OVR is a logical 1, the inductor current i_L is within a normal operating range and compilation profile engine 302 is operating in DCM.
  • DCM_S=0: If the duty cycle modulation control signal DCM_S is a logical 0, DSP 412 has determined that switch control signal CS₁ should be a logical zero.
  • DCM_S=1: If the duty cycle modulation control signal DCM_S is a logical 1, DSP 412 has determined that a pulse of switch control signal CS₁ should begin.

FIG. 7 depicts inductor over-current protection module 700 (“over-current protection module 700”), which represents one embodiment of inductor over-current module 410. FIG. 8 depicts an inductor over-current condition detection and response process 800 (referred to herein as the “over-current response process 800”). The over-current response process 800 represents one embodiment of the operation of inductor over-current module 700. The operation of over-current protection module 700 is described herein with various references to the switching power converter 302 of FIG. 3, the timing diagrams 500 of FIG. 5, and the over-current response process 800 of FIG. 8.

Referring to FIGS. 3, 4, 7, and 8, in summary, for each period of switch control signal CS₁, the operations of over-current response process 800 operate as follows:

• • (i) operations 802 and 804 initialize over-current protection module 700,
  • (ii) operations 806-812 accumulate values of input voltage signal V_X′(n), check for an inductor over-current condition when the inductor current i_L exceeds a potentially harmful level, and terminate a pulse of switch control signal CS₁ if this inductor over-current condition is detected until the inductor current i_L falls to zero, and
  • (iii) (iii) operations 814-818 check for an inductor over-current condition when the inductor current i_L has not reached zero during the inductor flyback period t₂ (FIG. 5) prior to when DSP 412 determines that a next pulse of switch control signal CS₁ should begin.

The over-current protection module 700 receives the input voltage signal V_X′(n) and discrete link voltage signal V_LINK′(n). As previously stated, input voltage signal V_X′(n) and link voltage signal V_LINK′(n) are non-inductor-current signals representing respective, discrete values of input voltage V_X and link voltage V_LINK. The over-current protection module 700 includes an accumulator 702 to accumulate values of input voltage signal V_X′(n) during a pulse of switch control signal CS₁. The accumulator 702 also decrements the current accumulator value A(n)_VS—OVR by [V_LINK′(n)−V_X′(n)] to track the inductor current i_L during inductor flyback periods. Operation 802 is an initialization operation that resets the accumulator output value A(0)_VS—OVR to zero (0) by asserting the RESET signal at the select terminal of 2:1 multiplexer 704. The zero at input 1 of multiplexer 704 forces the accumulator output value A(n)_VS—OVR to zero. After operation 802, the RESET signal is deasserted, and the 0 input is selected by multiplexer 704. In at least one embodiment, the accumulator 702 is a register that is updated at the frequency of clock signal CLK. Thus, forcing the input of accumulator 702 to zero (0) sets the current accumulator value A(n)_VS—OVR to zero (0).

Operation 804 is also an initialization operation. If the switch control signal CS₁ is a logical 1, i.e. switch 310 (FIG. 3) conducts, then over-current response process 800 proceeds to operation 806. Otherwise, over-current response process 800 waits to proceed to operation 806 until the switch control signal CS₁ becomes a logical 1. In at least one embodiment, the inductor over-current module 410 conducts operations 802 and 804 when controller 400 is turned ON.

Referring to FIGS. 3, 5, 7, and 8, the following discussion of over-current response process 800 assumes that inductor over-current module 410 does not detect an inductor over-current condition as indicated by period TT associated with pulse 502 in the timing diagram 500. In operation 804, when switch control signal CS₁ becomes a logical 1 at the beginning of pulse 502, which coincides with the beginning of time period t₁, over-current response process 800 proceeds to operation 806. The logical 1 value of switch control signal CS₁ selects the 1 input of multiplexer 706.

Operation 806 increments the previous accumulator value A(n−1)_VS—OVR by the current value of input voltage signal V_X′. Adder 708 increments the previous (n−1) accumulator value A(n−1)_VS—OVR by the current value (n) of input voltage signal V_X′(n). Multiplexers 706 and 708 pass the sum of V_X′(n) and A(n−1)_VS—OVR so that the input value Y(n) of accumulator 702 equals A(n−1)_VS—OVR+V_X′(n). The current accumulator value A(n)_VS—OVR then becomes Y(n)=A(n−1)_VS—OVR+V_X′(n). Thus, since the initial accumulator value A(0)_VS—OVR equals 0, during time t₁ accumulator 702 effectively accumulates successive values of input voltage signal V_X′(n). The unit of accumulator value A(n)_VS—OVR is “volt-second”.

When control signal CS₁ becomes a logical 1, inductor current i_L (FIG. 3) begins to rise and energy is stored in inductor 112 (FIG. 3). During time t₁, the input voltage V_X is related to the inductor current i_L in accordance with Equation V_X=L·di_L/dt [1]:
V_X=L·di_L/dt  [1];
where L is the inductance value of inductor 112 (FIG. 3). By rearranging Equation V_X=L·di_L/dt [1], Equation

i L = ∫ 0 t ⁢ ⁢ 1 ⁢ _ ⁢ end ⁢ V X L · ⁢ ⅆ t [ 2 ]
[2] illustrates that the inductor current i_L is related to the accumulation (represented in one embodiment by an integration) of the input voltage V_X:

i L = ∫ 0 t ⁢ ⁢ 1 ⁢ _ ⁢ end ⁢ V X L · ⁢ ⅆ t ; [ 2 ]

• • where t_1—end is the time at which time period t₁

Referring to FIGS. 4 and 7, the LPFs 402 and 404 can filter out sudden changes to input voltage signal V_X′ and link voltage signal V_LINK′. Sudden changes in the input voltage signal V_X′ can be caused by, for example, transient voltages produced by transients of input voltage rectified input voltage V_X or ringing in the EMI filter 118. However, as previously discussed, sudden changes to input voltage signal V_X′ can cause improper operation of controller 400. Accordingly, in at least one embodiment, inductor current modules 410 and 700 process the output signals V_X′(n) and V_LINK′(n) directly.

To detect an inductor over-current condition caused by a potentially harmful transient increase of inductor current i_L, operation 808 compares the current accumulator value A(n)_VS—OVR with the over-current threshold value VS_OVR—TH. In at least one embodiment, the over-current threshold value VS_OVR—TH represents a value of input voltage V_X′ that is detectable by ADC 402 and is associated with an inductor current i_L that could potentially damage switching power converter 302 and/or load 117. The particular determination of over-current threshold value VS_OVR—TH is a matter of design choice. In at least one embodiment, over-current threshold value SOVR_TH=VPEAKLOW·VLINK·VXPEAKLOW/(fmax·VLINK·0.85) [3]:
VS_OVR—TH=V_PEAKLOW·(V_LINK−V_XPEAKLOW)/(f_max·V_LINK·0.85)  [3];
where V_PEAKLOW is a minimum root mean square value (RMS) of input voltage V_X, V_LINK is the desired RMS value of link voltage V_LINK, f_max is the maximum frequency of control signal CS₁, and 0.85 is a tolerance factor for a tolerance between a stated inductance value of inductor 112 and an actual inductance value of inductor 112. In one embodiment, for V_PEAKLOW=127V, V_LINK=400V, f_max=80 kHz, VS_OVR—TH=127·(400−127)/(80,000·400·0.85)=0.001275 Vsec.

Equation VS_OVR—TH=V_PEAKLOW·(V_LINK−V_XPEAKLOW)/(f_max·V_LINK·0.85) [3] is derived from Equations [4]-[7]:
L_C=V_PEAKLOW²·(V_LINK−V_PEAKLOW)/(4·f_max·PoVLINK)  [4];
MaxIpeak=V_PEAKLOW·(V_LINK−V_PEAKLOW)/(f_max·L·V_LINK)  [5];
L=0.85L_C  [6];
and
VS_OVR—TH=L_C·MaxIpeak  [7];
where L_C is a maximum inductance value of inductor 112 within the tolerance of an inductance value of inductor 112. PoVLINK represents a maximum power output of switching power converter 302. MaxIpeak is a maximum desired inductor current i_L, and L is the inductance value of inductor 112.

Referring to FIGS. 4, 5, 7, and 8, in operation 808, if the current accumulator value A(n)_VS—OVR does not exceed the over-current threshold value VS_OVR—TH, operation 810 determines if the switch control signal CS₁ is still a logical 1. If the switch control signal CS₁ is still a logical 1, i.e. switch control signal CS₁ is still in time period t₁ (FIG. 5), then over-current response process 800 returns to operation 806 and continues therefrom. Comparator 707 compares the current accumulator value A(n)_VS—OVR with over-current threshold value VS_OVR—TH at operation 808. The output signal VSO of comparator 707 takes the value of logical 1 when the current accumulator value A(n)_VS—OVR is greater than the over-current threshold value VS_OVR—TH and is otherwise a logical 0. A logical 0 is, for example, 0V. If the output signal VSO is a logical 0, the over-current response process 800 returns to operation 806.

By returning to operation 806, accumulator 702 continues to accumulate sample values of input voltage signal V_X′(n). Assuming that the inductor current i_L is not in an over-current condition, i.e. in operation 808 A(n)_VS—OVR≦VS_OVR—TH, when switch control signal CS₁ becomes a logical 0 at the beginning of time period t₂, over-current response process 800 proceeds from operation 810 to operation 814. At the beginning of time period t₂, switching power converter 302 enters the inductor flyback period and proceeds to operation 814.

Operation 814 decrements the previous accumulator value A(n−1)_VS—OVR by the current (n) link voltage signal V_LINK′(n) minus the input voltage V_X′(n) to obtain a current accumulator value A(n)_VS—OVR. To accomplish operation 814, adder 712 adds the link voltage signal V_LINK′ to a negative input voltage signal V_X′, i.e. V_LINK′(n) V_X′(n). Adder 712 adds the previous accumulator value A(n−1)_VS—OVR to the negative of the result of adder 710 and provides the result to saturation module (SAT) 714. SAT 714 passes the output of adder 712 to multiplexer 706 but prevents the output of adder 712 from becoming a negative value. In other words, X(n)=A(n−1)_VS—OVR−[V_LINK′(n)−V_X′(n)], and A(n−1)_VS—OVR=0 if [V_LINK′(n)−V_X′(n)]<0. Switch control signal CS₁ selects the 0 input of multiplexer 706 so that Y(n)=X(n). Value Y(n) is the input to accumulator 702, so the current accumulator value A(n)_VS—OVR=Y(n). Thus, A(n)_VS—OVR=A(n−1)_VS—OVR−[V_LINK′(n)−V_X′(n)] or equals 0 if [V_LINK′(n)−V_X′(n)]<0. By decrementing the current accumulator value A(n)_VS—OVR by the difference between V_LINK′(n) and V_X′(n), the current accumulator value A(n)_VS—OVR is proportional to and, thus, tracks the inductor current i_L.

Operation 816 determines whether the current accumulator value A(n)_VS—OVR is less than or equal to 0. The current state of switch control signal CS₁ when the clock signal CLK transitions to a logical 1 is latched by D-flip flop 715 at the Q output. The Q output is provided as an input to logic AND gate 718. Inverter 720 current provides an inverted switch control signal CS₁ as a second input to AND gate 718. The output of AND gate 718 is falling edge signal CS1_FE. Falling edge signal CS1_FE transitions from a logical 0 to a logical 1 when a pulse, such as pulses 502 or 504, of switch control signal CS₁ transitions from logical 1 to logical 0. In other words, falling edge signal CS1_FE transitions from a logical 0 to a logical 1 at the falling edge of a pulse of switch control signal CS₁.

Logic OR gate 722 receives the output signal VSO from comparator 707 and falling edge signal CS1_FE and generates an output signal VS_SEL. The states and interpretation of output signal VS_SEL are as follows:

• • (i) VS_SEL=1 when at a falling edge of switch control signal CS₁.
  • (ii) VS_SEL=1 if the current accumulator value A(n)_VS—OVR is greater than the volt-second over-current threshold value VS_OVR—TH.
  • (iii) VS_SEL=0 if (a) switch control signal CS₁ is at any state other than a falling edge transition and (b) the current accumulator value A(n)_VS—OVR is less than the volt-second over-current threshold value VS_OVR—TH.

If output signal VS_SEL is a logical 1 due to state (i), then output signal VS_SEL will allow operation 816 to prevent a new pulse, such as pulse 504, of switch control signal CS₁ from occurring if the current accumulator value A(n)_VS—OVR is not zero. If output signal VS_SEL is a logical 1 due to state (ii), then output signal VS_SEL will allow operation 808 to drive switch control signal CS₁ to zero. If output signal VS_SEL is a logical 1, then the pulse width and period signal PWP from DSP 412 controls the state of switch control signal CS₁.

Continuing at operation 816, comparator 716 determines whether the current accumulator A(n)_VS—OVR is less than or equal to zero. If the current accumulator value A(n)_VS—OVR is greater than 0, then the switching power converter 302 is still in an inductor flyback period t₂, and the output of comparator 716 is a logical 1. If the current accumulator value A(n)_VS—OVR is less than or equal to 0, then the switching power converter 302 has completed the inductor flyback, and the output of comparator 716 is a logical 0. A volt-second overprotection signal VS_OVR provides the selection input signal for 2:1 multiplexer 724. Initially, the volt-second overprotection signal VS_OVR is set to logical 0. The output signal VS_SEL is the select signal for 2:1 multiplexer 726. If the accumulator value A(n)_VS—OVR is less than the volt-second over-current threshold value VS_OVR—TH and a falling edge of switch control signal CS₁ is not occurring, then the output signal VS_SEL is a logical 0 and D flip-flop 728 latches output signal VS_OVR to a logical 0. If output signal VS_OVR is a logical 0, then the pulse width and period signal PWP of DSP 412 controls the state of switch control signal CS₁. The value of output signal VS_OVR can cause switch control signal generator 416 (FIG. 4) to override an indication by pulse width and period signal PWP of DSP 412 (FIG. 4) to initiate a pulse of switch control signal CS₁ when the value of inductor current i_L is causing an over-current condition.

In operation 816, if the current accumulator value A(n)_VS—OVR is greater than zero, then the switching power converter 302 is still in an inductor flyback period t₂ and operation 812 keeps the switch control signal CS₁ at zero. Keeping the switch control signal CS₁ at zero stops the current flow into inductor 112 (FIG. 3). The inductor current over-current module 700 follows operation 812 because when the flyback period t₂ begins, switch control signal CS₁ transitions from 1 to 0, and output signal VS_SEL becomes a logical 1. Multiplexer 726 then passes a logical 1, and output signal VS_OVR becomes a logical 1. When output signal VS_OVR is a logical 1, multiplexer 724 selects the output of comparator 716 as the input to multiplexer 726. When switch control signal CS₁ is zero, output signal VS_SEL changes to logical 0 unless the current accumulator value A(n)_VS—OVR is greater than the volt-second over-current threshold value VS_OVR—TH. Assuming the current accumulator value A(n)_VS—OVR is not greater than the volt-second over-current threshold value VS_OVR—TH, the output signal VS_OVR will remain a logical 0 based on the output of comparator 716 until the current accumulator value A(n)_VS—OVR equals zero. If the current accumulator value A(n)_VS—OVR equals zero, the inductor flyback period t₂ of switching power converter 302 has ended. Operations 812, 814, and 816 repeat until the inductor flyback period t₂ is over.

Thus, operations 812, 814, and 816 keep the switch control signal CS₁ at logical 0 thereby preventing a new pulse of switch control signal CS₁ from turning switch 310 ON, until inductor current i_L is zero. When the inductor current i_L equals 0, the inductor flyback period t₂ is over. By keeping the switch control signal CS₁ at logical 0, operations 812, 814, and 816 prevent switching power converter 302 from operating in CCM. Operation 818 determines whether DSP 412 has indicated that the switch control signal CS₁ should be a logical 1. If DSP 412 has indicated that the switch control signal CS₁ should be a logical 1, during exemplary time period t₃, operation 818 waits for DSP 412 to indicate that the switch control signal CS₁ should be a logical 1. When operation 818 is true, over-current response process 800 returns to operation 806.

Referring to FIGS. 3, 5, 7, and 8, the following discussion of over-current response process 800 assumes that inductor over-current module 410 detects two inductor over-current conditions during the period TT′ in the timing diagram 700. The first inductor over-current condition involving a potentially damaging, high inductor current i_L is detected and resolved by operations 806-812. The second inductor over-current condition involves a non-zero inductor current i_L that could cause switching power converter 302 to enter into CCM.

Operations 806-810 proceed as previously described to accumulate input signal value V_X′(n) until operation 808 determines that the current accumulator value A(n)_VS—OVR is greater than the over-current threshold value VS_OVR—TH at the end of time period t′. If the current accumulator value A(n)_VS—OVR is greater than volt-second over-current threshold value VS_OVR—TH, then output signals VSO and VS_SEL become logical 1's. Multiplexer 726 and D flip-flop 728 then force output signal VS_OVR to a logical 1. If output signal VS_OVR is a logical 1, then switch control signal CS₁ is forced to a logical zero. Thus, operation 808 proceeds to operation 812 when current accumulator value A(n)_VS—OVR is greater than volt-second over-current threshold value VS_OVR—TH, and operation 812 causes switch control signal generator 416 to end the pulse 504 of switch control signal CS₁, i.e. switch control signal CS₁ transitions from a logical 1 to a logical 0. Ending the pulse 504 begins the inductor flyback period at the beginning of time period t₂′. Returning switch control signal CS₁ to a logical 0 turns switch 310 OFF, thus preventing the inductor current i_L from further increasing. The output signals VSO and VS_SEL will stay at logical 1 and continue to force output signal VS_OVR to a logical 1 and switch control signal CS₁ to a logical zero for at least as long as the current accumulator value A(n)_VS—OVR is greater than the volt-second over-current threshold value VS_OVR—TH. After switch control signal CS₁ is a logical 0, the falling edge signal CS1_FE transitions to a logical 0. Once the current accumulator value A(n)_VS—OVR is less than the volt-second over-current threshold value VS_OVR—TH, output signal VS_SEL transitions to logical 0, and multiplexers 724 and 726 together with D flip-flop 728 force output signal VS_OVR to the value of the output of comparator 716.

Operations 812-816 delay the onset of the next pulse 506 of switch control signal CS₁ until the current accumulator value A(n)_VS—OVR equals zero at the end of time period t₂′. Operations 812-818 proceed as previously described to determine the end of the inductor flyback period from non-inductor-current signals V_X′(n) and V_LINK′(n) and then return to operation 806. During period TT′, the inductor flyback period extends past the end of time period t₃. Thus, the inductor current i_L and the current accumulator value A(n)_VS—OVR are nonzero at the time when DSP 412 indicates that a new pulse of switch control signal CS₁ should begin. The output of comparator 716 is, thus, a logical 1, which forces the output signal VS_OVR to a logical 1. As described in more detail with reference to FIG. 8, when output signal VS_OVR is a logical 1, the switch control signal CS₁ is forced to a logical 0 as indicated by operation 812.

Setting the output signal VS_OVR to logical 0 delays the onset of a next pulse of switch control signal CS₁ if pulse width and period signal PWP indicates that the next pulse of switch control signal CS₁ should begin. Delaying the onset of a next pulse of switch control signal CS₁ until the current accumulator value A(n)_VS—OVR equals zero prevents operation of switching power converter 302 in CCM. Preventing CCM operation resolves the over-current condition when the inductor current i_L is non-zero at the time DSP 412 indicates that the next pulse 506 of switch control signal CS₁ should begin.

When operation 816 determines that the current accumulator value A(n)_VS—OVR is less than or equal to 0, the inductor current i_L is also zero. When the current accumulator value A(n)_VS—OVR equals 0, the output of comparator 716 is a logical 0, and output signal VS_OVR is set to logical 0. With the output signals VS_OVR and VS_SEL at logical 0, output signal VS_OVR is a logical 0, and the pulse width and switch control signal generator 416 permits period signal PWP of DSP 412 to set switch control signal CS₁.

Referring to FIGS. 4 and 8, in at least one embodiment, the inductor over-current module 410 is implemented as code that is stored in a memory, such as memory 414. When implemented as code, the inductor over-current module 410 implements the over-current response process 800 when executed by a processor of controller 400. The particular type of processor is a matter of design choice and, in at least one embodiment, is DSP 412.

FIGS. 9A and 9B (collectively referred to as FIG. 9) depict inductor over-current protection module 900 (“over-current protection module 900”), which represents another embodiment of inductor over-current module 410. In summary, over-current protection module 900 provides inductor current protection when the inductor current i_L exceeds a threshold value corresponding to the volt-second over-current threshold value V_SOVR—TH in the same manner as inductor current over-current module 700. However, instead of decrementing the accumulation of input voltage signal VX′, over-current protection module 900 uses a DCM inequality of TT·[V_LINK′(n)−V_X′(n)]≧V_LINK′(n)·t₁. Thus, difference signal [link voltage signal V_LINK′(n) minus input voltage signal V_X′(n)] is accumulated over an entire period TT of switch control signal CS1, and the link voltage signal V_LINK′(n) is accumulated until during a pulse, such as pulse 502 or 504 (FIG. 5), of the switch control signal CS₁. Once TT·[V_LINK′(n)−V_X′(n)] is greater than or equal to V_LINK′(n)·t₁, the inductor flyback period is over, and a new pulse of switch control signal CS₁ can be generated by switch control signal generator 416 (FIG. 4).

Referring to FIG. 9A, over-current protection module 900 provides inductor current protection when the inductor current i_L exceeds a threshold value corresponding to the volt-second over-current threshold value V_SOVR—TH. Adder 902, 2:1 multiplexers 904 and 906, accumulator 908, and comparator 910 generate the output signal VSO in the same manner as their respective counterparts: adder 708, 2:1 multiplexers 706 and 704, accumulator 702, and comparator 707 of inductor current over-current module 700 in FIG. 7. Similarly, inverter 912, logic AND gate 914, and D flip-flop 916 generate falling edge signal CS1_FE in the same manner as their respective counterparts: inverter 720, logic AND gate 718, and inverter 720 of inductor current over-current module 700. Logic OR gate 922 determines the output signal VS_SEL in the same manner as logic OR gate 722.

The over-current protection module 900 also detects the rising edge of switch control signal CS₁. Detecting the rising edge of switch control signal CS₁ allows over-current protection module 900 to accumulate the difference signal [link voltage signal V_LINK′(n) minus input voltage signal V_X′(n)] over an entire period, e.g. TT or TT′ (FIG. 5), of switch control signal CS₁. The inverted latched value Q of switch control signal CS₁ by D flip-flop 916 and the current value of switch control signal CS₁ are only both logical 1 at the rising edge of switch control signal CS₁. Accordingly, rising edge signal CS1_RE is a logical 1 at the rising edge transition of switch control signal CS₁ and is otherwise a logical 0.

Referring to FIGS. 5 and 9B, the input voltage accumulator 924 accumulates the link voltage signal V_LINK′(n) during each pulse period t₁* of switch control signal CS₁ to generate an output A(n)_VLINK—t1* equal to V_LINK′(n)·t₁* during each inductor flyback period. “t₁*” represents any pulse period of switch control signal CS₁ including pulse periods t₁ and t₁′. The RESET signal is asserted with a logical 1 to pass a logical 0 to accumulator 926 from 2:1 multiplexer 928 and, thus, reset the current accumulator value A(n)_VLINK—t1* of accumulator 926 to 0. The RESET signal is asserted, for example, during initial startup of input voltage accumulator 924. The RESET signal is then set to logical 0 to pass signal Y2(n) to accumulator 926. The current accumulator value A(n)_VLINK—t1* becomes signal Y2(n). After reset, the rising edge signal CS1_RE selects link voltage signal V_LINK′(n) as the output of 2:1 multiplexer 932. Thus, the current value of link voltage signal V_LINK′(n) becomes the initial value of the current accumulator value A(n)_VLINK—t1* at the beginning of each pulse of switch control signal CS₁. During each pulse t₁* of switch control signal CS₁, multiplexers 928 and 930 pass the “link voltage signal V_LINK′(n)+the previous accumulator value A(n−1)_VLINK—t1*” output of adder 934 to become the current accumulator value A(n)_VLINK—t1*. During the inductor flyback period when switch control signal CS₁ is a logical 0, multiplexers 932, 928, and 930 pass previous accumulator value A(n−1)_VX—t1* to become the current accumulator value A(n)_VLINK—t1*. So, during the inductor flyback period, the current accumulator value A(n)_VLINK—t1* is unchanged. Thus, the output of input voltage accumulator 924 during each inductor flyback period t₁* is A(n)_VLINK—t1*, which equals input voltage signal V_X′(n)·t₁*.

The link-input voltage accumulator 936 accumulates the link voltage signal V_LINK′(n) to accumulate [the link voltage signal V_LINK′(n) minus the input voltage signal V_X′(n) during each period TT* of switch control signal CS₁ to generate an output A(n)_{VLINK-VX—TT} equal to [V_LINK′(n)−V_X′(n)]·TT*. “TT*” represents each period of switch control signal CS₁ including periods TT and TT′. The RESET signal is asserted with a logical 1 to pass a logical 0 to accumulator 938 from 2:1 multiplexer 940 and, thus, reset the current accumulator value A(n)_{VLINK-VX—TT*} of accumulator 938 to 0. The RESET signal is asserted, for example, during initial startup of link-input voltage accumulator 936. The RESET signal is then set to logical 0 to pass signal Y3(n) to accumulator 926. The current accumulator value A(n)_VLINK—TT* becomes signal Y2(n). After reset, the rising edge signal CS1_RE selects V_LINK′(n)−V_X′(n)+A(n)_VLINK—TT* as the output of 2:1 multiplexer 942. “V_LINK′(n)−V_X′(n)+A(n)_{VLINK-VX—TT*}” equals the current value of V_LINK′(n)−V_X′(n). Thus, the current value of V_LINK′(n)−V_X′(n) becomes the initial value of the current accumulator value A(n)_{VLINK-VX—TT*} at the beginning of each pulse of switch control signal CS₁. During each period TT* of switch control signal CS₁, multiplexers 942 and 940 pass V_LINK′(n)−V_X′(n)+A(n)_{VLINK-VX—TT*} from the output of adder 944 to become the current accumulator value A(n)_{VLINK-VX—TT*}. Thus, the output of link-input voltage accumulator 936 during each period TT* of switch control signal CS₁ is A(n)_{VLINK-VX—TT*}, which equals [V_LINK′(n)−V_X′(n)]·TT*.

Comparator 946 generates an output signal VTT that is a logical 0 when V_LINK′(n)·t₁*>{[V_LINK′(n)−V_X′(n)]·TT*}. Output signal VTT is a logical 1 when {[V_LINK′(n)−V_X′(n)]·TT*}>V_LINK′(n)·t₁*. Output signal VTT selects the output of 2:1 multiplexer 948 as output signal VS_OVR when V_LINK′(n)·t₁*>{[V_LINK′(n)−V_X′(n)]·TT*}. Output signal VTT selects the output of 2:1 multiplexer 948 as logical 0 when {[V_LINK′(n)−V_X′(n)]·TT*}>V_LINK′(n)·t₁*. When output signal VS_SEL is a logical 1 indicating that the inductor current i_L (FIG. 4) is above a predetermined threshold, output signal VS_SEL forces multiplexer to output a logical 1. D flip-flop 952 then latches output signal VS_OVR to a logical 1. As previously described with reference to FIG. 8, output signal VS_OVR equal to logical 1 forces switch control signal CS₁ to a logical 0. When output signal VTT is a logical 1 and VS_SEL is a logical 0, output signal VS_OVR is a logical 0. An output signal VS_OVR equal to logical 0 allows the pulse width and period signal PWP of DSP 412 to control the state of switch control signal CS₁.

The states and interpretation of output signals VTT and VS_SEL are as follows:

• • (i) VS_SEL=1 when at a falling edge of switch control signal CS₁.
  • (ii) VS_SEL=1 if the current accumulator value A(n)_VS—OVR is greater than the volt-second over-current threshold value VS_OVR—TH.
  • (iii) VS_SEL=0 if (a) switch control signal CS₁ is at any state other than a falling edge transition and (b) the current accumulator value A(n)_VS—OVR is less than the volt-second over-current threshold value VS_OVR—TH.
  • (iv) VTT=1 if the inductor flyback period is not over.
  • (v) VTT=0 if the inductor flyback period is over.
  • (vi) VS_OVR=1 if VTT or VS_SEL=0 and the pulse width and period signal PWP of DSP 412 controls the state of switch control signal CS₁
  • (vii) VS_OVR=0 if VTT and VS_SEL=1 and switch control signal CS₁ is forced to logical 0.

Thus, a controller in a switching power converter based power control system detects an over-current condition of an inductor current using at least one non-inductor-current signal. In at least one embodiment, the switching power converter does not have a resistor or resistor network to sense the inductor current. The controller indirectly determines a state of the inductor current using at least one non-inductor-current signal.

Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.