Saturation correction without using saturation detection and saturation prevention for a power amplifier

Description

RELATED APPLICATIONS

This application claims the benefit of provisional patent application Ser. No. 61/175,641, filed May 5, 2009, the disclosure of which is hereby incorporated herein by reference in its entirety. This application also claims the benefit of provisional patent application 61/249,170, filed Oct. 6, 2009, the disclosure of which is hereby incorporated herein by reference in its entirety. This application further relates to U.S. Pat. No. 6,701,138, entitled “Power Amplifier Control,” filed Jun. 11, 2001, which is hereby incorporated herein by reference in its entirety.

FIELD OF THE DISCLOSURE

The present disclosure relates to power amplifiers, and particularly to controlling the saturation levels of power amplifiers to maintain desirable switching spectrums for the power amplifiers' outputs.

BACKGROUND

In recent years, worldwide demand for wireless cellular communications has increased dramatically. Radiotelephones manufactured to meet this burgeoning demand must adhere to standards such as the Global System for Mobile Communications (GSM) standard. Another standard, the Digital Cellular System (DCS) standard, is based on GSM, but is directed towards higher cell density and lower power. A third standard, Personal Communications Services (PCS) is a “catch all” for many digital cellular systems, including GSM, operating in North America. These standards all require precise output power control over a large dynamic range in order to prevent a transmitter located in one cell from interfering with the reception of transmissions from other transmitters in neighboring cells.

A key component common to all radiotelephones is a radio frequency (RF) power amplifier (PA). In modern digital radiotelephones, PAs receive as input a modulated RF carrier. The radio frequency carrier is what “carries” digital information such as digitized voice or data to a cellular base station. Before reaching the PA, the RF carrier is too weak to be received by a cellular base station. Therefore, it is the function of the PA to boost the power of the RF carrier to a level sufficient for reception by a cellular base station.

In GSM radiotelephones, the adjustable power control signal must comply with a specification known as a “burst mask.” The burst mask specifies the rise time, fall time, duration, and power levels associated with the adjustable power control signal. The GSM signal consists of eight equal time slots. Each time slot must conform to the burst mask specification. The output of an integrator circuit may be used to control the ramp-up time and ramp-down time of a PA control signal that is responsive to a dynamic baseband signal known as V_RAMP. The amplitude of V_RAMP dictates that the output power of the PA must conform to the shape of the burst mask.

A problem manifests itself in the prior art due to undesirable switching transients that occur when the up and down ramp of the burst is not smooth or changes shape nonlinearly. These switching transients also occur if the control slope of the power amplifier has an inflection point within the output range, or if the control slope is very steep. In particular, this problem will occur when the integrator circuit output attempts to drive the PA beyond its maximum output power capability, as shown in FIG. 1. In this situation, the integrator will ramp up to a maximum possible voltage level such as a power supply voltage, while the output power of the PA will remain at a saturated level.

When the burst is completed, V_RAMP needs to ramp down. However, the integrator circuit output voltage will have to first fall from the maximum possible voltage level, as shown in FIG. 2. During the time it takes for the integrator circuit output voltage to begin to fall, the PA output power will not immediately follow V_RAMP down. However, once V_RAMP decreases to a voltage level in which the PA is once again controllable, the integrator circuit output voltage must “catch up” with V_RAMP. As a result, there will be a sharp drop in the PA's output power, as shown in FIG. 3. As illustrated in FIG. 4, this sharp drop in the PA's output power typically results in failure of the European Telecommunications Standards Institute (ETSI) switching spectrum specification. Notice that both the −400 kHz signal and the +400 kHz signal exceed the ETSI limit as V_RAMP descends.

Thus, there remains a need to provide a circuit and methodology for controlling the saturation levels of power amplifiers to prevent switching transients and maintain desirable switching spectrums for the power amplifiers' outputs.

SUMMARY OF THE DISCLOSURE

The present disclosure provides for control of a power amplifier (PA). In particular, the present disclosure provides a power control circuit and method that provide a saturation correction for a PA in order to maintain a desirable switching spectrum. The power control circuit includes a closed loop system that is responsive to a dynamic baseband signal known as V_RAMP. The dynamic baseband signal (V_RAMP) has an amplitude that dictates the amount of output power delivered by the PA.

The method samples a feedback signal from the PA in order to capture a sample value, such as a detector voltage, that represents the output of the PA when V_RAMP is at or near a maximum level. A fixed dc signal has a magnitude that is derived from the sample value by subtracting a predetermined value from the sample value. The fixed dc signal is applied as a new PA control signal in place of the dynamic baseband signal (V_RAMP). Preferably the predetermined value is selected to decrease the output power of the PA by a fraction of a decibel (dB).

In response to the fixed dc signal, an integrator circuit comprising the closed loop system will force the feedback signal from the PA to equal the fixed dc signal. As a result, the saturation of the PA will be compensated without using a circuit or method for detecting PA saturation. As the amplitude of the dynamic baseband signal (V_RAMP) decreases, the dynamic baseband signal (V_RAMP) is reapplied as a dynamic PA control signal in place of the fixed dc signal. In this way, the PA will not experience an abrupt control input that would generate an undesirable switching spectrum.

Moreover, a saturation prevention method is disclosed that can cooperate with the above disclosed power control circuit and method in order to eliminate the possibility of undesirable power reductions for abnormal operating conditions, such as a low battery voltage supply to the PA being controlled. With the saturation prevention method, the power control circuit may be selectably enabled by a baseband control system to automatically reduce a fixed output power of the PA by a predetermined amount of offset power for power levels above a given power level during transmission of an RF signal. However, the fixed output power is maintained, not reduced, for power levels below the given power level. The power levels available to the PA that are above the given power level are calibrated to include the predetermined amount of offset power. In this way, PA output power at power levels above the given power level will be reduced to a desirable magnitude, whereas PA output power at levels below the given power level will be maintained at a desirable magnitude even in abnormal operating conditions such as a low battery voltage supply for the PA, etc.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIG. 1 depicts power amplifier (PA) control signal waveforms associated with the beginning of a GSM burst.

FIG. 2 depicts PA control signal waveforms associated with the end of a GSM burst.

FIG. 3 depicts an undesirable effect of saturation on a PA output power at the end of the GSM burst as the voltage of the PA control signal drops steeply.

FIG. 4 illustrates a severe degradation of the output switching spectrum due to a steep change in PA power output.

FIG. 5 depicts a mobile terminal having PA control circuitry according to an embodiment of the present disclosure.

FIG. 6 is a flowchart that illustrates a method according to the present disclosure for correcting a saturation of a PA.

FIG. 7 depicts the response of the PA control signal waveforms to the method of FIG. 6 at the beginning of a GSM burst.

FIG. 8 depicts the response of the PA control signal waveforms to the method of FIG. 6 at the end of a GSM burst.

FIG. 9 illustrates the improved output switching spectrum resulting from the implementation of the method of FIG. 6.

FIG. 10 is a detailed schematic of the power control circuitry of FIG. 5 that is in accordance with the present disclosure.

FIG. 11 is a graph of PA output power versus battery voltage illustrating the results of the saturation prevention method combined with the saturation correction method.

FIG. 12 is a graph of PA output power versus battery voltage illustrating the results of the saturation correction method without the saturation prevention method.

FIG. 13 is a graph of +/−400 kHz switching spectrum versus battery voltage.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice embodiments of the disclosure and illustrate the best mode of practicing the principles of the disclosure. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

With reference to FIG. 5, an embodiment of the present disclosure is preferably incorporated in a mobile terminal 20, such as a mobile telephone, personal digital assistant (PDA), or the like. The basic architecture of the mobile terminal 20 may include a receiver front end 22, a radio frequency (RF) transmitter section 24, an antenna 26, a duplexer or switch 28, a baseband processor 30, a control system 32, a frequency synthesizer 34, and an interface 36. The receiver front end 22 receives information bearing RF signals from one or more remote transmitters provided by a base station. A low noise amplifier (LNA) 37 amplifies the signal. A filter circuit 38 minimizes broadband interference in the received signal, while a downconverter 40 downconverts the filtered received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams. The receiver front end 22 typically uses one or more mixing frequencies generated by the frequency synthesizer 34.

The baseband processor 30 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. As such, the baseband processor 30 is generally implemented in one or more digital signal processors (DSPs).

On the transmit side, the baseband processor 30 receives digitized data from the control system 32, which it encodes for transmission. The encoded data is output to the RF transmitter section 24, where it is used by a modulator 42 to modulate a carrier signal that is at a desired transmit frequency. Power amplifier circuitry 44 amplifies the modulated carrier signal to a level appropriate for transmission from the antenna 26.

As described in further detail below, the power amplifier circuitry 44 provides gain for the signal to be transmitted under control of power control circuitry 46, which is preferably controlled by the control system 32 using the V_RAMP signal. A detector circuit 47 provides a feedback signal (V_DET) from the output of the power amplifier circuitry 44 to the power control circuitry 46. Preferably, the bias for the power amplifier circuitry 44 is relatively stable regardless of power, and varying the voltage supplied to the power amplifier circuitry 44 controls actual power levels. The control system 32 may also provide a transmit enable (TX ENABLE) signal to effectively turn the power amplifier circuitry 44 and power control circuitry 46 on during periods of transmission. The control system 32 may also include a general purpose input/output (GPIO) signal line for sending commands and data to the power control circuitry 44.

A user may interact with the mobile terminal 20 via the interface 36, which may include interface circuitry 48 associated with a microphone 50, a speaker 52, a keypad 54, and a display 56. The interface circuitry 48 typically includes analog-to-digital converters, digital-to-analog converters, amplifiers, and the like. Additionally, it may include a voice encoder/decoder, in which case it may communicate directly with the baseband processor 30.

The microphone 50 will typically convert audio input, such as the user's voice, into an electrical signal, which is then digitized and passed directly or indirectly to the baseband processor 30. Audio information encoded in the received signal is recovered by the baseband processor 30, and is converted into an analog signal suitable for driving speaker 52 by the input/output and interface circuitry 48. The keypad 54 and display 56 enable the user to interact with the mobile terminal 20 by inputting numbers to be dialed, address book information, or the like, and monitoring call progress information.

Turning now to FIG. 6, a method according to the present disclosure provides saturation correction for a PA of power amplifier circuitry 44 (FIG. 5) without using saturation detection. The disclosed method may be implemented using the power control circuitry 46 of FIG. 5. As shown by the flowchart of FIG. 6, the disclosed saturation correction method begins with a dynamic baseband signal (V_RAMP) that linearly increases from an initial voltage such as a pedestal of a few tenths of a volt (step 120). Preferably, the control system 32 (FIG. 5) provides the V_RAMP signal to the power control circuitry 46 (FIG. 5).

The power control circuitry 46 receives the V_RAMP signal as input, and in turn integrates the V_RAMP signal with the feedback signal (V_DET) to produce an output to the power amplifier circuitry 44 (step 122). The detector circuit 47 (FIG. 5) provides the feedback signal V_DET, which in this case is not used to detect PA saturation.

An inherent delay is maintained until the V_RAMP signal increases to a voltage level that is above a predetermined voltage level (step 124). In an example embodiment, the predetermined voltage level corresponds to a PA output power that is slightly greater than 20 dBm. Once the V_RAMP signal exceeds the predetermined voltage level, a predetermined delay is initiated (step 126). The predetermined delay is preferably around 120 microseconds (μS). Other values of delay can be used depending on a user's particular baseband application.

A sample voltage of the feedback signal V_DET is captured once the predetermined delay has expired (step 128). Next, the control of the output from the power amplifier circuitry 44 via the dynamic V_RAMP signal is removed while a constant voltage equal to the V_RAMP sample voltage is maintained as output to the power amplifier circuitry 44 (step 130). Practically instantaneously, a value of voltage equal to the V_DET sample voltage minus a predetermined offset voltage is applied to the power amplifier circuitry 44 (step 132). The predetermined offset voltage is selected such that the PA of the power amplifier circuitry 44 is slightly below the saturated power level at the time the dynamic V_RAMP signal is removed from controlling the output of the power control circuitry 46. A preferred offset voltage value is selectable to decrease the amount output power delivered by the power amplifier circuitry 44 during saturation by a fraction of a dBm.

At some point in time, the V_RAMP signal reaches a maximum voltage level and begins a voltage decrease. An output voltage of the power control circuitry 46 is maintained with the level of the V_DET sample voltage minus the offset voltage until the V_RAMP signal voltage decreases (step 134). Once the V_RAMP voltage begins to decrease, the dynamic V_RAMP signal is reapplied within the power amplifier circuitry 44 such that the dynamic V_RAMP signal is integrated with the feedback signal (V_DET) to provide output for controlling the power of the PA of the power amplifier circuitry 44 (step 136). The dynamic V_RAMP signal continues to dictate the PA output until the completion of the ramp down of the dynamic V_RAMP signal (step 138). As another GSM burst approaches, the V_RAMP signal begins again (step 120).

FIG. 7 depicts an example of a typical response of the PA control signal waveforms to the method of FIG. 5 at the beginning of a GSM burst. Notice that between about 57 quarter symbols (qs) and 77 qs, the ramp waveform is provided by the dynamic V_RAMP signal. At about 77 qs into the ramp signal, the dynamic V_RAMP signal is replaced by the sample and hold voltage of the V_DET minus an offset voltage of a few tenths of a volt. In response to the now slightly lower voltage level for the ramp signal, the integrator output voltage level falls away from a maximum voltage level that is typically the voltage of a supply rail that provides power to the power control circuitry 46 (FIG. 5), and thus is no longer saturated.

FIG. 8 depicts the response of the PA control signal waveforms to the method of FIG. 5 at the end of a GSM burst. Notice that by about 657 qs, the dynamic V_RAMP signal once again provides the ramp waveform. However, in contrast to the typical integrator output voltage level shown in FIG. 2, the integrator output voltage level shown in FIG. 8 is not at a maximum voltage level. Instead, the integrator output voltage level is well below the maximum voltage level and corresponds to an output power level that is not saturated. Thus, the feedback loop of the integrator is active and can respond correctly to changes in the dynamic V_RAMP signal.

FIG. 9 illustrates the improved output switching spectrum that results from the disclosed method that eliminates a need for the integrator output voltage to follow the dynamic V_RAMP signal with a steep descent. Notice that in FIG. 9 both the +400 kHz spectrum and the −400 kHz spectrum fall well below the ETSI spectrum limit. In fact, at the critical time around 657 qs when the V_RAMP signal's voltage begins to transition from near maximum PA power, the +400 kHz spectrum and the −400 kHz spectrum improves on the order of −15 db in comparison with the same time period depicted in FIG. 4.

Turning now to FIG. 10, a detailed schematic of the power control circuitry 46 of FIG. 5 is disclosed. A first terminal of a capacitor C1 is coupled to a non-inverting input 58 of an op amp U1 and a second terminal of the capacitor C1 is coupled to a fixed voltage reference and, in this case, ground. The non-inverting input 58 selectably receives a V_RAMP signal through a switch S1 and a V_RAMP input 59. The op amp U1 has an output terminal 60 coupled to a gate 62 of a transistor Q1. A drain 64 of the transistor Q1 is coupled to the inverting input 66 of op amp U1 such that the voltage on the non-inverting input 58 will be reproduced on the drain 64 of the transistor Q1.

The V_RAMP signal is coupled to the drain 64 of the transistor Q1 through a resistor R1. The V_RAMP signal is also coupled to a drain 68 of a transistor Q2 through a resistor R2. A gate 70 of the transistor Q2 is selectably coupled through a switch S2 to the gate 62 of the transistor Q1. The gate 70 of the transistor Q2 is also selectably coupled through a resistor R3 and a switch S3 to the gate 62 of the transistor Q1. A capacitor C2 has a first terminal coupled to the gate 70 of the transistor Q2 and a second terminal coupled to ground. The capacitor C2 is usable to maintain a voltage on the gate 70 of the transistor Q2 when the switch S3 is open. The resistor R3, along with the capacitor C2, sets a smooth transition of the voltage on the gate 70 when the switch S3 closes. After this transition is essentially complete, the switch S2 closes to insure the voltage is fully settled.

The drain 68 of the transistor Q2 is also coupled to a non-inverting input 72 of an op amp U2. An output 74 provides a PA control signal for the power amplifier circuitry 44. The output 74 is also coupled to a first terminal of a capacitor C3. The capacitor C3 has a second terminal coupled to ground. The output 74 is also coupled to a resistor-capacitor filter made up of a resistor R11 that is in series with a capacitor C4 that has a terminal coupled to ground. An inverting input 76 of the op amp U2 is coupled to the detector circuit 47, which is coupled to an output of the power amplifier circuitry 44.

In this preferred embodiment of the disclosure, the op amp U2 is a transconductance amplifier. As configured in FIG. 10, the op amp U2 and capacitor C3 form an integrator that integrates signals that are applied to the non-inverting input 72 and the inverting input 76. In this case, the V_RAMP signal is periodically applied to the non-inverting input 72, whereas the feedback signal V_DET provided by the detector circuit 47 is continuously applied to the inverting input 76.

The feedback signal V_DET is also selectably applied to a non-inverting input 78 of an op amp U12 through a switch S4. A capacitor C5 is coupled to the non-inverting input 78 and ground. An inverting input 80 of the op amp U12 is coupled through a variable resistor R12 to an output terminal 82 of the op amp U12. This particular configuration of U12 forms a sample-and-hold-type circuit.

A current source 84 is tapped into the variable resistor R12 to provide a correction offset voltage signal (COR_OFS) that is summed with a V_DET sample voltage held by the capacitor C5. The output terminal 82 is selectably coupled through a resistor R5 and the switch S5 to the non-inverting input 58 of the op amp U1. The resistor R5 forms an RC time constant with the capacitor C1 such that when the switch S1 opens and the switch S5 closes there will be a smooth transition between what may be two different voltage levels. The resistance value of R5 preferably provides an RC time constant of one or two microseconds.

An AND gate U13 receives four inputs. One input signal is a baseband signal (i.e., SATURATION PREVENTION) that is usable for a saturation prevention mode. Another input signal (MODE=GMSK(0)) is used to signify whether or not the power amplifier circuitry 44 is to operate in GMSK mode. Yet another input signal signifies whether or not the V_RAMP signal will yield a PA output power (P_OUT) that is greater than a 20 dBm power reference. Other power level references could be selected, but 20 dBm is a convenient choice because the PA of power amplifier circuitry 44 will typically not saturate at power levels of less than 20 dBm. One more input signal is a delay signal from a DELAY 86. The delay signal from the DELAY 86 is inverted by an inverter gate 88 before the delay signal reaches the input of the AND gate U13.

The DELAY 86 is triggered from an output terminal 90 of an op amp U5. The op amp U5 has a non-inverting input 92 coupled to the V_RAMP input 59 and an inverting input 94 coupled to a voltage reference 96. Preferably, the voltage reference 96 is equal to a voltage of V_RAMP that yields a P_out of 20 dBm. The delay signal from the DELAY 86 also is inputted into an AND gate U7 that also receives input from a Q output of a set/reset (SR) flip-flop U9. The AND gate U7 has an output terminal 98 that controls the opening and closing of switches S1, S4 and S5.

The output terminal 98 of the AND gate U7 is also coupled to a DELAY 100 that is triggered when the logic state of the AND gate U7 transitions from a logic low to a logic high. An output terminal 102 of the DELAY 100 is coupled to the S input of an SR flip-flop U10 and to the S input of an SR flip-flop U11. A Q output of the SR flip-flop U10 controls the opening and closing of the switch S3, while a Q output of the SR flip-flop U11 controls the opening and closing of the switch S2. Moreover, the Q output of the SR flip-flop U10 feeds an input terminal 104 of an OR gate U8, which in turn has an output terminal 106 that feeds an R input of the SR flip-flop U9. The OR gate U8 has another input terminal 107 that is coupled to an output terminal 108 of an op amp U6. The op amp U6 has an inverting input 110 coupled to the V_RAMP input 59 and a non-inverting input 112 coupled to a voltage reference 114 that has a voltage equal to a voltage of V_RAMP that yields a P_out of 10 dBm. The output terminal 108 of the op amp U6 is also coupled to a DELAY 116 that feeds a delay signal to an R input to SR flip-flop U11.

At the beginning of operation, the switches S1, S2, S3, and S4 are closed, while the switch S5 is open. As a result of this beginning configuration of the switches S1, S2, S3, S4, and S5, an equivalent of the V_RAMP signal is inputted to the non-inverting input 72 of the op amp U2, which performs the integrator function along with capacitor C3.

Once V_RAMP rises to a level that urges the PA of power amplifier circuitry 44 to deliver a power level greater than 20 dBm, and while at the same time the SATURATION PREVENTION signal is at a logic high, and the GMSK(0) signal is at a logic low, and the output of the DELAY 86 is at a logic low, the AND gate U13 will output a logic high. The logic high output of the AND gate U13 will set the Q output of a flip-flop U9 to a logic high level. Moreover, a timing function of the DELAY 86 will begin.

The AND gate U7 receives the Q output of flip-flop U9 and the logic output of the DELAY 86. At first, the output of the DELAY 86 is low. However, the output of the DELAY 86 will transition to a logic high as soon as the delay time has expired. The delay time expiration should insure that the V_RAMP signal is at a maximum. The delay time for the DELAY 86 may be preset to be as short as 20 microseconds or as great as 125 microseconds depending on the specific needs of the baseband system. Note also that when the output of delay goes high, the output of an inverter gate 88 coupled to an input of the AND gate U13 goes low. Nevertheless, the Q output of the SR flip-flop U9 will remain unchanged. However, it is important to remove the high logic level from the S input of the flip-flop U9 after the delay, because at some point the flip-flop U9 will be reset by a high logic level. This is because a high logic level is not simultaneously allowable on both the S and R inputs of the flip-flop U9.

Now that the AND gate U7 has both inputs at a logic high, the output of the AND gate U7 will go to a logic high, which in turn will open the switches S1 and S4 and close the switch S5. The capacitor C5, which is coupled to the non-inverting input 78 of op amp U12, is by now charged with a sample of the feedback signal V_DET, which is provided by the detector circuit 47. The saturation correction offset signal (COR_OFS) is subtracted from the voltage of C5, which is the sample and hold voltage captured from the feedback signal V_DET. The sample and hold voltage held by the capacitor C5 minus the COR_OFS is outputted from the output terminal 82 of op amp U12. Since switch S5 is closed at this time, the capacitor C1 is charged to the sampled detector voltage that is present at the non-inverting input 78 of U12 minus the COR_OFS signal voltage.

In response, an output voltage at the output terminal 60 of the op amp U1 is applied to the gate 62 of the transistor Q1 such that the voltage impressed upon the non-inverting input 58 from the charged capacitor C1 appears at the drain 64 of the transistor Q1. Similarly, the output of the op amp U1 is applied to the gate 70 of the transistor Q2 through the closed switch S2 such that the voltage impressed upon the non-inverting input 58 of the op amp U1 from the charged capacitor C1 appears at the drain 68 of the transistor Q2. Since the drain 68 of the transistor Q2 is directly coupled to the non-inverting input 72 of the op amp U2, the output of the op amp U2 will be equal to the sampled V_DET detector voltage of capacitor C5 minus the saturation correction offset voltage COR_OFS. The output of the op amp U2 is applied to the power amplifier circuitry 44 for the duration of the burst.

When the output of the AND gate U7 goes high, the DELAY 100 starts a 5 microsecond delay. At the end of the 5 microsecond delay, the SR flip-flop U10 is set, which forces the Q output of the SR flip-flop U10 to transition from a logic low to a logic high, thereby opening the switch S3. The SR flip-flop U11 is also set at the end of the 5 microsecond delay, which results in the opening of the switch S2 when the Q output of the SR flip-flop U10 is forced high. However, the capacitor C2 remains charged and applies a voltage to the gate 70 of the transistor Q2 such that the sampled detector voltage of capacitor C5 minus the saturation correction offset voltage COR_OFS will remain on the drain 68 of the transistor Q2. Therefore, until the V_RAMP signal decreases to a voltage level that begins to bring the PA of power amplifier circuitry 44 out of saturation, the sampled detector voltage of capacitor C5 minus the saturation correction offset voltage COR_OFS will remain on the non-inverting input 72 of the op amp U2.

Once the V_RAMP signal descends, the voltage on the non-inverting input 72 of the op amp U2 will follow the V_RAMP signal. This is because the V_RAMP signal is applied directly to a common node 118 of the resistor R1 and the resistor R2.

As soon as the V_RAMP signal voltage drops to a point at which the output power of the PA of the power amplifier circuitry 44 is less than 10 dBm, the output of op amp U6 will transition from a logic low to a logic high. The outputted logic high from op amp U6 will force the output of the OR gate U8 to transition from a logic low to a logic high, which in turn will reset the SR flip-flop U9. As a result, the output of the AND gate U7 will transition from a logic high to a logic low, causing the switch S1 and the switch S4 to close. Simultaneously, the switch S5 will be opened. The high output of the op amp U6 will also reset the SR flip-flop U10, which will close the switch S3 and will initiate the DELAY 116 to start a 3 microsecond delay. After the 3-microsecond delay expires, the SR flip-flop U11 is reset, and the Q output of the SR flip-flop U11 transitions from a logic high to a logic low, thereby closing switch S2. At this point, the power control circuitry 46 is ready for another V_RAMP cycle.

A saturation prevention method is also disclosed to cooperate with the power control circuit 46 and method of FIG. 6 in order to eliminate the possibility of undesirable power reductions for abnormal operating conditions, such as a low battery voltage supply to the power amplifier circuitry 44. With the saturation prevention method, the power control circuit 46 may be selectably enabled by the control system 32 (FIG. 5) to automatically reduce a fixed output power of the PA by a predetermined amount of offset power for power levels above a given power level during transmission of an RF signal. However, the fixed output power is maintained, not reduced, for power levels below the given power level. The power levels available to the PA that are above a given power level are calibrated to include the predetermined amount of offset power, such as an additional 0.3 db. In this way, even in abnormal operating conditions, such as a low battery voltage for the power amplifier circuitry 44, the PA output power at power levels above the given power level will be reduced to a desirable magnitude, whereas PA output power at levels below the given power level will be maintained at a desirable magnitude.

In order to implement the saturation prevention method, the control system 32 can use the GPIO signal line (FIG. 5) to transmit a baseband data signal having a value (e.g., COR_OFS) that is indicative of the predetermined amount of offset power. A typical value for the predetermined amount of offset power is 0.3 dB. For example, a power level known as a power control level (PCL) for the ETSI standard is 24 dBm. In this example, the 24 dBm is the given power level for which higher power levels have the power offset added during calibration of the power amplifier circuitry 46. In this case, the next highest ETSI PCL of 26.0 dBm would be calibrated to equal 26.3 dBm. Likewise, an ETSI PCL of 28.3 dBm would be calibrated to 28.6 dBm and an ETSI PCL of 30 dBm would be calibrated to equal 30.3 dBm.

FIG. 11 is a graph that depicts a customer's desire to have an output power of 31.1 dBm with no saturation correction, and an output power of 30.8 dBm with saturation prevention. Notice that at points on the graph wherein the battery voltage begins to droop, the saturation correction power output will follow a saturation power limit, whereas the saturation prevention output will always be below the saturation prevention output by the amount of the power offset. In this case, the power offset is 0.3 dBm.

FIG. 12 is a graph showing a saturation detection and correction type method that dictates PA output power until the battery voltage drops below about 3.7V, at which point the saturation correction method takes over. However, in this case, saturation correction by itself reduces output power by too much. Turning back to FIG. 11, notice that the saturation correction method would not reduce the PA output power by too much because the saturation prevention method provides the additional offset power amount of 0.3 dB.

FIG. 13 is a graph of a +/−400 kHz switching spectrum versus battery voltage. This graph illustrates the value of the disclosed saturation correction and saturation prevention methods. Notice that when a battery supply voltage drops below a certain point, and in this case to around 3.5V, the +/−400 kHz switching spectrum increases to an undesirable level that is greater than −20 dBm. In contrast, both the saturation correction method and the saturation prevention method maintain a desirable +/−400 kHz switching spectrum that is below −30 dBm for all battery voltage levels.

Those skilled in the art will recognize improvements and modifications to the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein.