High-efficiency power supply for a modulated load

Description

This application claims the benefit of provisional patent application Ser. No. 61/225,315, filed Jul. 14, 2009, the disclosure of which is hereby incorporated herein by reference in its entirety.

FIELD OF THE DISCLOSURE

Embodiments of the present invention relate to high-efficiency power supplies, which may be used to provide power to an amplitude modulated load, such as an amplitude-modulated radio frequency (RF) power amplifier, which may be used in an RF communications system.

BACKGROUND OF THE DISCLOSURE

As technology progresses, portable devices tend to integrate more features. For example, portable devices may include features associated with personal digital assistants (PDAs), cellular telephones, wireless internet access devices, global positioning system (GPS) receivers, and the like. Such portable devices may support one or more wireless communications protocols, such as third (3G), fourth (4G), or later generation cellular telephone protocols, GPS protocols, wireless fidelity (Wi-Fi) protocols, Bluetooth®, and the like. Some of these protocols may have tight channel spacing that require narrow channel bandwidths and tight restrictions on transmissions of spurious RF signals outside a channel's bandwidth. Often, to meet channel bandwidth requirements and to meet spurious RF emissions requirements, an RF transmitter may need to meet stringent linearity and noise requirements. An RF power amplifier in an RF transmitter may be a major source of non-linearity; therefore, there is a need for an RF power amplifier that meets stringent linearity requirements.

Most portable devices are battery powered and, since battery life is inversely related to power consumption, need to consume as little power as possible to maximize battery life. The RF power amplifier in a wireless portable device may consume a significant portion of the power used by the portable device. One way to reduce power consumption in an RF power amplifier is to improve its efficiency. Some communications protocols, such as those using wideband code division multiple access (WCDMA), may require polar modulation of an RF signal. Polar modulation includes an amplitude modulation (AM) component and a phase modulation (PM) component. To maximize efficiency in an amplitude-modulated or polar-modulated RF power amplifier, an envelope power supply input to the RF power amplifier may be provided by an AM power supply, which may include a switching power supply that tracks, at least to some extent, the amplitude of an amplitude-modulated or polar-modulated RF signal to the RF power amplifier.

Linearity of the RF power amplifier may be degraded when using a constant power supply due to modulation of the gain of the RF power amplifier by the RF envelope, which is associated with AM. Additionally, the AM power supply must provide adequate headroom for proper operation of the RF power amplifier. In some systems, such as 4G or later communications protocols, the bandwidth of an AM signal used to modulate the AM power supply may be about 12 megahertz or more; therefore, for proper tracking, the bandwidth of the AM power supply may need to be about 12 megahertz or more. Such an AM power supply may include a switching power supply circuit for high efficiency and a linear power supply circuit to meet bandwidth requirements; however, linear power supplies are typically less efficient than switching power supplies. Therefore, a 12 megahertz AM power supply may be less efficient than an AM power supply with less bandwidth. Thus, there is a need for an AM power supply having wide bandwidth and high efficiency that allows RF power amplifier circuitry to meet linearity requirements.

SUMMARY OF THE EMBODIMENTS

The present disclosure relates to power supply circuitry that has wide bandwidth and achieves high efficiency by using at least one energy storage element for efficient power transfer between two power supply circuits and to an amplitude modulated load, such as an amplitude modulated or polar modulated power amplifier. Specifically, the power supply circuitry may include a first power supply circuit, which may be a switching power supply circuit, a second power supply circuit, which may be a linear power supply circuit and may include the energy storage element, and control circuitry to facilitate efficient power transfer. The control circuitry may select one of multiple operating modes, which may include a first operating mode and a second operating mode. During the first operating mode, the first power supply circuit may provide power to the amplitude modulated load and may provide power to the energy storage element. During the second operating mode, the second power supply circuit may provide power to the amplitude modulated load from the energy storage element. Further, during the second operating mode, the first power supply circuit may also provide power to the amplitude modulated load.

An output bandwidth of the linear power supply circuit and a modulation bandwidth of the amplitude modulated load may both be wider than an output bandwidth of the switching power supply circuit. The switching power supply circuit may provide efficient transfer of power from a direct current (DC) power supply, such as a battery, to the amplitude modulated load. However, since the output bandwidth of the switching power supply circuit may be narrower than the modulation bandwidth of the amplitude modulated load, the switching power supply circuit may be unable to provide power to the amplitude modulated load without significant levels of distortion.

In this regard, since the output bandwidth of the linear power supply circuit may be wider than the output bandwidth of the switching power supply circuit, the linear power supply circuit may be able to supplement the switching power supply circuit to provide power to the amplitude modulated load with minimal distortion. However, since the linear power supply circuit may provide power using series pass devices, efficiency may suffer. When the series pass devices are coupled to the DC power supply or to ground, the resulting voltage drops across the series pass devices may be relatively large, thereby resulting in significant losses. However, when the series pass devices are coupled to the energy storage element instead of to the DC power supply or to ground, the resulting voltage drops across the series pass devices may be significantly reduced, thereby improving efficiency.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIG. 1 shows power supply circuitry according to one embodiment of the power supply circuitry.

FIG. 2 shows details of a second power supply circuit illustrated in FIG. 1 according to one embodiment of the second power supply circuit.

FIG. 3 shows details of a first power supply circuit and the second power supply circuit illustrated in FIG. 1 according to one embodiment of the first power supply circuit and the second power supply circuit.

FIG. 4 shows an amplitude-modulated RF power amplifier circuit, according to the prior art.

FIG. 5 shows an amplitude-modulated RF power amplifier circuit, according to one embodiment of the present disclosure.

FIG. 6 shows a polar-modulated RF power amplifier circuit, according to an alternate embodiment of the present disclosure.

FIG. 7 shows a polar-modulated quadrature RF power amplifier circuit, according to an additional embodiment of the present disclosure.

FIG. 8 shows the power supply circuitry illustrated in FIG. 3 according to an alternate embodiment of the power supply circuitry.

FIG. 9 is a graph showing a first current, a second current, a load current, and a bypass current illustrated in FIG. 8 according to one embodiment of the power supply circuitry.

FIG. 10 shows details of a linear power supply circuit and control circuitry illustrated in FIG. 8 according to one embodiment of the linear power supply circuit and the control circuitry.

FIG. 11 shows details of the linear power supply circuit and the control circuitry illustrated in FIG. 8 according to an alternate embodiment of the linear power supply circuit and the control circuitry.

FIG. 12 shows details of the linear power supply circuit and the control circuitry illustrated in FIG. 8 according to an additional embodiment of the linear power supply circuit and the control circuitry.

FIG. 13 shows details of the linear power supply circuit and the control circuitry illustrated in FIG. 8 according to another embodiment of the linear power supply circuit and the control circuitry.

FIG. 14 shows details of the linear power supply circuit and the control circuitry illustrated in FIG. 8 according to a supplemental embodiment of the linear power supply circuit and the control circuitry.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

The present disclosure relates to power supply circuitry that has wide bandwidth and achieves high efficiency by using at least one energy storage element for efficient power transfer between two power supply circuits and to an amplitude modulated load, such as an amplitude modulated or polar modulated power amplifier. Specifically, the power supply circuitry may include a first power supply circuit, which may be a switching power supply circuit, a second power supply circuit, which may be a linear power supply circuit and may include the energy storage element, and control circuitry to facilitate efficient power transfer. The control circuitry may select one of multiple operating modes, which may include a first operating mode and a second operating mode. During the first operating mode, the first power supply circuit may provide power to the amplitude modulated load and may provide power to the energy storage element. During the second operating mode, the second power supply circuit may provide power to the amplitude modulated load from the energy storage element. Further, during the second operating mode, the first power supply circuit may also provide power to the amplitude modulated load.

FIG. 1 shows power supply circuitry 10 according to one embodiment of the power supply circuitry 10. The power supply circuitry 10 includes a first power supply circuit 12, a second power supply circuit 14, and control circuitry 16. The power supply circuitry 10 receives a power supply control input signal PSCIS and DC power from a DC supply DCSPLY, and provides power to an amplitude modulated load 18 via a power supply output signal PSOS. The power supply circuitry 10 uses the power supply control input signal PSCIS to regulate the power supply output signal PSOS. In one embodiment of the power supply control input signal PSCIS, the power supply control input signal PSCIS is amplitude modulated, thereby amplitude modulating the power supply output signal PSOS. The AM of the power supply control input signal PSCIS may correlate with AM of the amplitude modulated load 18. In an alternate embodiment of the power supply control input signal PSCIS, the power supply control input signal PSCIS is not amplitude modulated. However, in this embodiment, the power supply control input signal PSCIS may be adjusted to accommodate modulation peaks of the amplitude modulated load 18.

The control circuitry 16 selects one of multiple operating modes, which includes at least a first operating mode and a second operating mode. During both the first and second operating modes, the first power supply circuit 12 may provide power to the amplitude modulated load 18 via a first output signal OS1 using DC power supplied from the DC supply DCSPLY. During the first operating mode, the first power supply circuit 12 may provide power to the second power supply circuit 14 via the first output signal OS1 and during the second operating mode, the second power supply circuit 14 may provide power to the amplitude modulated load 18 via a second output signal OS2. During the first operating mode, and during other operating modes, the second power supply circuit 14 may provide power to the amplitude modulated load 18 using DC power supplied from the DC supply DCSPLY. The first output signal OS1 has a first current I1 and the second output signal OS2 has a second current I2. The first output signal OS1 and the second output signal OS2 may combine to provide the power supply output signal PSOS to the amplitude modulated load 18. The control circuitry 16 receives and selects the operating mode using the power supply output signal PSOS and an energy storage status signal ESSS. Further, the control circuitry 16 provides a mode select signal MSS, which is indicative of the selected mode, to the second power supply circuit 14.

The second power supply circuit 14 receives the power supply control input signal PSCIS and provides a first power supply control signal PSCS1 to the first power supply circuit 12. The first power supply circuit 12 may have higher efficiency and narrower bandwidth than the second power supply circuit 14. Therefore, to maximize efficiency, most of the power may be provided by the first power supply circuit 12 and the second power supply circuit 14 may be used to overcome bandwidth limitations of the first power supply circuit 12. The first power supply circuit 12 may regulate the first output signal OS1 using the first power supply control signal PSCS1. To ensure that most of the power is provided by the first power supply circuit 12, the second power supply circuit 14 may regulate the first power supply control signal PSCS1 to minimize the second current I2. Minimizing the second current I2 minimizes the power provided by the second power supply circuit 14. As such, the second power supply circuit 14 may regulate the second output signal OS2 using the power supply control input signal PSCIS to provide the appropriate power supply output signal PSOS and may regulate the first power supply control signal PSCS1 to minimize the second current I2 to maximize efficiency. As a result, both the first output signal OS1 and the second output signal OS2 are regulated based on the power supply control input signal PSCIS to provide the appropriate power supply output signal PSOS.

FIG. 2 shows details of the second power supply circuit 14 illustrated in FIG. 1 according to one embodiment of the second power supply circuit 14. The second power supply circuit 14 illustrated in FIG. 2 is similar to the second power supply circuit 14 illustrated in FIG. 1, except the second power supply circuit 14 illustrated in FIG. 2 includes at least a first energy storage element 20, which is used to improve the efficiency of the second power supply circuit 14. Instead of providing power to the amplitude modulated load 18 by always using DC power from the DC supply DCSPLY, under certain conditions, the second power supply circuit 14 may be able to use the first energy storage element 20 to provide power to the amplitude modulated load 18, thereby increasing efficiency. Specifically, during the first operating mode, the first power supply circuit 12 may provide power to the first energy storage element 20 via the first output signal OS1, and during the second operating mode, the second power supply circuit 14 may provide power to the amplitude modulated load 18 via the second output signal OS2 from the first energy storage element 20. Further, during the first operating mode, the second power supply circuit 14 may prevent power from being provided from the first energy storage element 20 to the amplitude modulated load 18, and during the second operating mode the second power supply circuit 14 may prevent power from being provided to the first energy storage element 20 from the first power supply circuit 12.

The energy storage status signal ESSS provides status regarding the first energy storage element 20, such that by using the energy storage status signal ESSS and the power supply output signal PSOS, the control circuitry 16 can determine which operating mode to select for most efficient operation. In alternate embodiments of the second power supply circuit 14, multiple energy storage elements (not shown) may be used to store and provide power to further increase the efficiency of the second power supply circuit 14.

FIG. 3 shows details of the first power supply circuit 12 and the second power supply circuit 14 illustrated in FIG. 1 according to one embodiment of the first power supply circuit 12 and the second power supply circuit 14. The first power supply circuit 12 and the second power supply circuit 14 illustrated in FIG. 3 are similar to the first power supply circuit 12 and the second power supply circuit 14 illustrated in FIG. 1, except the first power supply circuit 12 and the second power supply circuit 14 illustrated in FIG. 3 include a switching power supply circuit 22 and a linear power supply circuit 24, respectively. Further, FIG. 3 shows the DC supply DCSPLY being provided by a battery 26 according to one embodiment of the present disclosure. The switching power supply circuit 22 receives the first power supply control signal PSCS1 and DC power from the DC supply DCSPLY, and provides the first output signal OS1 via a first output OUT1. The linear power supply circuit 24 includes at least the first energy storage element 20; receives the power supply control input signal PSCIS, DC power from the DC supply DCSPLY, and the mode select signal MSS; and provides the first power supply control signal PSCS1 and the energy storage status signal ESSS. Further, the linear power supply circuit 24 provides the second output signal OS2 via a second output OUT2. As such, the first output OUT1 and the second output OUT2 are coupled together to provide the power supply output signal PSOS.

In one embodiment of the switching power supply circuit 22 and the linear power supply circuit 24, the linear power supply circuit 24 regulates the second output signal OS2 using the power supply control input signal PSCIS, the linear power supply circuit 24 regulates the first power supply control signal PSCS1 to approximately minimize the second current I2, and the switching power supply circuit 22 regulates the first output signal OS1 using the first power supply control signal PSCS1. As a result, the switching power supply circuit 22 regulates the first output signal OS1 to approximately minimize the second current I2. Since regulating the second output signal OS2 using the power supply control input signal PSCIS uses the second current I2, and since the switching power supply circuit 22 regulates the first output signal OS1 to approximately minimize the second current I2, the switching power supply circuit 22 regulates the first output signal OS1 based on the power supply control input signal PSCIS.

An output bandwidth of the linear power supply circuit 24 and a modulation bandwidth of the amplitude modulated load 18 may both be wider than an output bandwidth of the switching power supply circuit 22. The switching power supply circuit 22 may provide efficient transfer of power from the DC supply DCSPLY to the amplitude modulated load 18. However, since the output bandwidth of the switching power supply circuit 22 may be narrower than the modulation bandwidth of the amplitude modulated load 18, the switching power supply circuit 22 may be unable to provide power to the amplitude modulated load 18 without significant levels of distortion. In this regard, since the output bandwidth of the linear power supply circuit 24 may be wider than the output bandwidth of the switching power supply circuit 22, the linear power supply circuit 24 may be able to supplement the switching power supply circuit 22 to provide power to the amplitude modulated load 18 with minimal distortion. However, since the linear power supply circuit 24 may provide power using series pass devices, efficiency may suffer. When the series pass devices are coupled to the DC supply DCSPLY or to ground, the resulting voltage drops across the series pass devices may be relatively large, thereby resulting in significant losses. However, when the series pass devices are coupled to the first energy storage element 20 instead of to the DC supply DCSPLY or to ground, the resulting voltage drops across the series pass devices may be significantly reduced, thereby improving efficiency. In general, the power to the amplitude modulated load 18 via the second output signal OS2 from the first energy storage element 20 may compensate for the output bandwidth of the switching power supply circuit 22.

FIG. 4 shows an amplitude-modulated RF power amplifier (PA) circuit 28, according to the prior art. AM is a modulation technique such that the amplitude of an RF carrier is modulated, which may be used to encode some kind of information. An AM baseband controller 30 provides an AM signal VAM to an AM modulation circuit 32. The AM signal VAM may provide an AM power supply input signal VAMPSI to an AM power supply 34, which provides an AM power supply output signal VAMPSO based on the AM power supply input signal VAMPSI. The AM modulation circuit 32 receives and amplitude-modulates an RF carrier signal RFCAR using the AM signal VAM to provide an AM RF input signal RFAM to a PA stage 36, which amplifies the AM RF input signal RFAM to provide an AM RF output signal RFAMOUT. The AM power supply output signal VAMPSO may provide power for amplification to the PA stage 36.

FIG. 5 shows the power supply circuitry 10 (FIG. 1) used in an amplitude-modulated RF PA circuit 38, according to one embodiment of the amplitude-modulated RF PA circuit 38. The AM baseband controller 30 provides the AM signal VAM to the AM modulation circuit 32. Further, the AM baseband controller 30 provides the power supply control input signal PSCIS to the power supply circuitry 10, which provides the power supply output signal PSOS based on the power supply control input signal PSCIS. The AM modulation circuit 32 receives and amplitude-modulates the RF carrier signal RFCAR using the AM signal VAM to provide the AM RF input signal RFAM to the PA stage 36, which is one example of the amplitude modulated load 18. The PA stage 36 amplifies the AM RF input signal RFAM to provide the AM RF output signal RFAMOUT. The power supply output signal PSOS may provide power for amplification to the PA stage 36. The power supply control input signal PSCIS may be based on the AM of the AM RF input signal RFAM. Alternate embodiments of the amplitude modulated load 18 may include at least one additional PA stage coupled in series with the PA stage 36.

FIG. 6 shows the power supply circuitry 10 (FIG. 1) used in a polar-modulated RF power amplifier circuit 40, according to one embodiment of the polar-modulated RF power amplifier circuit 40. Phase modulation (PM) is a modulation technique such that the phase of an RF carrier is modulated, which may be used to encode some kind of information. PM may be combined with AM to provide polar modulation, which may provide encoding of more information than either PM or AM alone. A polar modulation baseband controller 42 provides the AM signal VAM to the AM modulation circuit 32 and a PM signal VPM to a PM RF modulator 44, which phase-modulates an RF carrier signal (not shown) using the PM signal VPM to provide a PM RF signal RFPM to the AM modulation circuit 32. The polar modulation baseband controller 42 provides the power supply control input signal PSCIS to the power supply circuitry 10, which provides the power supply output signal PSOS based on the power supply control input signal PSCIS. The AM modulation circuit 32 receives and amplitude-modulates the PM RF signal RFPM using the AM signal VAM to provide a polar-modulated RF input signal RFAMPM to the PA stage 36, which amplifies the polar-modulated RF input signal RFAMPM to provide a polar-modulated RF output signal RFAMPMOUT. The power supply output signal PSOS may provide power for amplification to the PA stage 36. Generally, the polar-modulated RF input signal RFAMPM is one embodiment of the AM RF input signal RFAM and the polar-modulated RF output signal RFAMPMOUT is one embodiment of the AM RF output signal RFAMOUT. Alternate embodiments of the amplitude modulated load 18 may include at least one additional PA stage coupled in series with the PA stage 36.

FIG. 7 shows the power supply circuitry 10 (FIG. 1) used in a polar-modulated quadrature RF power amplifier circuit 46, according to one embodiment of the polar-modulated quadrature RF power amplifier circuit 46. The polar modulation baseband controller 42 provides the AM signal VAM to an in-phase AM modulation circuit 48 and a quadrature-phase AM modulation circuit 50, and provides the PM signal VPM to the PM RF modulator 44, which phase-modulates an RF carrier signal (not shown) using the PM signal VPM to provide an in-phase PM RF signal RFPMI to the in-phase AM modulation circuit 48 and a quadrature-phase PM RF signal RFPMQ to the quadrature-phase AM modulation circuit 50. The polar modulation baseband controller 42 provides the power supply control input signal PSCIS to the power supply circuitry 10, which provides the power supply output signal PSOS based on the power supply control input signal PSCIS.

The in-phase AM modulation circuit 48 receives and amplitude-modulates the in-phase PM RF signal RFPMI using the AM signal VAM to provide an in-phase polar-modulated RF input signal RFAMPMI to an in-phase PA stage 52, which amplifies the in-phase polar-modulated RF input signal RFAMPMI to provide an in-phase polar-modulated RF output signal RFOUTPI. The quadrature-phase AM modulation circuit 50 receives and amplitude-modulates the quadrature-phase PM RF signal RFPMQ using the AM signal VAM to provide a quadrature-phase polar-modulated RF input signal RFAMPMQ to a quadrature-phase PA stage 54, which amplifies the quadrature-phase polar-modulated RF input signal RFAMPMQ to provide a quadrature-phase polar-modulated RF output signal RFOUTPQ. The in-phase PA stage 52 and the quadrature-phase PA stage 54 together form one example of the amplitude modulated load 18. The power supply output signal PSOS may provide power for amplification to the in-phase PA stage 52 and the quadrature-phase PA stage 54. The in-phase PM RF signal RFPMI may be of about equal amplitude to and phase-shifted from the quadrature-phase PM RF signal RFPMQ by about 90 degrees.

Generally, the in-phase polar-modulated RF input signal RFAMPMI is one embodiment of an in-phase AM RF input signal (not shown), the quadrature-phase polar-modulated RF input signal RFAMPMQ is one embodiment of a quadrature-phase AM RF input signal (not shown), the in-phase polar-modulated RF output signal RFOUTPI is one embodiment of an in-phase AM RF output signal (not shown), and the quadrature-phase polar-modulated RF output signal RFOUTPQ is one embodiment of a quadrature-phase AM RF output signal (not shown). Further, the in-phase AM RF input signal and the quadrature-phase AM RF input signal together form one embodiment of the AM RF input signal RFAM, and the in-phase AM RF output signal and the quadrature-phase AM RF output signal together form one embodiment of the AM RF output signal RFAMOUT. Alternate embodiments of the amplitude modulated load 18 may include at least one additional PA stage coupled in series with the in-phase PA stage 52 and may include at least one additional PA stage coupled in series with the quadrature-phase PA stage 54.

FIG. 8 shows the power supply circuitry 10 illustrated in FIG. 3 according to an alternate embodiment of the power supply circuitry 10. The power supply circuitry 10 illustrated in FIG. 8 further includes a bypass capacitive element CB coupled between the first output OUT1 and ground and the switching power supply circuit 22 includes a multi-level charge-pump 56 and a buck switching power supply 58, which includes buck switching circuitry 60 and a first inductive element L1. The multi-level charge-pump 56 receives DC power from the DC supply DCSPLY and provides one of several possible output voltages to the buck switching circuitry 60. The first inductive element L1 is coupled between the buck switching circuitry 60 and the first output OUT1. The multi-level charge-pump 56 may provide a voltage to the buck switching circuitry 60 that is higher than, less than, or about equal to a DC voltage provided by the DC supply DCSPLY. A buck switching power supply is defined as a switching power supply that can provide an output voltage that is less than or equal to an input voltage. Therefore, the buck switching power supply 58 can provide an output voltage that is less than or equal to the voltage provided by the multi-level charge-pump 56. However, since the voltage provided by the multi-level charge-pump 56 may be higher than the DC voltage provided by the DC supply DCSPLY, the switching power supply circuit 22 may be a buck or boost switching power supply. Therefore, the buck switching power supply 58 receives DC power via the multi-level charge-pump 56 and the buck switching power supply 58 provides the first output signal OS1 based on the DC power from the DC supply DCSPLY.

The first inductive element L1 may be the only energy conversion inductive element in the switching power supply circuit 22. Since the first inductive element L1 is coupled between the buck switching circuitry 60 and the first output OUT1, the first inductive element L1 provides the first current I1. However, the ability of the switching power supply circuit 22 to provide rapid changes in the first current I1 is limited by a slew rate of the current, which is the first current I1, in the first inductive element L1. The slew rate is given by d(I1)/dt. As such, if an inductance of the first inductive element L1 is represented as L and a voltage across the first inductive element L1 is represented as V, then the slew rate is given by EQ. 1.
Slew Rate=d(I1)/dt=V/L.  EQ. 1

By examining EQ. 1, the slew rate is proportional to the voltage V across the first inductive element L1. Therefore, by having boost capability, the available voltage V is higher, which allows for a higher slew rate, thereby increasing an effective bandwidth of the switching power supply circuit 22 and decreasing the second current I2. Alternate embodiments of the switching power supply circuit 22 may not be capable of boost operation, may omit the multi-level charge-pump 56, or both.

The bypass capacitive element CB has a bypass current IB. The combination of the first inductive element L1 and the bypass capacitive element CB filters switching effects of the buck switching circuitry 60, thereby smoothing the first output signal OS1. However, the first inductive element L1 and the bypass capacitive element CB also limit the bandwidth of the switching power supply circuit 22. Therefore, there is a trade-off between the filtering benefits and the bandwidth limitations. Ideally, an output impedance from the linear power supply circuit 24 would be zero. However, since the linear power supply circuit 24 has a finite output impedance, the bypass capacitive element CB also limit the bandwidth of the linear power supply circuit 24.

The amplitude modulated load 18 has a load current IL, which is typically amplitude modulated. As such, according to Kirchhoff's Current Law, the sum of the first current I1 and the second current I2 are equal to the sum of the load current IL and the bypass current IB. The first current I1 and the bypass current IB work together to provide the amplitude modulated load current IL. However, any bandwidth shortcomings of the switching power supply circuit 22 may cause a shortfall in the first current I1 and the bypass current IB working together to provide the amplitude modulated load current IL. As a result, the second current I2 makes up the difference for the bandwidth shortcomings of the switching power supply circuit 22.

FIG. 9 is a graph showing the first current I1, the second current I2, the load current IL, and the bypass current IB illustrated in FIG. 8 according to one embodiment of the power supply circuitry 10. FIG. 9 illustrates the role of the second current I2 in providing the load current IL. When the load current IL is rapidly changing, the slew rate limitations of the first current I1 limit the ability of the first current I1 to provide all of the load current IL. Since the linear power supply circuit 24 operates to keep the voltage of the second output signal OS2 in line with a desired voltage of the power supply output signal PSOS, the second current I2 makes up the difference.

FIG. 10 shows details of the linear power supply circuit 24 and the control circuitry 16 illustrated in FIG. 8 according to one embodiment of the linear power supply circuit 24 and the control circuitry 16. The control circuitry 16 includes a high side mode select circuit 62 and a low side mode select circuit 64. The linear power supply circuit 24 includes a high side differential amplifier 66, a low side differential amplifier 68, a first high side linear transistor element 70, a second high side linear transistor element 72, a first low side linear transistor element 74, a second low side linear transistor element 76, a switching setpoint circuit 78, a first resistive element R1, a second resistive element R2, a first capacitive element C1, and a second capacitive element C2. The first energy storage element 20 includes a third capacitive element C3. Alternate embodiments of the linear power supply circuit 24 may include additional storage elements (not shown) coupled together in any manner to the first energy storage element 20

Inverting inputs of the high side differential amplifier 66 and the low side differential amplifier 68 receive the power supply control input signal PSCIS and non-inverting inputs of the high side differential amplifier 66 and the low side differential amplifier 68 are coupled to the second output OUT2 to receive the second output signal OS2 (FIG. 8). The first resistive element R1 and the first capacitive element C1 are coupled in series between the non-inverting input of the high side differential amplifier 66 and an output of the high side differential amplifier 66 to provide feedback for proper operation of the high side differential amplifier 66. Similarly, the second resistive element R2 and the second capacitive element C2 are coupled in series between the non-inverting input and an output of the low side differential amplifier 68 to provide feedback for proper operation of the low side differential amplifier 68. The high side differential amplifier 66 provides a high side amplifier output signal HSAOS to the high side mode select circuit 62 based on a difference between the power supply control input signal PSCIS and the second output signal OS2 (FIG. 8). Similarly, the low side differential amplifier 68 provides a low side amplifier output signal LSAOS to the low side mode select circuit 64 based on a difference between the power supply control input signal PSCIS and the second output signal OS2 (FIG. 8).

The first high side linear transistor element 70 and the second high side linear transistor element 72 may be P-type metal-oxide-semiconductor (PMOS) transistor elements and the first low side linear transistor element 74 and the second low side linear transistor element 76 may be N-type metal-oxide-semiconductor (NMOS) transistor elements. The high side mode select circuit 62 provides a first high side control signal HS1 to an input, which may be a gate, to the first high side linear transistor element 70 and provides a second high side control signal HS2 to an input, which may be a gate, to the second high side linear transistor element 72. The low side mode select circuit 64 provides a first low side control signal LS1 to an input, which may be a gate, to the first low side linear transistor element 74 and a second low side control signal LS2 to an input, which may be a gate, to the second low side linear transistor element 76.

A non-inverting output, which may be a source, of the first high side linear transistor element 70 may receive DC power from the DC supply DCSPLY. A non-inverting output, which may be a source, of the first low side linear transistor element 74 is coupled to ground. Non-inverting outputs, which may be sources, of the second high side linear transistor element 72 and the second low side linear transistor element 76 are coupled together. The first energy storage element 20 is coupled between ground and the non-inverting outputs of the second linear transistor elements 72, 76. Specifically, the third capacitive element C3 is coupled between ground and the non-inverting outputs of the second linear transistor elements 72, 76. The non-inverting outputs of the second linear transistor elements 72, 76 provide the energy storage status signal ESSS to the high side mode select circuit 62 and the low side mode select circuit 64. Inverting outputs, which may be drains, of the linear transistor elements 70, 72, 74, 76 are coupled together and coupled to the second output OUT2. Alternate embodiments of the linear transistor elements 70, 72, 74, 76 may include bipolar transistor elements (not shown).

As previously mentioned, the control circuitry 16 selects one of multiple operating modes. Depending on which operating mode is selected, either the first high side linear transistor element 70 or the second high side linear transistor element 72 is biased off and the high side linear transistor element 70, 72 that is not biased off is available to provide amplification. Similarly, depending on which operating mode is selected, either the first low side linear transistor element 74 or the second low side linear transistor element 76 is biased off and the low side linear transistor element 74, 76 that is not biased off is available to provide amplification. For example, when the operating mode is selected such that the first high side linear transistor element 70 is biased off, the first high side control signal HS1 biases the first high side linear transistor element 70 off and the second high side control signal HS2 is based on the high side amplifier output signal HSAOS, such that the second high side linear transistor element 72 can provide amplification. As such, the second high side control signal HS2 may be about equivalent to the high side amplifier output signal HSAOS.

When the operating mode is selected such that the second high side linear transistor element 72 is biased off, the second high side control signal HS2 biases the second high side linear transistor element 72 off and the first high side control signal HS1 is based on the high side amplifier output signal HSAOS. As such, the first high side control signal HS1 may be about equivalent to the high side amplifier output signal HSAOS. When the operating mode is selected such that the first low side linear transistor element 74 is biased off, the first low side control signal LS1 biases the first low side linear transistor element 74 off and the second low side control signal LS2 is based on the low side amplifier output signal LSAOS, such that the second low side linear transistor element 76 can provide amplification. As such, the second low side control signal LS2 may be about equivalent to the low side amplifier output signal LSAOS. When the operating mode is selected such that the second low side linear transistor element 76 is biased off, the second low side control signal LS2 biases the second low side linear transistor element 76 off and the first low side control signal LS1 is based on the low side amplifier output signal LSAOS. As such, the first low side control signal LS1 may be about equivalent to the low side amplifier output signal LSAOS.

Normally, the voltage across the third capacitive element C3 falls somewhere between the voltage provided by the DC supply DCSPLY and ground. Therefore, the voltage drop across the second high side linear transistor element 72 when the second high side linear transistor element 72 is used to provide amplification is less than the voltage drop across the first high side linear transistor element 70 when the first high side linear transistor element 70 is used to provide amplification, thereby reducing power loss in the linear power supply circuit 24 and increasing efficiency. Similarly, the voltage drop across the second low side linear transistor element 76 when the second low side linear transistor element 76 is used to provide amplification is less than the voltage across the first low side linear transistor element 74 when the first low side linear transistor element 74 is used to provide amplification, thereby reducing power loss in the linear power supply circuit 24 and increasing efficiency. As a result, the third capacitive element C3 increases efficiency by storing energy when the second low side linear transistor element 76 is used to provide amplification and by providing energy when the second high side linear transistor element 72 is used to provide amplification. In summary, the stored energy reduces the voltage drops across the linear transistor elements that are used to provide the second output signal OS2 (FIG. 8).

During the first operating mode, the first high side linear transistor element 70 is available to provide amplification, the second high side linear transistor element 72 is biased off, the first low side linear transistor element 74 is biased off, and the second low side linear transistor element 76 is available to provide amplification. The control circuitry 16 selects the first operating mode when the voltage of the second output signal OS2 (FIG. 8) is positive with respect to the voltage of the energy storage status signal ESSS and when the voltage across the second low side linear transistor element 76 is greater than a first threshold, such that the second low side linear transistor element 76 has sufficient headroom for proper operation. Therefore, the first energy storage element 20, and specifically, the third capacitive element C3 may receive power from the switching power supply circuit 22 (FIG. 8) via the first output signal OS1 (FIG. 8).

During the second operating mode, the first high side linear transistor element 70 is biased off, the second high side linear transistor element 72 is available to provide amplification, the first low side linear transistor element 74 is available to provide amplification, and the second low side linear transistor element 76 is biased off. The control circuitry 16 selects the second operating mode when the voltage of the second output signal OS2 (FIG. 8) is negative with respect to the voltage of the energy storage status signal ESSS and when the voltage across the second high side linear transistor element 72 is greater than a second threshold, such that the second high side linear transistor element 72 has sufficient headroom for proper operation. Therefore, first energy storage element 20, and specifically, the third capacitive element C3 may provide power to the amplitude modulated load 18 (FIG. 8) via the second output signal OS2 (FIG. 8).

The multiple operating modes may further include a third operating mode, such that during the third operating mode, the first high side linear transistor element 70 is available to provide amplification, the second high side linear transistor element 72 is biased off, the first low side linear transistor element 74 is available to provide amplification, and the second low side linear transistor element 76 is biased off. As such, the first energy storage element 20, and specifically, the third capacitive element C3 neither provides nor receives power. The control circuitry 16 selects the third operating mode when the voltage of the energy storage status signal ESSS is such that neither the first operating mode nor the second operating mode can be selected.

The second output OUT2 is coupled to the high side mode select circuit 62 and the low side mode select circuit 64. As such, the high side mode select circuit 62 may sense currents through the first high side linear transistor element 70 and the second high side linear transistor element 72 by using a current sense technique, such as current mirroring. As a result, the high side mode select circuit 62 provides a high side current sense signal HSCSS to the switching setpoint circuit 78 based on the sensed currents through the first high side linear transistor element 70 and the second high side linear transistor element 72. Similarly, the low side mode select circuit 64 may sense currents through the first low side linear transistor element 74 and the second low side linear transistor element 76 by using a current sense technique, such as current mirroring. As a result, the low side mode select circuit 64 provides a low side current sense signal LSCSS to the switching setpoint circuit 78 based on the sensed currents through the first low side linear transistor element 74 and the second low side linear transistor element 76. Since the second current I2 (FIG. 8) is based on the currents through the linear transistor elements 70, 72, 74, 76; the switching setpoint circuit 78 may sense the second current I2 (FIG. 8) based on the low side current sense signal LSCSS and the high side current sense signal HSCSS. The switching setpoint circuit 78 provides the first power supply control signal PSCS1 based on the sensed second current.

The switching setpoint circuit 78 may regulate the switching power supply circuit 22 via the first power supply control signal PSCS1 to minimize the sensed second current to minimize the second current I2 (FIG. 8). Further, the high side differential amplifier 66, the low side differential amplifier 68, and the linear transistor elements 70, 72, 74, 76 may regulate the linear power supply circuit 24 to minimize a voltage difference between the second output signal OS2 (FIG. 8) and the power supply control input signal PSCIS.

FIG. 11 shows details of the linear power supply circuit 24 and the control circuitry 16 illustrated in FIG. 8 according to an alternate embodiment of the linear power supply circuit 24 and the control circuitry 16. The linear power supply circuit 24 and the control circuitry 16 illustrated in FIG. 11 is similar to the linear power supply circuit 24 and the control circuitry 16 illustrated in FIG. 10, except the linear power supply circuit 24 illustrated in FIG. 11 further includes an output impedance compensation circuit 80. Ideally, the output impedance from the linear power supply circuit 24 would be zero, such that the linear power supply circuit 24 could perfectly regulate the second output signal OS2 (FIG. 8) to match the power supply control input signal PSCIS. However, the output impedance from the linear power supply circuit 24 is not zero. As such, an error is introduced into the regulation of the second output signal OS2 (FIG. 8). The output impedance compensation circuit 80 compensates for this error based on an estimate of the bypass current IB (FIG. 8) and sensing the second current I2 (FIG. 8).

As previously mentioned, the switching setpoint circuit 78 may sense the second current I2 (FIG. 8) based on the low side current sense signal LSCSS and the high side current sense signal HSCSS. Similarly, the output impedance compensation circuit 80 receives the low side current sense signal LSCSS and the high side current sense signal HSCSS and senses the second current I2 (FIG. 8) based on the low side current sense signal LSCSS and the high side current sense signal HSCSS. Further, the output impedance compensation circuit 80 may estimate the bypass current IB (FIG. 8) based on a capacitance of the bypass capacitive element CB and the power supply control input signal PSCIS.

Instead of the high side differential amplifier 66 and the low side differential amplifier 68 receiving the power supply control input signal PSCIS directly as was illustrated in FIG. 10, the output impedance compensation circuit 80 receives the power supply control input signal PSCIS and provides a compensated power supply control input signal CPSCIS to the high side differential amplifier 66 and the low side differential amplifier 68 based on compensating the power supply control input signal PSCIS. The compensated power supply control input signal CPSCIS may be based on the estimated bypass current and the sensed second current.

In an exemplary embodiment of the compensated power supply control input signal CPSCIS, the compensated power supply control input signal CPSCIS is about equal to a sum of a voltage of the power supply control input signal PSCIS and a correction voltage, such that the correction voltage is about equal to a correction inductance times a derivative with respect to time of a difference between the estimated bypass current and the sensed second current. The correction inductance is a correction factor that converts the derivative with respect to time of the difference between the estimated bypass current and the sensed second current into a voltage. The estimated bypass current may be about equal to an estimated capacitance of the bypass capacitive element CB (FIG. 8) times a derivative with respect to time of the voltage of the power supply control input signal PSCIS.

FIG. 12 shows details of the linear power supply circuit 24 and the control circuitry 16 illustrated in FIG. 8 according to an additional embodiment of the linear power supply circuit 24 and the control circuitry 16.

The linear power supply circuit 24 and the control circuitry 16 illustrated in FIG. 12 is similar to the linear power supply circuit 24 and the control circuitry 16 illustrated in FIG. 11, except the linear power supply circuit 24 illustrated in FIG. 12 further includes a offset capacitive element COS and an offset sense circuit 82. Instead of the inverting outputs of the linear transistor elements 70, 72, 74, 76 and the high side mode select circuit 62 and the low side mode select circuit 64 being coupled together and coupled to the second output OUT2 as illustrated in FIG. 11, the offset capacitive element COS is coupled between the second output OUT2 and the coupling of the inverting outputs of the linear transistor elements 70, 72, 74, 76, the high side mode select circuit 62, and low side mode select circuit 64. The offset sense circuit 82 is coupled across the offset capacitive element COS to sense the voltage across the offset capacitive element COS. The offset sense circuit 82 provides an offset sense signal OSS to the switching setpoint circuit 78 based on the voltage across the offset capacitive element COS.

Since the first high side linear transistor element 70 receives DC power from the DC supply DCSPLY and since the switching power supply circuit 22 may be capable of providing output voltages greater than the voltage provided by the DC supply DCSPLY, the first high side linear transistor element 70 may have insufficient headroom to provide the second output signal OS2 (FIG. 8) as needed. Therefore, by adding the offset capacitive element COS, the switching power supply circuit 22 can provide an offset voltage across the offset capacitive element COS to allow the first high side linear transistor element 70 to function properly. To provide the proper offset voltage, the offset sense circuit 82 senses the offset voltage and provides the offset sense signal OSS, which is indicative of the offset voltage. The switching setpoint circuit 78 may further regulate the switching power supply circuit 22 via the first power supply control signal PSCS1 to provide a desired offset voltage based on the offset sense signal OSS.

During the first operating mode, the first high side linear transistor element 70 is available to provide amplification, the second high side linear transistor element 72 is biased off, the first low side linear transistor element 74 is biased off, and the second low side linear transistor element 76 is available to provide amplification. The control circuitry 16 selects the first operating mode when the voltage at the inverting outputs of the linear transistor elements 70, 72, 74, 76 is positive with respect to the voltage of the energy storage status signal ESSS and when the voltage across the second low side linear transistor element 76 is greater than the first threshold, such that the second low side linear transistor element 76 has sufficient headroom for proper operation. Therefore, the first energy storage element 20, and specifically, the third capacitive element C3 may receive power from the switching power supply circuit 22 (FIG. 8) via the first output signal OS1 (FIG. 8).

During the second operating mode, the first high side linear transistor element 70 is biased off, the second high side linear transistor element 72 is available to provide amplification, the first low side linear transistor element 74 is available to provide amplification, and the second low side linear transistor element 76 is biased off. The control circuitry 16 selects the second operating mode when the voltage at the inverting outputs of the linear transistor elements 70, 72, 74, 76 is negative with respect to the voltage of the energy storage status signal ESSS and when the voltage across the second high side linear transistor element 72 is greater than the second threshold, such that the second high side linear transistor element 72 has sufficient headroom for proper operation. Therefore, the first energy storage element 20, and specifically, the third capacitive element C3 may provide power to the amplitude modulated load 18 (FIG. 8) via the second output signal OS2 (FIG. 8).

During the third operating mode, the first high side linear transistor element 70 is available to provide amplification, the second high side linear transistor element 72 is biased off, the first low side linear transistor element 74 is available to provide amplification, and the second low side linear transistor element 76 is biased off. As such, the first energy storage element 20, and specifically, the third capacitive element C3 neither provides nor receives power. The control circuitry 16 selects the third operating mode when the voltage of the energy storage status signal ESSS is such that neither the first operating mode nor the second operating mode can be selected.

FIG. 13 shows details of the linear power supply circuit 24 and the control circuitry 16 illustrated in FIG. 8 according to another embodiment of the linear power supply circuit 24 and the control circuitry 16. The linear power supply circuit 24 and the control circuitry 16 illustrated in FIG. 13 is similar to the linear power supply circuit 24 and the control circuitry 16 illustrated in FIG. 12, except in the linear power supply circuit 24 illustrated in FIG. 13, the inverting output of the second low side linear transistor element 76 is coupled to the second output OUT2 instead of to the inverting outputs of the other linear transistor elements 70, 72, 74. By coupling to the second output OUT2, the inverting output of the second low side linear transistor element 76 has a higher voltage, thereby increasing the voltage that is available to charge the third capacitive element C3. As a result, the linear power supply circuit 24 may operate in the first and second operating modes more often, with a higher duration, or both, thereby increasing efficiency.

During the first operating mode, the first high side linear transistor element 70 is available to provide amplification, the second high side linear transistor element 72 is biased off, the first low side linear transistor element 74 is biased off, and the second low side linear transistor element 76 is available to provide amplification. The control circuitry 16 selects the first operating mode when the voltage at the second output OUT2 is positive with respect to the voltage of the energy storage status signal ESSS and when the voltage across the second low side linear transistor element 76 is greater than the first threshold, such that the second low side linear transistor element 76 has sufficient headroom for proper operation. Therefore, the first energy storage element 20, and specifically, the third capacitive element C3 may receive power from the switching power supply circuit 22 (FIG. 8) via the first output signal OS1 (FIG. 8).

During the second operating mode, the first high side linear transistor element 70 is biased off, the second high side linear transistor element 72 is available to provide amplification, the first low side linear transistor element 74 is available to provide amplification, and the second low side linear transistor element 76 is biased off. The control circuitry 16 selects the second operating mode when the voltage at the inverting outputs of the linear transistor elements 70, 72, 74, 76 is negative with respect to the voltage of the energy storage status signal ESSS and when the voltage across the second high side linear transistor element 72 is greater than the second threshold, such that the second high side linear transistor element 72 has sufficient headroom for proper operation. Therefore, the first energy storage element 20, and specifically, the third capacitive element C3 may provide power to the amplitude modulated load 18 (FIG. 8) via the second output signal OS2 (FIG. 8).

During the third operating mode, the first high side linear transistor element 70 is available to provide amplification, the second high side linear transistor element 72 is biased off, the first low side linear transistor element 74 is available to provide amplification, and the second low side linear transistor element 76 is biased off. As such, the first energy storage element 20, and specifically, the third capacitive element C3 neither provides nor receives power. The control circuitry 16 selects the third operating mode when the voltage of the energy storage status signal ESSS is such that neither the first operating mode nor the second operating mode can be selected.

FIG. 14 shows details of the linear power supply circuit 24 and the control circuitry 16 illustrated in FIG. 8 according to a supplemental embodiment of the linear power supply circuit 24 and the control circuitry 16.

The linear power supply circuit 24 and the control circuitry 16 illustrated in FIG. 14 is similar to the linear power supply circuit 24 and the control circuitry 16 illustrated in FIG. 10, except in the linear power supply circuit 24 illustrated in FIG. 14, the second high side linear transistor element 72 and the second low side linear transistor element 76 are omitted; and the linear power supply circuit 24 further includes a first high side switching element 84, a second high side switching element 86, a first low side switching element 88, and a second low side switching element 90. The first high side switching element 84 may be a PMOS switching transistor element and the second high side switching element 86 may be a PMOS switching transistor element. The first low side switching element 88 may be an NMOS switching transistor element and the second low side switching element 90 may be an NMOS switching transistor element.

The high side mode select circuit 62 provides the second high side control signal HS2 to an input, which may be a gate, to the first high side switching element 84 and provides a third high side control signal HS3 to an input, which may be a gate, to the second high side switching element 86. The first high side switching element 84 and the second high side switching element 86 may each operate in either an OPEN state or a CLOSED state. Selection of either the OPEN state or the CLOSED state is based on the second high side control signal HS2 for the first high side switching element 84 and is based on the third high side control signal HS3 for the second high side switching element 86.

The low side mode select circuit 64 provides the second low side control signal LS2 to an input, which may be a gate, to the first low side switching element 88 and provides a third low side control signal LS3 to an input, which may be a gate, to the second low side switching element 90. The second high side switching element 86 and the first low side switching element 88 may each operate in either an OPEN state or a CLOSED state. Selection of either the OPEN state or the CLOSED state is based on the second low side control signal LS2 for the first low side switching element 88 and is based on the third low side control signal LS3 for the second low side switching element 90.

As previously mentioned, the control circuitry 16 selects one of multiple operating modes. The high side mode select circuit 62 provides the second high side control signal HS2 and the third high side control signal HS3 based on which of the multiple operating modes is selected. Similarly, the low side mode select circuit 64 provides the second low side control signal LS2 and the third low side control signal LS3 based on which of the multiple operating modes is selected.

A first switching terminal, which may be a source, of the first high side switching element 84 receives DC power from the DC supply DCSPLY. A first switching terminal, which may be a source, of the second high side switching element 86 is coupled to a first switching terminal, which may be a source, of the second low side switching element 90. The first energy storage element 20, and specifically, the third capacitive element C3 is coupled between ground and the first switching terminals of the second switching elements 86, 90. Additionally, the first switching terminals of the second switching elements 86, 90 provide the energy storage status signal ESSS to the high side mode select circuit 62 and the low side mode select circuit 64. A first switching terminal, which may be a source, of the first low side switching element 88 is coupled to ground.

Instead of the non-inverting output of the first high side linear transistor element 70 receiving DC power from the DC supply DCSPLY as illustrated in FIG. 10, the non-inverting output of the first high side linear transistor element 70 is coupled to second switching terminals, which may be drains, of the first high side switching element 84 and the second high side switching element 86. Instead of the non-inverting output of the first low side linear transistor element 74 being coupled to ground as illustrated in FIG. 10, the non-inverting output of the first low side linear transistor element 74 is coupled to second switching terminals, which may be drains, of the first low side switching element 88 and the second low side switching element 90.

Normally, the first high side linear transistor element 70 and the first low side linear transistor element 74 are available to provide amplification regardless of which operating mode is selected. Normally, only one of the first high side switching element 84 and the second high side switching element 86 is in the CLOSED state. Similarly, normally only one of the first low side switching element 88 and the second low side switching element 90 is in the CLOSED state. As such, when the first high side switching element 84 is in the CLOSED state and the second high side switching element 86 is in the OPEN state, the first high side switching element 84 electrically couples the non-inverting output of the first high side linear transistor element 70 to the DC supply DCSPLY to receive DC power. When the first high side switching element 84 is in the OPEN state and the second high side switching element 86 is in the CLOSED state, the second high side switching element 86 electrically couples the non-inverting output of the first high side linear transistor element 70 to the first energy storage element 20, and specifically, to the third capacitive element C3 to receive power from the third capacitive element C3.

When the first low side switching element 88 is in the CLOSED state and the second low side switching element 90 is in the OPEN state, the first low side switching element 88 electrically couples the non-inverting output of the first low side linear transistor element 74 to ground. When the first low side switching element 88 is in the OPEN state and the second low side switching element 90 is in the CLOSED state, the second low side switching element 90 electrically couples the non-inverting output of the first low side linear transistor element 74 to the first energy storage element 20, and specifically, to the third capacitive element C3 to provide power to the third capacitive element C3.

In this regard, during the first operating mode, the first high side switching element 84 is in the CLOSED state, the second high side switching element 86 is in the OPEN state, the first low side switching element 88 is in the OPEN state, and the second low side switching element 90 is in the CLOSED state. During the second operating mode, the first high side switching element 84 is in the OPEN state, the second high side switching element 86 is in the CLOSED state, the first low side switching element 88 is in the CLOSED state, and the second low side switching element 90 is in the CLOSED state. During the third operating mode, the first high side switching element 84 is in the CLOSED state, the second high side switching element 86 is in the OPEN state, the first low side switching element 88 is in the CLOSED state, and the second low side switching element 90 is in the OPEN state.

None of the embodiments of the present disclosure are intended to limit the scope of any other embodiment of the present disclosure. Any or all of any embodiment of the present disclosure may be combined with any or all of any other embodiment of the present disclosure to create new embodiments of the present disclosure.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.