Variable minimum input voltage based switching in an electronic power control system

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. §119(e) and 37 C.F.R. §1.78 of U.S. Provisional Application No. 61/372,527 filed on Aug. 11, 2010, and entitled “Dynamic Light Load Switching Disable,” and is incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to the field of electronics, and more specifically to a method and system for variable minimum input voltage based switching in an electronic power control system to, for example, reduce switching related losses.

2. Description of the Related Art

Power control systems often utilize a switching power converter to convert alternating current (AC) voltages to direct current (DC) voltages or DC-to-DC. Switching power converters provide power factor corrected and regulated output voltages to many devices that utilize a regulated output voltage. Exemplary devices that utilize a regulated output voltage include lamps, such as light emitting diode and gas discharge type lamps, cellular telephones, computing devices, personal digital assistants, and power supplies.

FIG. 1 depicts an electronic power control system 100 that includes a controller 102 that controls the operation of, and, thus, the delivery of power by switching power converter 104. Voltage source 106 supplies an alternating current (AC) input voltage V_IN to a full bridge diode rectifier 108. The voltage source 106 is, for example, a public utility, and the AC voltage V_IN is, for example, a 60 Hz/110 V line voltage in the United States of America or a 50 Hz/220 V line voltage in Europe. The full bridge rectifier 108 supplies a rectified AC voltage V_X to the switching power converter 104. Capacitor 110 filters high frequency components from rectified voltage V_X.

To control the operation of switching power converter 104, controller 102 generates the control signal CS₀ to control conductivity of field effect transistor (FET) switch 124. The control signal CS₀ is a pulse width modulated signal. Control signal CS₀ generally has a frequency within a range of 20 kHz to 100 kHz. Each pulse of control signal CS₀ turns switch 124 ON (i.e. conducts), and the inductor current i_L energizes inductor 126. Diode 128 prevents current flow from link capacitor 130 into switch 124. When the pulse ends, the inductor 126 reverses voltage polarity (commonly referred to as “flyback”) and the inductor current i_L charges link capacitor 130 through diode 111. The switching power converter 104 is a boost-type converter because the link voltage V_LINK is greater than the rectified input voltage V_X. Controller 102 operates the switching power converter 104 to maintain an approximately constant link voltage V_LINK for load 132 and provide power factor correction. Load 132 can be any type of load that utilizes the link voltage, such as lamps, such as light emitting diode and gas discharge type lamps, cellular telephones, computing devices, personal digital assistants, and power supplies.

To control operation of switching power converter 104, controller 102 monitors a sense signal V_X—SENSE, which represents the rectified voltage V_X, and monitors a sense signal V_LINK—SENSE, which represents the link voltage V_LINK. Controller 102 uses the sense signals V_X—SENSE and V_LINK—SENSE to generate the control signal CS₀ using well-known control circuitry.

FIG. 2 depicts exemplary signal waveforms 200, which are associated with electronic power control system 100. The signal waveforms 200 are the rectified input voltage V_X and control signal CS_0A. Control signal CS_0A represents two exemplary cycles 202 and 204 of the control signal CS₀ in FIG. 1. Referring to FIGS. 1 and 2, since each cycle 202 and 204 of input voltage V_X is one-half of the original cycle of the input supply voltage V_IN, each full cycle 202 and 204 of input voltage V_X spans from 0° to 180° of the rectified input voltage V_X. In one embodiment, when controlling switching power converter 104, controller 102 continuously generates the control signal CS_0A for the full 0°-180° of each cycle, including cycles 202 and 204, of input voltage V_X.

FIG. 3 depicts exemplary signal waveforms 300, which are associated with electronic power control system 100. The signal waveforms 300 are the utilized portion V_X—USED of the rectified input voltage V_X and control signal CS_0B. Control signal CS_0B represents two exemplary cycles 302 and 304 of the control signal CS₀ in FIG. 1. Referring to FIGS. 1 and 3, when controlling switching power converter 104, controller 102 generates the control signal CS_0B only when the input voltage V_X is greater than a static, minimum line voltage V_{LINE—MIN—STATIC}. In at least one embodiment, generating pulses of control signal CS_B only when the line voltage V_X is greater than the minimum line voltage V_LINE—MIN facilitates a simpler calculation of the duration for each pulse width of control signal CS_0B. The minimum line voltage V_{LINE—MIN—STATIC} is, thus, static and is set to facilitate the simpler calculations. The minimum line voltage V_{LINE—MIN—STATIC} corresponds to the first and last 5° of the input voltage V_X, i.e. V_{LINE—MIN—STATIC} corresponds to 5° and 175° of V_X. Thus, controller 102 does not generate the control signal CS_B for the first and last 5° of the input voltage V_X.

Referring to FIGS. 2 and 3, generating control signal CS_0A continuously allows switching power converter 104 to deliver full power to load 132 and facilitates accurate power factor correction. However, control signal CS_0A incurs switching losses throughout the entire cycle of each cycle of input voltage V_X. Switching losses are incurred, for example, by charging and discharging parasitic capacitances associated with switch 124. Generating control signal CS_0B using the static, minimum line voltage V_{LINE—MIN—STATIC} reduces switching losses of switch 124 by eliminating the switching losses that would otherwise be incurred when the controller 102 stops generating control signal CS_B, e.g. for the first and last 5° of the input voltage V_X. However, the intermittent generation of control signal CS_0B causes harmonic distortion when the current i_L is not proportional to the input voltage V_X. Because of the abrupt restarts of control signal CS_0B during the first and last 5° of each cycle of the input voltage V_X, the input voltage V_X is not proportional to the current i_L during the first and last 5° of each cycle of the input voltage V_X. Maximum total harmonic distortion of a load on a public voltage distribution systems, such as an embodiment of voltage source 106, is often regulated, such as by the IEC61000-3-2 specification of the International Engineering Consortium. The IEC61000-3-2 specification specifies limits for harmonic current emissions applicable to electrical and electronic equipment having an input current up to and including 16 A per phase and intended to be connected to public low-voltage distribution systems.”

SUMMARY OF THE INVENTION

In one embodiment of the present invention, a method includes sensing a link voltage to a switching power converter of an electronic system. The link voltage is a voltage provided to a load coupled to the switching power converter. The method further includes dynamically determining power utilization of a load coupled to the switching power converter using the sensed link voltage. The method also includes causing the switching power converter to cease converting power during a first portion of a cycle of an input voltage to the switching power converter when one or more operating parameters of the electronic system indicates that power from a second portion of the cycle of the input voltage is sufficient to meet a power demand of the load. The method additionally includes causing the switching power converter to convert power during the remaining portion of each cycle of the input voltage.

In another embodiment of the present invention, a method includes determining power utilization of a load coupled to a switching power converter. The method also includes generating a switch control signal to control the switching power converter when an input voltage to the switching power converter is greater than a threshold value. The threshold value is based on power utilization of a load. The method further includes disabling generation of the switch control signal when the input voltage to the switching power converter is less than the threshold value.

In a further embodiment of the present invention, an apparatus includes a controller having an input to sense a link voltage to a switching power converter of an electronic system. The link voltage is a voltage provided to a load coupled to the switching power converter. The controller is configured to at least dynamically determine power utilization of a load coupled to the switching power converter using the sensed link voltage. The controller is also configured to at least cause the switching power converter to cease converting power during a first portion of a cycle of an input voltage to the switching power converter when one or more operating parameters of the electronic system indicates that power from a second portion of the cycle of the input voltage is sufficient to meet a power demand of the load. The controller is further configured to at least cause the switching power converter to convert power during the remaining portion of each cycle of the input voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the several figures designates a like or similar element.

FIG. 1 (labeled prior art) depicts an electronic power control system with continuous monitoring of input and link voltages by a controller.

FIG. 2 (labeled prior art) depicts a set of exemplary signal waveforms, which are associated with electronic power control system of FIG. 1.

FIG. 3 (labeled prior art) depicts another set of exemplary signal waveforms, which are associated with electronic power control system of FIG. 1.

FIG. 4 depicts an electronic power control system that dynamically determines a minimum line voltage switching threshold based on power utilization of a load.

FIG. 5 depicts exemplary signals associated with the electronic power control system of FIG. 4.

FIG. 6 depicts an exemplary control signal generator for the electronic power control system of FIG. 4.

FIG. 7 depicts a voltage threshold related parameter relationships associated with generating the minimum line voltage switching threshold.

FIG. 8 depicts an exemplary load-based power utilization threshold generator of the control signal generator of FIG. 6.

DETAILED DESCRIPTION

An electronic system includes a controller that controls switching in a switching power converter in accordance with a dynamically determined, minimum line voltage switching threshold based on one or more operating parameters of the electronic system. In at least one embodiment, the one or more operating parameters of the electronic system include power utilization of a load. The controller utilizes the dynamically determined, minimum line voltage switching threshold to determine when to enable and disable switching in the switching power converter. Since the controller bases determination of the dynamically determined, minimum line voltage switching threshold on power utilization of the load, the controller operates more efficiently by reducing switching losses while still meeting power demand by the load. For example, in at least one embodiment, when the power utilization of the load decreases, the controller increases the dynamically determined, minimum line voltage switching threshold and, thus, disables switching in the switching power converter for a longer amount of time. In at least one embodiment, when the power utilization of the load increases, the controller lowers the dynamically determined, minimum line voltage switching threshold and, thus, disables switching in the switching power converter for a shorter amount of time.

In at least one embodiment, the term “dynamically determine” is used herein to indicate that a value or values is determined based on one or more other values that can change over time and are determined or obtained during operation of the controller. The manner of dynamically determining values is a matter of design choice. For example, in at least one embodiment, the controller calculates the dynamically determined, minimum line voltage switching threshold. In at least one embodiment, the controller determines the determined, minimum line voltage switching threshold by accessing values from a memory that correspond to a particular amount of power utilization by the load.

Disabling and enabling switching of the dynamically determined, minimum line voltage switching threshold introduces harmonic distortion and can introduce instability in a control signal generation system. In at least one embodiment, the controller has a maximum threshold value for the dynamically determined, minimum line voltage switching threshold to prevent, for example, exceeding total harmonic distortion regulations.

FIG. 4 depicts an electronic power control system 400 that dynamically determines a minimum line voltage switching threshold based on power utilization of load 132. Electronic power system 400 includes a controller 402, which is constructed as, for example, an integrated circuit, discrete digital and/or analog components, or a combination of integrated circuits and discrete digital and/or analog components. The controller 402 includes a control signal generator 404 to generate a control signal CS₁. The control signal generator 404 includes a load-based power utilization threshold generator 406 that generates a dynamically determined, minimum line voltage switching threshold V_{LINE—MIN—DYN}. As subsequently described in more detail, the threshold generator 406 dynamically determines power utilization by the load 132 and generates a corresponding minimum line voltage switching threshold V_{LINE—MIN—DYN}. By dynamically determining the minimum line voltage switching threshold V_{LINE—MIN—DYN} based on power utilization of load 132, controller 402 disables and enables the control signal CS₁ in correlation with power supplied by switching power converter 408 to power utilization by the load 132. The frequency of determining the minimum line voltage switching threshold V_{LINE—MIN—DYN} is a matter of design choice.

Switching power converter 408 can be any type of switching power converter such as a boost-type switching power converter identical to switching power converter 104 (FIG. 1), a buck-type switching power converter, a boost-buck type switching power converter, or a Cúk-type switching power converter. Other types of switching power converters are well-known to those of ordinary skill in the art. Switch 410 is any type of switch such as a field effect transistor (FET).

FIG. 5 depicts exemplary signals 500 associated with electronic power control system 400. Referring to FIGS. 4 and 5, since the minimum line voltage switching threshold V_{LINE—MIN—DYN} is dynamically determined by controller 402, the voltage switching threshold V_{LINE—MIN—DYN} changes over time as the power utilization of the load 132 changes. In at least one embodiment, the value of the voltage switching threshold V_{LINE—MIN—DYN} correlates to a switching duty cycle of control signal CS₁. The “switching duty cycle of control signal CS₁” refers to the percentage of time during a cycle of input voltage V_X during which control signal CS₁ is generating pulses to cause switch 410 to conduct. In at least one embodiment, controller 402 does not generate a pulse of control signal CS₁ until the input voltage V_X is equal to the voltage switching threshold V_{LINE—MIN—DYN}. Once the input voltage V_X reaches the voltage switching threshold V_{LINE—MIN—DYN}, controller 402 begins generating pulses of control signal CS₁.

For example, the power utilization of load 132 for cycle 502 of the input voltage V_X correlates to a value of the voltage switching threshold V_{LINE—MIN—DYN} equal to V_{LINE—MIN—DYN—502}. The input voltage V_X initially reaches V_{LINE—MIN—DYN—502} at a 30° phase angle cut of input voltage V_X and reaches V_{LINE—MIN—DYN—502} again at a 150° phase angle cut. In at least one embodiment, for cycle 502, controller 402 begins generating pulses of control signal CS₁ when the input voltage V_X initially reaches V_{LINE—MIN—DYN—502} at the 30° phase angle of the input voltage V_X. In at least one embodiment, controller 402 stops generating pulses of control signal CS₁ when the input voltage V_X reaches a 150° phase angle cut of the input voltage V_X. Accordingly, in this embodiment, the switching duty cycle of control signal CS₁ is reduced by ⅓ or approximately 33.3%, e.g. for a sine wave [1−(150°−30°)/180°].

Continuing the example, the cycle 504 of the input voltage V_X occurs at a time after cycle 504 when the power utilization of load 132 has increased relative to the power utilization of the load 132 when cycle 502 was generated. The power utilization of load 132 for cycle 504 now correlates to a value of the voltage switching threshold V_{LINE—MIN—DYN} equal to V_{LINE—MIN—DYN—504}. The value of voltage switching threshold V_{LINE—MIN—DYN—504} is less than the value of voltage switching threshold V_{LINE—MIN—DYN—502} so that portion of the input voltage V_X used to provide power to load 132 during cycle 502 is greater than the portion of the input voltage V_X used to provide power to load 132 during cycle 504. For cycle 504, the input voltage V_X initially reaches V_{LINE—MIN—DYN—504} at a 20° phase angle cut of input voltage V_X and reaches V_{LINE—MIN—DYN—504} again at a 160° phase angle cut. In at least one embodiment, for cycle 504, controller 402 begins generating pulses of control signal CS₁ when the input voltage V_X initially reaches V_{LINE—MIN—DYN—504} at the 30° phase angle of the input voltage V_X. In at least one embodiment, controller 402 stops generating pulses of control signal CS₁ when the input voltage V_X reaches a 160° phase angle cut of the input voltage V_X. Accordingly, in this embodiment, the switching duty cycle of control signal CS₁ is reduced by 2/9 or approximately 22.2%, i.e. [1−(160°−20°)/180°].

Thus, when the dynamically determined, minimum line voltage switching threshold V_{LINE—MIN—DYN} is non-zero, controller 402 enables and disables the generation of pulses of control signal CS₁ when the input voltage V_X is below the voltage switching threshold V_{LINE—MIN—DYN}. Because the input voltage V_X is less at low and high phase angles relative to the peak voltage phase angle of 90°, input voltage V_X provides less power at the low and high phase angles than at phase angles closer to 90°. For example, the input voltage V_X at phase angles 20° and 160° provides less power than when the input voltage V_X is at 30° and 150°. However, switching power losses of switch 410 remain constant while controller 402 generates pulses of control signal CS₁ regardless of the phase angle of input voltage V_X. Thus, the efficiency of electronic power control system 400 increases when the switching duty cycle of control signal CS₁ decreases at low and high phase angles relative to the peak phase angle of 90°.

As the voltage switching threshold V_{LINE—MIN—DYN} increases, the frequencies of the input current i_IN and the input voltage V_X diverge. Divergent frequencies of the input current i_IN and the input voltage V_X cause harmonic distortion. In at least one embodiment, to prevent the total harmonic distortion (THD) from exceeding a predetermined maximum allowable THD, a maximum voltage switching threshold V_{LINE—MIN—DYN—MAX} is set. As subsequently discussed in more detail, the value of the maximum voltage switching threshold V_{LINE—MIN—DYN—MAX} is a function of one or more operating parameters of the electronic power control system 400. Also, as subsequently discussed in more detail, in at least one embodiment, controller 402 dynamically determines the maximum voltage switching threshold V_{LINE—MIN—DYN—MAX} based on power utilization of the load 132.

The number of dynamically determined, minimum line voltage switching thresholds used per cycle of input voltage V_X is a matter of design choice. In FIG. 5, the waveform of each cycle of the used input voltage V_X—USED is symmetric, i.e. the same voltage switching threshold V_{LINE—MIN—DYN} is used to determine when to begin generating pulses of control signal CS₁ and when to stop generating pulses of control signal CS₁. In another embodiment, one voltage switching threshold is used to determine when to begin generating pulses of control signal CS₁ and another voltage switching threshold is used to determine when to stop generating pulses of control signal CS₁.

FIG. 6 depicts a control signal generator 600, which represents one embodiment of the control signal generator 404. In at least one embodiment, the control signal generator 600 includes a microprocessor and a memory having code executable by the processor to implement some or all of the operations of the control signal generator. Control signal generator 600 receives the sense signals V_LINK—SENSE and V_X—SENSE, which respectively represent link voltage V_LINK and input voltage V_X. Subtraction operator 602 subtracts the sense signal V_LINK—SENSE from a reference voltage V_REF to generate an error signal e_V. The reference signal V_REF represents a target link voltage. As the load 132 requires less power, less current is drawn from link capacitor 130 (FIG. 4). As less current is drawn from capacitor 130, the link voltage V_LINK will begin to increase. Thus, since the sense signal V_LINK—SENSE is directly proportional to the link voltage V_LINK, the sense signal V_LINK—SENSE increases above the reference voltage V_REF as the power utilization of load 132 decreases. Conversely, when the power utilization of load 132 increases, more current is drawn from capacitor 130, and the link voltage V_LINK, and correspondingly the sense signal V_LINK—SENSE will decrease. Thus, the error signal e_V provides a direct indication of the power utilization of load 132.

A proportional integrator 604 performs a proportional integration on the error signal e_V and generates a power utilization factor PU representing the power utilization of load 132. The proportional integrator 604 compensates for small changes in the error signal e_V over time to generate a stable power utilization factor PU. In at least one embodiment, the power utilization factor PU is a value ranging from 0 to 1, with 0 corresponding to zero power utilization and 1 corresponding to 100% power utilization by load 132 of power available from switching power converter 408 (FIG. 4). In at least one embodiment, the subtraction operator 602 and proportional integrator 604 dynamically determine the power utilization of the load 132 during each cycle of the input voltage V_X.

The load-based power utilization threshold generator 606 generates the voltage switching threshold V_{LINE—MIN—DYN} using the power utilization factor PU. In at least one embodiment, the load-based power utilization threshold generator 606 executes the following Verilog code to generate the voltage switching threshold V_{LINE—MIN—DYN}:

• • (1) always@(posedge clk)
  • (2) if (PU<Vrect_thresh_trip)
  • (3) Vrect_thresh<=vrect_cut*(PU−Vrect_thresh_trip);
  • (4) else
  • (5) Vrect_thresh<=0;
  • (6) V_{LINE—MIN—DYN}=Vrect_thresh*Vpeak;
  • Line (1) of the code causes the subsequent lines of code to execute at a frequency “clk”. An exemplary value for the frequency clk is 2 times the frequency of the input voltage V_IN, such as 120 Hz in the United States of America and 100 Hz in Europe.
  • Line (2) of the code determines if the power utilization factor PU of the load 132 is less than the value of Vrect_thresh_trip. The value of Vrect_thresh_trip is a maximum percentage of the input voltage V_X above which the switching duty cycle of control signal CS₁ is set to 100%. The value of Vrect_thresh_trip directly corresponds to the voltage switching threshold V_{LINE—MIN—DYN—MAX}. If PU is less than Vrect_thresh_trip, then line (3) is executed. Otherwise, the load-based power utilization threshold generator 606 executes lines (4) and (5).
  • Line (3) sets the value of Vrect_thresh equal to vrect_cut times (PU-Vrect_thresh_trip). “vrect_cut” represents a rate of change of voltage switching threshold V_{LINE—MIN—DYN} as the power utilization factor PU changes. The power utilization factor PU and the voltage switching threshold V_{LINE—MIN—DYN} are inversely proportional, so the value of vrect_cut is negative.
  • Lines (4) and (5) set the value of Vrect_thresh equal to zero if the power utilization factor PU is greater than Vrect_thresh_trip. Setting Vrect_thresh equal to zero indicates that the power utilization of the load 132 is high enough for load-based power utilization threshold generator 606 to set the switching duty cycle of control signal CS₁ to 100%.
  • Line (6) sets the voltage switching threshold V_{LINE—MIN—DYN} equal to Vrect_thresh times Vpeak, and Vpeak is the peak voltage of the input voltage V_X. Thus, if Vrect_thresh equals 0 because of a high power utilization of load 132, voltage switching threshold V_{LINE—MIN—DYN} is set to 0. If voltage switching threshold V_{LINE—MIN—DYN} is zero, the control signal CS₁ has a 100% switching duty cycle, and switch 410 operates continually until the value of voltage switching threshold V_{LINE—MIN—DYN} changes. If Vrect_thresh is non-zero, load-based power utilization threshold generator 606 sets the value of voltage switching threshold V_{LINE—MIN—DYN} equal to the percentage of the peak input voltage V_X indicated by Vrect_thresh.

FIG. 7 depicts voltage switching threshold V_{LINE—MIN—DYN} related parameter relationships 700 as determined by an exemplary embodiment of the code to generate the voltage switching threshold V_{LINE—MIN—DYN}. The voltage switching threshold V_{LINE—MIN—DYN} can be determined for any peak value of input voltage V_X. Two typical values of 230 VRMS and 115 VRMS are illustrative of the relationship between the power utilization PU of load 132 and the voltage switching threshold V_{LINE—MIN—DYN}.

Referring to FIGS. 6 and 7, if the power utilization PU is greater than Vrect_thresh_trip, then load-based power utilization threshold generator 606 generates control signal CS₁ with a 100% switching duty cycle. If the power utilization PU is less than Vrect_thresh_trip, then the value of voltage switching threshold V_{LINE—MIN—DYN} increases at a rate equal to vrect_cut. In at least one embodiment, the value of voltage switching threshold V_{LINE—MIN—DYN} continues to increase until the power utilization equals zero. In another embodiment, the value of voltage switching threshold V_{LINE—MIN—DYN} increases until the power utilization factor reaches a minimum power utilization associated with an acceptable loop gain in load-based power utilization threshold generator 606. The minimum power utilization for the input voltage equal to 115VRMS and 230VRMS is respectively PU_GST_—115 and PU_GST_—230. When voltage switching threshold V_{LINE—MIN—DYN} reaches PU_GST_—115 for V_X=115VRMS or PU_GST_—230 for V_X=230VRMS, voltage switching threshold V_{LINE—MIN—DYN} is set respectively to voltage switching threshold V_{LINE—MIN—DYN—115} or voltage switching threshold V_{LINE—MIN—DYN—230}. The power transferred over a quarter-sine wave of input voltage V_X is shown below. Since the input voltage V_X is symmetrical for phase angles 0-90° and 90°-180° (i.e. 0−π/2 and π/2−π), the integral for power P is determined from 0 to pi/2, i.e. 90°, to allow for a less complicated integral:

P = Vrms 2 R

P = ∫ T Π / 2 ⁢ Vrms 2 * sin 2 ⁡ ( t ) R ⁢ ⅆ t

P = C * ∫ T Π / 2 ⁢ sin 2 ⁡ ( t ) ⁢ ⁢ ⅆ t

P = C 4 * ( - 2 * T + sin ⁡ ( 2 - T ) + Π )
T represents the phase angle cut in radians of the input voltage V_X, and C represents Vrms²/R. T is expressed in terms of Vrect_thresh (with 0 being no cut of the input voltage V_X and 1 being a full sine wave cut of input voltage V_X) as follows:
T=arcsine(Vrect_thresh)
Accordingly, the proportion of power cut (P_cut) by the load-based power utilization threshold generator 606 as a result of cutting the input voltage V_X and the actual total power (P_tot) available for supply by the switching power converter 408 (FIG. 4) is:

P cut P tot = C 4 * ( - 2 * sin - 1 ⁡ ( Vrect thresh ) + sin ⁡ ( 2 * sin - 1 ⁡ ( Vrect thresh ) ) + Π ) C 4 * Π ⁢ ⁢ P cut P tot = - 2 Π * sin - 1 ⁡ ( Vrect thresh ) + 1 Π * sin ⁡ ( 2 * sin - 1 ⁡ ( Vrect thresh ) ) + 1 [ 1 ]

Referring to Table 1, Vrect_thresh equals voltage switching threshold V_{LINE—MIN—DYN}/V_X—PEAK. The Phase refers to the phase cut of the input voltage V_X, sin⁻¹ (Vrect_thresh) is the arcsin of Vrect_thresh. “% Power” is the amount of power relative to total power available from input voltage V_X with no phase cutting that is provided by switching power converter 408 to load 132. The Gain is gain introduced into load-based power utilization threshold generator 606 by the phase cutting due to the difference between the expected power to be delivered to the load 132 based on zero phase cutting of the input voltage V_X, and the actual power delivered to the load 132 with phase cutting of input voltage V_X. For example, for a 115VRMS peak input voltage V_X, if Vrect_thresh equals 0.5, voltage switching threshold V_{LINE—MIN—DYN} equals 57.5V, the phase angle cut is 30°, the percentage power delivered to the load 132 is 94%, and the gain is −0.52 dB.

Following is a specific example of the effect of a non-zero voltage switching threshold V_{LINE—MIN—DYN} for a vrect_thresh_trip corresponding to a 0.4 power utilization factor PU, i.e. voltage switching threshold V_{LINE—MIN—DYN} equals 0 for all PU>0.4, thus, no phase cutting of input voltage V_X for all values of the input voltage V_X above the voltage switching threshold V_{LINE—MIN—DYN}.

• • if (Pu>0.4)
  • Vrect_thresh_pct=0.0;

else

• • Vrect_thresh_pct=(0.4−Pu);

For this example, the derivative of P_CUT/P_TOT is:

ⅆ ⅆ x * ( - 2 Π * sin - 1 ⁡ ( 0.4 - x ) + 1 Π * sin ⁡ ( 2 * sin - 1 ⁡ ( 0.4 - x ) ) + 1 ) = 2 - 2 * cos ⁡ ( 2 * sin - 1 ⁡ ( 0.4 - x ) ) Π * 1 - ( 0.4 - x ) 2 [ 2 ]

Table 2 represents the evaluation of equation [2] over the valid range of the power utilization factor PU less than or equal to 0.4:

Thus, as the power utilization factor decreases and the voltage switching threshold V_{LINE—MIN—DYN} increases, the negative effect on the loop gain of the load-based power utilization threshold generator 606 becomes apparent. Accordingly, in at least one embodiment, to maintain a stable load-based power utilization threshold generator 606, the maximum voltage switching threshold V_{LINE—MIN—DYN} is set so that the corresponding loop gain does not cause the load-based power utilization threshold generator 606 to become unstable. The particular value of the maximum voltage switching threshold V_{LINE—MIN—DYN} depends upon characteristics of electronic power control system 400. In at least one embodiment, vrect_thresh_trip is set at PU equal to 0.4.

Thus, in at least one embodiment, when selecting values for vrect_thresh_trip and vrect_cut three trade-off criteria are considered:

Efficiency improvements by increasing the maximum allowable voltage switching threshold V_{LINE—MIN—DYN};

Minimizing control loop stability impact due to, for example, increasing negative loop gain;

Maintain acceptable THD+noise.

In at least one embodiment, to achieve efficiency while having at most a 1.11 dB impact on the control loop and no change in THD+noise below 20% of full power P_TOT, set vrect_thresh_trip at 0.2 and select vrect_cut such that at Pu=0, vrect_thresh is 0.3. This would give a vrect_cut of 1.5.

Referring to FIG. 6, control signal generator 600 includes a T₁/TT generator 608 to determine T₁ and TT of the control signal CS₁. “T₁” is the pulse width of control signal CS₁, and “TT” is the period of control signal CS₁. The voltage switching threshold V_{LINE—MIN—DYN} is utilized as previously described to disable generation of control signal CS₁ by, for example, setting the pulse width T₁ of control signal CS₁ equal to zero. The T₁/TT generator 608 provides the determined values of T₁ and TT to pulse width modulator (PWM) 610. PWM 610 generates the control signal CS₁ in accordance with the values of T₁ and TT received from the T₁/TT generator 608.

The particular implementation of the T₁/TT generator 608 and the proportional integrator 604 are matters of design choice. In at least one embodiment, the T₁/TT generator 608 and proportional integrator are implemented as described in U.S. Pat. No. 7,719,246, entitled “Power Control System Using a Nonlinear Delta-Sigma Modulator with Nonlinear Power Conversion Process Modeling”, filed Dec. 31, 2007, inventor John L. Melanson, and assignee Cirrus Logic, Inc., which is hereby incorporated by reference in its entirety.

FIG. 8 depicts an exemplary load-based power utilization threshold generator 800, which represents an embodiment of the load-based power utilization threshold generator 606. The values of “Vrect_cut”, “PU”, “Vrect_thresh_trip”, “Vrect_thresh”, “Vpeak”, “V_{LINE—MIN—DYN}”, and “clk” are the same as described in conjunction with the load-based power utilization threshold generator 606 and the Verilog code used to generate the voltage switching threshold V_{LINE—MIN—DYN}. The load-based power utilization threshold generator 800 includes a 2:1 multiplexer 802. If PU is less than Vrect_thresh_trip, then multiplexer 802 selects vrect_cut*(PU−Vrect_thresh_trip) as the output of multiplexer 802. Otherwise, the output of multiplexer 802 is 0. D-flip-flop 804 provides the output Vrect_thresh of multiplexer 802 as to an input of multiplier 806 upon occurrence of each positive edge of the clock signal clk. Multiplier 806 multiplies Vrect_thresh times Vpeak to generate voltage switching threshold V_{LINE—MIN—DYN}. Thus, if Vrect_thresh is non-zero, load-based power utilization threshold generator 800 sets the value of voltage switching threshold V_{LINE—MIN—DYN} equal to the percentage of the peak input voltage V_X indicated by Vrect_thresh.

Thus, by correlating phase cutting of the input voltage to power utilization by a load, in at least one embodiment, an electronic system reduces switching losses associated with switching of a control switch in the switching power converter while still meeting power demands by a load.

Although embodiments have been described in detail, it should be understood that various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.