Data storage device employing cascaded voltage regulators during power failure

Description

BACKGROUND

Data storage devices (DSDs), such as disk drives and solid state drives are employed in numerous areas such as computer systems (e.g., desktops, laptops, portables, etc.) and consumer devices (e.g., music players, cell phones, cameras, etc.). User data is typically stored in a non-volatile memory, such as a magnetic disk or a non-volatile semiconductor memory (e.g., Flash memory). When a power failure occurs, it may be desirable to complete pending write commands prior to safely shutting down the DSD so that user data is not lost. This is of particular concern in DSDs that cache write data in a volatile semiconductor memory prior to writing the data to the non-volatile memory. A conventional DSD may charge a capacitor to a high voltage using the power supplied by the host, and then use the capacitor voltage to power circuitry in the DSD to flush a write cache during a power failure. Using a high voltage capacitor to generate the backup power is more cost effective compared to using a lower voltage capacitor or bank of capacitors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a data storage device according to an embodiment of the present invention comprising a non-volatile memory.

FIG. 1B shows control circuitry according to an embodiment of the present invention comprising a capacitor, an operating voltage regulator, and a backup voltage regulator.

FIG. 1C is a flow diagram according to an embodiment of the present invention wherein the backup voltage regulator converts the capacitor voltage to a backup voltage for powering the operating voltage regulator during a power failure.

FIG. 2A shows a data storage device comprising a disk drive according to an embodiment of the present invention wherein a 5 v supply is used to charge the capacitor and a 12 v supply powers a voice coil motor (VCM).

FIG. 2B shows a data storage device comprising a disk drive according to an embodiment of the present invention wherein a 5 v supply is used to charge the capacitor as well as power a voice coil motor (VCM).

FIG. 3 shows a data storage device comprising a non-volatile semiconductor memory according to an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

FIGS. 1A and 1B show a data storage device 2 according to an embodiment of the present invention comprising a non-volatile memory 4, and control circuitry 6 comprising an interface operable to receive a supply voltage 8, and a capacitor 10. The control circuitry 6 executes the flow diagram of FIG. 1C wherein an operating voltage regulator 12 converts the supply voltage 8 into an operating voltage 14 used to operate the non-volatile memory 4 (step 22). The supply voltage 8 is used to charge the capacitor 10 to a capacitor voltage 16 higher than the supply voltage 8 (step 24), and during a power failure (step 26), a backup voltage regulator 18 converts the capacitor voltage 16 into a backup voltage 20 substantially equal to the supply voltage 8 (step 28). The operating voltage regulator 12 converts the backup voltage 20 into the operating voltage 14 used to operate the non-volatile memory 4 (step 30).

In the embodiment of FIG. 1B, the control circuitry 6 comprises a suitable controller 32 (e.g., a microprocessor and memory) that controls the non-volatile memory 4 in response to the operating voltage 14, for example, by processing host write/read commands. During normal operation, a voltage booster 34 boosts the supply voltage 8 to a boosted voltage 36 that charges the capacitor 10 to a capacitor voltage 16 higher than the supply voltage 8. When a power fail is detected, a power fail control signal 38 disconnects the charging voltage 36 from the capacitor 10, and connects the input of the operating voltage regulator 12 to the backup voltage 20 output by the backup voltage regulator 18.

In the embodiments of the present invention, cascading an operating voltage regulator with a backup voltage regulator decreases the overall expense of the data storage device by enabling the operating voltage regulator to be supplied with the same voltage during a power failure as that supplied during normal operation. This is particularly beneficial when the data storage device comprises multiple operating voltage regulators that can be cascaded with the backup voltage regulator rather than design all of the operating voltage regulators to tolerate a higher supply voltage during a power failure. That is, the backup voltage regulator is designed to convert the higher capacitor voltage to a backup voltage substantially equal to the supply voltage for use by the downstream operating voltage regulators during a power failure. Those skilled in the art will recognize that the several embodiments in the following figures provide example voltage levels in accordance with the general principles set forth above and that other voltage levels may be used.

FIG. 2A shows an embodiment of the present invention wherein the data storage device comprises a disk drive employing multiple operating voltage regulators for generating different operating voltages. For example, operating voltage regulators 40 may generate a 1 v operating voltage and a 1.5 v operating voltage supplied to a core logic and memory block 42, and a 2.5 v operating voltage supplied to a read channel 44. In this embodiment, the disk drive receives a 5 v supply voltage 8A and a 12 v supply voltage 8B from a host. The 12 v supply voltage 8B is applied to a VCM driver 46 that generates a control signal 48 for controlling a VCM 50 that actuates a head 52 radially over a disk 54. The 5 v supply voltage 8A is applied to the operating voltage regulators 40 during normal operation. An operating voltage regulator 56 also boosts the 5 v supply voltage to generate a 17 v boosted voltage 58 for charging the capacitor 10. The 17 v boosted voltage 58 is also applied to a microactuator driver 60 that generates a control signal 62 for controlling a microactuator 64.

When a power fail is detected, the power fail control signal 38 disconnects the VCM driver 46 from the 12 v supply voltage 8B so that the VCM driver 46 is powered by a spindle motor supply voltage 66 generated from a back electromotive force (BEMF) voltage of a spindle motor (not shown) that rotates the disk 54. The backup voltage regulator 18 converts the capacitor voltage across capacitor 10 to a 5 v backup voltage 20, and the power fail control signal 38 connects the operating voltage regulators 40 to the 5 v backup voltage 20. The power fail control signal 38 also connects the operating voltage regulator 56 to the 5 v backup voltage 20 so as to continue to generate the 17 v boosted voltage for the microactuator driver 60. Accordingly, in this embodiment the backup voltage regulator 18 is designed to tolerate the 17 v boosted voltage 58 whereas the operating voltage regulators 40 and 56 are designed to tolerate the lower 5 v supply voltage 8A.

FIG. 2B shows an alternative embodiment of the present invention wherein the disk drive receives a single 5 v supply voltage 8 from the host applied to the operating voltage regulators 40 and 56, as well as to the VCM driver 46 during normal operation. A disk drive operating from a single 5 v supply voltage 8 typically employs a smaller form factor disk, such as a 2.5 inch disk drive as compared to a 3.5 inch disk drive that typically requires a 5 v supply voltage and a 12 v supply voltage as shown in FIG. 2A.

FIG. 3 shows a non-volatile semiconductor memory 68 comprising a memory device 70 having a memory array 72 including a plurality of memory segments, and a data register 74 for storing write data prior to being written to one of the memory segments. A memory controller 76 comprises a microprocessor 78 for executing access commands received from a host 80. Interface circuitry 82 generates control signals that enable the microprocessor 78 to communicate with the memory device 70. The non-volatile semiconductor memory 68 may comprise any suitable configuration of memory controller 76 and memory device 70. In one embodiment, the memory device 70 comprises a suitable flash memory (e.g., NAND or NOR flash), and the memory controller 76 comprises a suitable flash controller. In one embodiment, the memory controller 76 implements a solid state drive (SSD) by emulating a disk drive accessible by a host system using a standard disk drive communication protocol (e.g., the ATA protocol). The host 80 in this embodiment may comprise a separate microprocessor (e.g., in a desktop or laptop computer) which communicates with the SSD over a suitable interface (e.g., serial or parallel ATA). In an alternative embodiment, the non-volatile semiconductor memory 68 may be implemented within a consumer device (e.g., a camera or cell phone), wherein the host 80 may be implemented as a firmware component executed by the same microprocessor 78 for implementing the memory controller 76.

In one embodiment, the memory controller 76 comprises a volatile memory (e.g., DRAM) implementing a buffer 84 for caching data that is written to the memory device 70 and read from the memory device 70. The interface circuitry 82 comprises suitable state machine circuitry for accessing the buffer 84 during write/read operations. The memory device 70 comprises a controller 86 for receiving the control signals and command data from the interface circuitry 82. For example, the command data may comprise address information for writing data to a particular memory segment in the memory array 72. The write data is buffered in the data register 74 and when the controller 86 receives a flush command, the controller 86 transfers the data buffered in the data register 74 to the target memory segment in the memory array 72.

The memory controller 76 comprises one or more operating voltage regulators 88 for converting a supply voltage 90 into one or more operating voltages 92 for controlling the components of the non-volatile semiconductor memory 68 during normal operation. The supply voltage 90 is boosted 94 to generate a boosted voltage 96 for charging a capacitor 10. During a power failure, a backup voltage regulator 98 converts the capacitor voltage into a backup voltage substantially equal to the supply voltage 90, and a power fail control signal 38 connects the operating voltage regulator 88 to the backup voltage (as well as disconnects the boosting voltage regulator 94 from the capacitor 10). In this manner, the backup voltage enables the interface circuitry 82 to command the memory device 70 to flush the data stored in the data register 74 prior to shutting down.

Any suitable control circuitry may be employed to implement the flow diagrams in the embodiments of the present invention, such as any suitable integrated circuit or circuits. In one embodiment, the control circuitry may comprise a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the steps of the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a system on a chip (SOC). In another embodiment, the instructions are stored on a disk or in a non-volatile semiconductor memory and read into a volatile semiconductor memory when the data storage device is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry. In one embodiment, the operating voltage regulator(s) and the backup voltage regulator may be implemented within a power large scale integrated (PLSI) circuit coupled to an SOC, or integrated within an SOC.