Disk drive initializing servo read channel by reading data preceding servo preamble during access operation

Description

BACKGROUND

Disk drives comprise a disk and a head connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. The disk comprises a plurality of radially spaced, concentric tracks for recording user data sectors and servo sectors. The servo sectors comprise head positioning information (e.g., a track and wedge address) which is read by the head and processed by a servo control system to control the actuator arm as it seeks from track to track as well as establish rotational position of the head.

FIG. 1 shows a prior art disk format 2 as comprising a number of servo tracks 4 defined by servo sectors 6₀-6_N recorded around the circumference of each servo track. Each servo sector 6_i comprises a preamble 8 for storing a periodic pattern, which allows proper gain adjustment and timing synchronization of the read signal, and a sync mark 10 for storing a special pattern used to symbol synchronize to a servo data field 12. The servo data field 12 stores coarse head positioning information, such as a servo track address (Gray coded) and wedge address, used to position the head over a target data track during a seek operation and monitor the rotational position with respect to a reference index-wedge. Each servo sector 4, further comprises groups of servo bursts 14 (A, B, C, D in the example shown), which are recorded with precise intervals and offsets relative to the servo track centerlines. The servo bursts 14 provide fine head position information used for centerline tracking while accessing a data track during write/read operations.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a prior art disk format comprising a plurality of servo tracks defined by embedded servo sectors.

FIG. 2A shows a disk drive according to an embodiment comprising a head actuated over a disk.

FIG. 2B illustrates an embodiment wherein a servo gate is opened early over data preceding a servo preamble.

FIG. 2C is a flow diagram according to an embodiment wherein during an access operation, data preceding the servo preamble is read in order to initialize an analog front end of a servo read channel.

FIG. 3 shows a servo read channel according to an embodiment comprising an analog front end and a timing recovery circuit.

FIG. 4 shows an embodiment wherein the data preceding the servo preamble comprises data of a data sector in a data track.

FIG. 5 shows an embodiment wherein the data preceding the servo preamble comprises servo data in the servo sector.

FIGS. 6A-6C illustrate an embodiment wherein at least part of a servo preamble is overwritten with data of a data sector during a write operation in order to eliminate the gap between the data sector and the servo sector.

DETAILED DESCRIPTION

FIG. 2A shows a disk drive according to an embodiment comprising a disk 16 having a plurality of data tracks 18 defined by servo sectors 20₀-20_N, where each data track comprises a plurality of data sectors, and each servo sector comprises a servo preamble 22 and servo data 24 (FIG. 2B). The disk drive further comprises a head 26 comprising a read element and a write element, and control circuitry 28 comprising a servo read channel (FIG. 3) including an analog front end (AFE) 30 and a timing recovery circuit 32. The control circuitry 28 is operable to execute the flow diagram of FIG. 2C, wherein during an access operation (block 34) the head is positioned over a first data track (block 36), and during a revolution of the disk, a first data sector of the first data track is accessed (block 38). After accessing the first data sector, data 40 (FIG. 2B) preceding the servo preamble 22 of a first servo sector in the first data track is read (block 40) in order to initialize the AFE 30 of the servo read channel (block 42). At least part of the servo preamble 22 is read to initialize the timing recovery circuit 32 of the servo read channel (block 44), and at least part of the servo data 24 of the servo sector is read using the timing recovery circuit (block 46).

In the embodiment of FIG. 2A, the control circuitry 28 processes a read signal 50 emanating from the head 26 to demodulate the servo sectors 20₀-20_N and generate a position error signal (PES) representing an error between the actual position of the head and a target position relative to a target track. The control circuitry 28 filters the PES using a suitable compensation filter to generate a control signal 52 applied to a voice coil motor (VCM) 54 which rotates an actuator arm 56 about a pivot in order to actuate the head 26 radially over the disk 18 in a direction that reduces the PES. The servo sectors 20₀-20_N may comprise any suitable head position information, such as a track address for coarse positioning and servo bursts for fine positioning. The servo bursts may comprise any suitable pattern, such as an amplitude based servo pattern (FIG. 1) or a phase based servo pattern.

During an access operation (write/read), the control circuitry 28 seeks the head 26 to a target data track, and then tracks a centerline of the data track in response to the servo sectors 20₀-20_N. In order to demodulate a servo sector 20_i, the control circuitry 28 opens a servo gate, and in an embodiment illustrated in FIG. 2B, the servo gate is opened when the head 26 is over data 40 that precedes the servo preamble 22 in order to initialize the AFE 30 of the servo read channel (FIG. 3). When the head 26 reaches the servo preamble 22, the AFE 30 has been properly initialized so that the timing recovery circuit 32 may be synchronized in response to the servo preamble 22. This allows the length of the servo preamble 22 to be reduced as compared to a prior art technique of using the beginning of the servo preamble 22 to initialize the AFE 30. Reducing the length of the servo preamble 22 can improve the format efficiency and can increase the overall capacity of the disk 18.

In the embodiment of FIG. 3, the AFE 30 comprises suitable circuitry for preconditioning the read signal 50, such as an analog filter (e.g., a low pass filter) for shaping the read signal 50 toward a desired response (e.g., a partial response). The timing recovery circuit 32 generates a sampling clock 58 for use in sampling the analog signal 60 output by the AFE 30 to generate signal samples 62. The signal samples 62 may be equalized by an equalizer filter 64 in order to further shape the signal samples 62 toward the desired response, and the equalized signal samples 66 may be processed by a sequence detector 68 to detect the servo data 24.

In one embodiment, the timing recovery circuit 32 generates the sampling clock 58 synchronous to the data rate of the servo data (i.e., the analog signal 60 is sampled synchronously). Accordingly in this embodiment the servo preamble 22 is processed in order to initially synchronize the timing recovery circuit 32 prior to reading the servo data 24. In one embodiment, the timing recovery circuit 32 executes a zero-phase start operation wherein the phase of a phase-locked loop (PLL) is initialized based on the first few signal samples of the servo preamble 22. Once the phase of the PLL has been initialized, the remaining signal samples of the servo preamble 22 are processed to further lock the PLL to the frequency/phase of the servo preamble 22. Accordingly, in one embodiment the control circuitry 28 enables the servo read gate (FIG. 2B) to begin initializing the AFE 30, and then enables another internal gate to enable the timing recovery circuit 32 to execute the zero-phase start operation. Other embodiments may employ interpolated timing recovery (ITR), wherein the analog signal 60 output by the AFE 30 may be sampled asynchronously, and the asynchronous signal samples interpolated to generate the synchronous signal samples. An embodiment employing an ITR type timing recovery may also execute a zero-phase start operation at the beginning of the servo preamble 22.

At least some of the components of the servo read channel shown in FIG. 3 may also be used to read the data sectors of a data track. In one embodiment, some of the components of the read channel may be configured based on whether the read channel is reading a data sector or a servo sector (e.g., the AFE 30 and equalizer filter 64 may be configured to adjust the filtering of the read signal). In one embodiment, the sequence detector 68 may be used to detect both the user data of a data sector and the servo data of a servo sector. In another embodiment, the sequence detector for detecting the servo data may be less complex than the sequence detector for detecting the user data in order to reduce the latency of the detection algorithm, thereby improving performance of the servo algorithm.

Any suitable data 40 may precede the servo preamble 22 in FIG. 2B, wherein in an embodiment shown in FIG. 4 the data comprises data of a data sector 70 preceding the servo preamble 22. The data of the data sector 70 may comprise random (i.e., unknown) user data that is written to the disk during a write operation. Even though the frequency content of the random user data may be different than the servo preamble 22, the random user data may still be used to initialize the AFE 30 which is why the servo gate is opened while the head is still over the data sector 70. In one embodiment, the gap between the end of the data sector 70 and the beginning of the servo preamble 22 is erased (e.g., AC erased) so that the DC component of the read signal is substantially zero, thereby matching the DC component of the servo preamble 22.

In one embodiment, the data 40 that precedes the servo preamble 22 in FIG. 2B comprises at least part of the servo data 24. FIG. 5 shows an embodiment wherein the servo sector comprises a long format and a short format, wherein the short format facilitates writing a data sector up to the beginning of the servo sector (when the read element 84 leads the write element 86 as shown in FIG. 6A). The long format of the servo sector is read during non-write operations, such as during seeks and read operations. The servo sector can include a first preamble 72, a first sync mark 74, a high order of a servo track ID 76, a second preamble 78, a second sync mark 80, and a low order servo track ID 82. While tracking a data track during a write operation, the high order servo track ID 76 does not change and therefore in one embodiment is not fully read when reading a servo sector. Instead, the short format of the servo sector is read comprising the second preamble 78, the second sync mark 80, and the low order servo track ID 82. In this embodiment the servo gate may be opened while the read element 84 is over the high order servo track ID 76 as illustrated in FIG. 5 so that at least one of the high order bits of the servo track ID may be read to initialize the AFE 30 of the servo read channel. This embodiment reduces the length of the second preamble 78 by including just enough pattern to initialize the timing recovery circuit 32. The servo data 24 may comprise additional fields not shown in FIG. 5, such as a wedge ID that identifies the circumferential location of the head (the current servo sector). The wedge ID may be recorded in a split format similar to the track ID in FIG. 5, wherein a high order wedge ID may be recorded in the long format and a low order wedge ID may be recorded in the short format.

FIG. 6A shows an embodiment wherein an extended length servo preamble is initially written when servo writing the servo sectors to the disk. The extended length servo preamble is then read, for example, during a manufacturing procedure in order to improve the servoing operation. For example, the manufacturing procedure may learn servo compensation values (e.g., to compensate for a repeatable runout (RRO)) by reading the servo sectors, wherein the servo compensation values may then be written at the end of each servo sector as extended servo data. After executing the manufacturing procedure, data may be written to the data sectors, for example, during a defect scan of the data sectors or during normal write operations while the disk drive is deployed in the field. As shown in FIG. 6B, in one embodiment when a data sector is written preceding a servo sector the data sector overwrites at least part of the extended servo preamble. In this manner, there is no gap between the data sectors and the servo sectors shown in FIG. 4. This can avoid spurious, potentially random noise that may be generated when reading such a gap, as well as avoiding the need to erase such a gap. After overwriting the beginning part of the extended servo preamble with the data of a data sector as shown in FIG. 6B, during subsequent access operations the servo gate may be opened while the read element is over the data sector as shown in FIG. 6C in order to initialize the AFE 30 of the servo read channel.

Any suitable control circuitry may be employed to implement the flow diagrams in the above embodiments, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain operations described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into a SOC.

In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.

The various features and processes described above may be used independently of one another, or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of this disclosure. In addition, certain method, event or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate. For example, described tasks or events may be performed in an order other than that specifically disclosed, or multiple may be combined in a single block or state. The example tasks or events may be performed in serial, in parallel, or in some other manner. Tasks or events may be added to or removed from the disclosed example embodiments. The example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed example embodiments.

While certain example embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions disclosed herein. Thus, nothing in the foregoing description is intended to imply that any particular feature, characteristic, step, module, or block is necessary or indispensable. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions disclosed herein.