Mapping of shingled magnetic recording media

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 61/823,241, filed on May 14, 2013, which is hereby incorporated by reference in its entirety, and hereby incorporates by reference in their entirety U.S. application Ser. No. 13/316,039, filed on Dec. 9, 2011, U.S. application Ser. No. 13/709,470, filed on Dec. 10, 2012, and U.S. application Ser. No. 12/729,159, filed on Mar. 22, 2010.

BACKGROUND

In a shingled magnetic recording (SMR) drive, data tracks are written in a partially overlapped manner to increase data density and overall drive capacity. An SMR drive may be divided into multiple shingle zones according to one approach of formatting an SMR drive. In such a case, each shingle zone has a user data area and a guardband area. Due to the overlapping nature of the written tracks, a guardband may be necessary to separate two adjacent shingle zones to prevent data corruption.

BRIEF DESCRIPTIONS OF THE DRAWINGS

The features and advantages of the implementations of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. The drawings and the associated descriptions are provided to illustrate implementations of the disclosure and not to limit the scope of what is claimed.

FIG. 1A presents a block diagram of a data storage device according to one implementation of the present disclosure;

FIG. 1B presents a diagram of hard disk platters according to one implementation of the present disclosure;

FIG. 2A presents a diagram of a simple mapping scheme according to one implementation of the present disclosure;

FIG. 2B presents a table of sector counts according to one implementation of the present disclosure;

FIG. 3A presents a conceptual diagram illustrating a count of defective sectors according to one implementation of the present disclosure;

FIG. 3B presents a defect list corresponding to the diagram of FIG. 3A according to one implementation of the present disclosure;

FIG. 4A presents a conceptual diagram of shingled tracks according to one implementation of the present disclosure;

FIG. 4B presents a diagram of a mapping scheme according to one implementation of the present disclosure;

FIG. 4C presents a diagram of mapped out zones according to one implementation of the present disclosure; and

FIG. 5 presents a flowchart of a data storage device format operation according to one implementation of the present disclosure.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth to provide a full understanding of the present disclosure. It will be apparent, however, to one of ordinary skill in the art that the various implementations disclosed may be practiced without some of these specific details. In other instances, well-known structures and techniques have not been shown in detail to avoid unnecessarily obscuring the various implementations.

FIG. 1 presents one implementation of a data storage device (DSD) 100 connected to a host 110. The host 110 may be a computer, such as a desktop, a laptop, or a mobile device. The DSD 100 includes a host interface 120, a controller 122, a voice coil motor (VCM) 130, an actuator arm 132, a head 140, and a platter 150. The DSD 100 also includes a solid state memory 124, but other implementations may not have the solid state memory 124. The solid state memory 124 may be used as an internal cache, or may be available for storing data from the host 110.

The host 110 communicates to the DSD 100 through the host interface 120. The host interface 120 communicates with the controller 122, which further communicates with the solid state memory 124 and the VCM 130. The VCM 130 operates in conjunction with the actuator arm 132 to position the head 140 over a desired track 155 of the platter 150. Although not shown in FIG. 1, another head 140 is positioned adjacent a bottom surface of the platter 150 such that both sides of the platter 150 can be utilized. Further, the DSD 100 has multiple platters 150, each having two heads 140.

To operate (i.e. read, write, etc.) on a desired location or sector of the platter 150, the VCM moves the head 140 to the desired sector. FIG. 1B illustrates how locations on the platter 150 are located. Each platter 150 has sectors 170, which are the smallest storage unit addressable by the DSD 100. The sectors 170 are numbered, starting from the index line 180 having a physical sector number (PSN) of 0. The servo track 155 is a thin, concentric circular strip of sectors 170. A cylinder 160 maps to servo tracks 155 having the same radial location on each platter 150. Because each platter 150 has two usable sides, and a head 140 for each side, identifying the head 140 will identify a specific side of a platter 150. Thus, the combination of cylinder-head-sector (CHS) locations provides an address to each physical block of data on the DSD 100. To simplify the addressing scheme, the CHS address may be mapped to absolute block addresses (ABA), which are numbered starting from 0 in one implementation. FIG. 2A presents a diagram 200 depicting how this addressing scheme may be used. In the discussion below, “sectors” and “blocks” are used interchangeably unless otherwise indicated.

In FIG. 2A, the client layer 210 corresponds to the host 110, and the media layer 220 corresponds to the DSD 100. As seen in FIG. 2A, the media layer 220 uses ABA 222 and CHS 226, whereas the client layer 210 does not. The client layer 210 instead uses a host logical block address (LBA) 215.

Defects may be present on the platters 150. In other words, certain sectors 170 may not be usable. However, ABA addressing includes all blocks, good or bad. To prevent the bad blocks from being used, another addressing scheme may be used to skip over the bad blocks. FIG. 2B presents a table 230 depicting how LBA addressing skips over bad sectors. As seen in table 230, ABA starts with 0, and assigns the next number to each consecutive block. LBA also starts with 0, but only numbers the good blocks. Because ABA 2 and 3 are bad, they are not assigned an LBA. The next LBA after 1 is assigned to ABA 4. By ABA 8, the LBA is at 4, the difference between the two also corresponding to the cumulative number of defects. The accumulated defect sector counts for a particular ABA is the push down count (PDC). Thus, the ABA can be calculated as the sum of the LBA and the PDC.

Returning to FIG. 2A, the client layer 210 uses the host LBA 215 and the media layer 220 uses the ABA 222. The host LBA 215 may map 1 to 1 with the ABA 222. In certain implementations, the host LBA 215 is the same as the ABA 222.

FIG. 3A presents a diagram 300 illustrating how a primary push down list (PDList) 350 in FIG. 3B is determined. In FIG. 3A, there are 50 bad sectors immediately preceding LBA 3000. Entry 301 in the PDList 350 stores this information. There are 300 bad sectors immediately preceding LBA 180000. However, entry 302 of the PDList 350 stores a PDC of 350 (300+50) because it tracks a cumulative count. By knowing the cumulative count, the ABA can be calculated for a given LBA. For instance, LBA 180000 maps to ABA 180350. Similarly, 23000 bad sectors precede LBA 310000, having a PDC of 23350, and 5000 bad sectors precede LBA 450000, having a PDC of 28350.

Shingled magnetic recording (SMR) can improve the density of magnetic disk storage, such as the platters 150. Writing data to a magnetic medium generally requires a stronger magnetic field than reading data. As such, the head 140 writes a wide track, but reads a narrow track. SMR takes advantage of the discrepancy between the width of the written track and the width of the read track. The tracks can be placed closer to improve density. Because only a narrow track is read, the rest of the wide written track can be overwritten while maintaining the integrity of the narrow track for reading. As long as the narrow track is not overwritten, adjacent tracks may overlap.

FIG. 4A presents a conceptual diagram 400 of shingled tracks 455. The tracks 455 overlap like roof shingles. In FIG. 4A, with no guardband in place, writing may begin with track 456, with successive tracks 455, such as track 459, overlapping the left side of the previous track. Writing may continue with the rightmost track 457, and continuing left to track 458. However, the track 456 gets overlapped on both sides, becoming unreadable. In order to preserve data integrity, the track 456 is restricted or otherwise reserved and not used, designated as a guardband.

To ensure the guardbands and other restricted areas are not used, they must be mapped out during the drive formatting process. To use conventional mapping schemes, the restricted areas may be treated as defects. However, due to the large number of shingle zones (e.g. 20,000 shingle zones), many sectors are designated as defective in such conventional mapping schemes. As a result, conventional mapping schemes would require larger tables and more processing time. For example, the guardband, or other restricted areas such as write logs can be treated as defects and added to the PDList. A write log of a track contains metadata of the written user data on that track. There may be two write logs per track for redundancy purposes. For example, one write log near the middle of a track may refer to the first half of the track, and a second write log near the end of the track may refer to the second half of the track. The host LBA would not have addresses for the restricted areas, similar to actual defects. Before the DSD 100 is used, it must build the PDList. However, because entire tracks or significant portions of tracks may be restricted, the iterative process of building the PDList becomes a time-consuming process, as each sector is essentially checked as good or bad/restricted.

FIG. 4B presents a chart 405 of a mapping scheme according to an implementation of the present disclosure. Similar to the chart 200 in FIG. 2A, a client layer 410 uses a host LBA 415, and a media layer 420 uses an ABA 422, a CHS 426, and further uses a media logical block address (MLBA) 424. However, in contrast to the chart 200, the chart 405 uses an additional layer, a shingle layer 430 using a shingle block address (SBA) 435. Similar to how LBA addresses skip over defective blocks, the SBA 435 does not assign addresses to restricted blocks. The shingle layer 430 can support a 1-to-1 mapping of addresses from the host LBA 415 to the SBA 435. The shingle layer 430 also supports a 1-to-many mapping of addresses from the host LBA 415 to the SBA 435.

FIG. 4C presents a diagram 460 of a shingle zone layout according to an implementation of the present disclosure. A logical zone 461 has shingle zone 471, shingle zone 472, and shingle zone 473. The shingle zone 471 includes a data portion 475 and a guardband 481. The shingle zone 472 has a data portion 476 and a guardband 482. The shingle zone 473 has a data portion 477 and a guardband 483. The data portions 475, 476, and 477 may be available for reading and storing data from the host. The guardbands 481, 482, and 483 are restricted.

The positions labeled with A demark the starting ABA of each shingle zone 471-473. The positions labeled with B demark the starting SBA of the shingle zones 471-473. The positions labeled C demark the starting ABA of the guardbands 481-483. Although in certain implementations MLBA or CHS are used rather than ABA, for the sake of simplicity, ABA is described in FIG. 4C. For the shingle zone 471, the ABA addresses start at A1 (0) and increment through C1 up to A2. A2 starts with the next value. However, the SBA addresses start with B1 (0), and increments through C1 (X). B2 starts with the value after C1 (X+1), skipping over the guardband 481. Likewise, B3 starts at Y+1. Thus, the restricted areas, such as the guardbands 481-483, are not assigned SBAs.

Mapping out the SBAs avoids the time-intensive process of building the PDList with restricted areas mapped as defects. The SBAs can be mapped out in a separate process. In addition, because the restricted areas are not random or nondeterministic sectors, such as defects, the process can take advantage of being able to calculate the restricted areas rather than having to iteratively inspect each sector. In other words, because SBA mapping follows a predictable pattern and defect mapping does not, separating the two mapping processes enhances the efficiency of the overall process. The mapping could also be done in the field rather than at the factory. For instance, the PDList may be rebuilt on the fly to account for new defects. The SBAs would be remapped afterwards.

FIG. 5 presents a flowchart 500 of one formatting process which can be performed by the controller 122 of the DSD 100 according to an implementation of the present disclosure. At 510, defective sectors are detected for building a PDList. This may be an iterative process of checking each sector. In other implementations, other suitable methods may be used to detect the defective sectors. In addition, this defect detection may occur at the factory during a manufacturing process, or could be initiated on the fly while in the field. At 520, the defect list is built. The PDList may be an array or matrix, such as PDList 350. In other implementations, 510 and 520 may be reversed, combined, and/or performed simultaneously.

At 530, the restricted areas are calculated. By knowing or setting various parameters, the restricted areas can be calculated. For example, if the number of good sectors, percent of sectors to use as guardbands, number of shingle zones, and number of tracks per shingle zone are known, the average shingle zone size can be calculated, and further used to calculate the guardband sizes and locations. With the parameters kept static, the guardband locations will be consistent for subsequent calculations. Taking advantage of the calculable nature of the restricted areas yields significant reductions in time over conventional mapping schemes. In other implementations, the restricted areas may be calculated by other algorithms.

At 540, the locations of the restricted areas are mapped out. For example, SBAs are mapped to good blocks, but not assigned to restricted areas. The mapping may also take advantage of the calculable nature of the restricted areas. In other implementations, 530 and 540 may be combined or performed simultaneously.

Having the restricted areas calculated for an SBA layer provides for a quicker mapping of restricted areas and does not overburden the defect detection process. In this regard, the PDList may be unsuitable for storing the guardbands and other restricted areas as defects. For example, the PDList may only hold about 30,000 entries. A DSD may have 10,000 shingle zones, each requiring two guardbands or restricted areas for a total of at least 20,000 entries as defects. Building the PDList with the guardbands as defects may take hours. In contrast, the SBA calculation may take less than a minute.

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks, modules, and processes described in connection with the examples disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. Furthermore, the foregoing processes can be embodied on a computer readable medium which causes a processor or computer to perform or execute certain functions.

To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, and modules have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those of ordinary skill in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, units, modules, and controllers described in connection with the examples disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The activities of a method or process described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The steps of the method or algorithm may also be performed in an alternate order from those provided in the examples. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable media, an optical media, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC).

The foregoing description of the disclosed example implementations is provided to enable any person of ordinary skill in the art to make or use the implementations in the present disclosure. Various modifications to these examples will be readily apparent to those of ordinary skill in the art, and the principles disclosed herein may be applied to other examples without departing from the spirit or scope of the present disclosure. The described implementations are to be considered in all respects only as illustrative and not restrictive and the scope of the disclosure is, therefore, indicated by the following claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.