Programmable device using fixed and configurable logic to implement floating-point rounding

Description

FIELD OF THE INVENTION

This invention relates to a programmable integrated circuit device, and particularly to a configurable specialized processing block in a programmable integrated circuit device.

BACKGROUND OF THE INVENTION

Considering a programmable logic device (PLD) as one example of an integrated circuit device, as applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include configurable specialized processing blocks in addition to blocks of generic programmable logic resources. Such configurable specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A configurable specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such configurable specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.

These fixed-logic elements within the configurable specialized processing blocks are interconnected by a configurable interconnect structure within the configurable specialized processing block. They may also be able to accept parameters as well as data inputs. Thus, while the elements are fixed in the type of arithmetic or logical functions that they perform, their interconnection within the block is flexible under user control, and moreover, if an element accepts parameters, then the way in which it performs its fixed function may be subject to a degree of user control. In addition, it may be possible to route the outputs of some or all of the fixed-logic elements within a block either to another fixed-logic element within the block or directly out of the block.

One particularly useful type of configurable specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations.

For example, PLDs sold by Altera Corporation, of San Jose, Calif., as part of the STRATIX® and ARRIA® families include DSP blocks, each of which includes a plurality of multipliers. Each of those DSP blocks also includes adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components of the block to be configured in different ways.

Typically, the arithmetic operators (adders and multipliers) in such configurable specialized processing blocks have been fixed-point operators. If floating-point operators were needed, the user would construct them outside the configurable specialized processing block using general-purpose programmable logic of the device, or using a combination of the fixed-point operators inside the configurable specialized processing block with additional logic in the general-purpose programmable logic.

SUMMARY OF THE INVENTION

In accordance with embodiments of the present invention, configurable specialized processing blocks such as the DSP blocks described above may be enhanced by including floating-point addition among the functions available in the DSP block. This reduces the need to construct floating-point functions outside the configurable specialized processing block. The addition function may be a wholly or partially dedicated (i.e., “hard logic”) implementation of addition in accordance with the IEEE754-1985 standard, and can be used for addition operations, multiply-add (MADD) operations, or vector (dot product) operations, any of which can be either real or complex. The floating-point adder circuit may be incorporated into the DSP Block, and can be independently accessed, or used in combination with a multiplier in the DSP block, or even multipliers in adjacent DSP blocks.

While rounding operations for the floating-point arithmetic operations in the configurable specialized processing block may be performed completely outside the configurable specialized processing block in the general-purpose programmable logic of the programmable device, in accordance with other embodiments of the invention, rounding operations may be performed partly inside the configurable specialized processing block and partly outside the configurable specialized processing block. This allows at least the portions of the rounding operations that are inefficient when performed in the general-purpose programmable logic to be performed in fixed logic.

Therefore, in accordance with embodiments of the present invention there is provided a configurable specialized processing block on a programmable integrated circuit device. The specialized processing block includes a first floating-point arithmetic operator stage, a second floating-point arithmetic operator stage, configurable interconnect within the configurable specialized processing block for routing signals into and out of each of the first and second floating-point arithmetic operator stages, and fixed rounding circuitry for performing a partial rounding operation on output of the second floating-point arithmetic operator stage. There is also provided a programmable integrated circuit device including a plurality of such configurable specialized processing blocks, with additional circuitry configured as additional rounding circuitry, as well as a method of configuring such a device.

BRIEF DESCRIPTION OF THE DRAWINGS

Further features of the invention, its nature and various advantages will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

FIG. 1 shows a logical diagram of an exemplary configurable specialized processing block incorporating an embodiment of the present invention;

FIG. 1A shows a logical diagram of an exemplary configurable specialized processing block incorporating an embodiment of the present invention;

FIG. 2 shows a more detailed diagram of an exemplary configurable specialized processing block according to an embodiment of the present invention;

FIG. 3 shows a simplified block diagram of number of exemplary configurable specialized processing blocks according to an embodiment of the present invention, in an exemplary arrangement according to an embodiment of the present invention;

FIG. 4 shows an exemplary arrangement of exemplary configurable specialized processing blocks according to an embodiment of the invention configured to perform a dot product;

FIG. 5 shows an exemplary selection of datapaths when the exemplary arrangement of FIG. 4 is used to implement a vector dot product operation;

FIG. 6 shows an exemplary dedicated floating point adder block according to an embodiment of the present invention;

FIG. 7 shows an exemplary arrangement according to an embodiment of the invention, of a plurality of exemplary dedicated floating point adder blocks of FIG. 6;

FIG. 8 shows an exemplary use of the arrangement of FIG. 8 as a ternary adder tree;

FIG. 9 shows an exemplary arrangement of exemplary configurable specialized processing blocks similar to FIG. 4 with rounding implemented outside the blocks;

FIG. 10 shows an exemplary arrangement of a first embodiment of the invention in which rounding is performed partly inside a configurable specialized processing block and partly outside a configurable specialized processing block;

FIG. 11 shows an exemplary arrangement of a second embodiment of the invention in which rounding is performed partly inside a configurable specialized processing block and partly outside a configurable specialized processing block;

FIG. 12 shows an exemplary arrangement of a third embodiment of the invention in which rounding is performed partly inside a configurable specialized processing block and partly outside a configurable specialized processing block;

FIG. 13 is a cross-sectional view of a magnetic data storage medium encoded with a set of machine-executable instructions for performing a method according to the present invention;

FIG. 14 is a cross-sectional view of an optically readable data storage medium encoded with a set of machine-executable instructions for performing a method according to the present invention; and

FIG. 15 is a simplified block diagram of an exemplary system employing a programmable logic device incorporating the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows a logical diagram of an exemplary DSP block 100 according to an embodiment of the invention. In this logical representation, implementational details, such as registers and some programmable routing features—such as multiplexers that may allow the output of a particular structure to be routed directly out of block 100—are omitted to simplify discussion. In addition, some elements that are shown may, in an actual embodiment, be implemented more than once. For example, the multiplier 101 may actually represent two or more multipliers, as in the DSP blocks of the aforementioned STRATIX® and ARRIA® families of PLDs.

In the logical representation of FIG. 1, the floating-point adder 102 follows a floating-point multiplier 101. The floating-point multiplier may be constructed from a 27×27 fixed-point multiplier supported by the DSP block provided in STRATIX® V or ARRIA® V programmable devices from Altera Corporation, and some additional logic. The additional logic calculates exponents, as well as special and error conditions such as NAN (not-a-number), Zero and Infinity. Optionally, other logic may be provided to round the result of the multiplier to IEEE754 format. Such rounding can be implemented as part of the final carry-propagate adder within the multiplier structure (not shown), or in programmable logic outside the DSP block 100 when the output of the multiplier 101 is outputted directly from the DSP block 100.

The floating point multiplier 101 can feed the floating point adder 102 directly in a multiplier-add (MADD) mode, as depicted in FIG. 1. Alternatively, as depicted in FIG. 1A, the multiplier 101 output can be routed around the adder 102 directly to the output of the DSP block, with a multiplexer 103 provided to select between the output of the multiplier 101 or the output of the adder 102. Although the bypass 104 and multiplexer 103 are omitted from the other drawings to avoid cluttering those drawings, they should be considered to be present in all of the multiplier/adder DSP blocks shown, including that of FIG. 1.

FIG. 2 shows a more detailed diagram of an exemplary DSP block 200 according to an embodiment of this invention. Optionally bypassable pipelining (not shown) may be provided between the floating-point multiplier 101 and the floating-point adder 102. Optionally bypassable pipelining (not shown) can also be provided within either or both of the floating-point multiplier 101 and the floating-point adder 102. Inputs can be routed to the adder 102 from multiple sources, including an output of the multiplier 101, one of the inputs 201 to the DSP block 200, or a direct connection 202 from an adjacent similar DSP block 200.

In addition, the output of multiplier 101 and/or one of the inputs 201 to the DSP block 200, can also be routed via a direct connection 212 to the adder in an adjacent similar DSP block 200 (it being apparent that, except at the ends of a chain of blocks 200, each direct connection 202 receives its input from a direct connection 212, and that each direct connection 212 provides its output to a direct connection 202). Specifically, multiplexer 211 may be provided to select either input 201 or direct connection 202 as one input to adder 102. Similarly, multiplexer 221 may be provided to select either input 201 or the output of multiplier 101 as another input to adder 102. A third multiplexer 231 may be provided to select either input 201 or the output of multiplier 101 as the output to direct connection 212. Thus the inputs to adder 102 can be either input 201 and the output of multiplier 101, or input 201 and direct connection 202, and direct connection 212 can output either input 201 or the output of multiplier 101.

In one embodiment, multiplexer 221 and multiplexer 231, which have the same two inputs (input 201 and the output of multiplier 101), share a control signal, but in the opposite sense as indicated at 241, so that if one of the two multiplexers selects one of those two inputs, the other of the two multiplexers selects the other of those two inputs.

Multiple DSP blocks according to embodiments of the invention may be arranged in a row or column, so that information can be fed from one block to the next using the aforementioned direct connections 202/212, to create more complex structures. FIG. 3 shows a number of exemplary DSP blocks 301 according to an embodiment of the invention, arranged in a row 300 (without showing connections 202/212).

FIG. 4 shows a row 400 of five exemplary DSP blocks 401-405 according to an embodiment of the invention configured to perform a dot product operation. Alternatively, the DSP blocks 401 in that configuration could be arranged in a column (not shown) without changing the inputs and outputs. The drawing shows the interface signals. In each pair of blocks 401/402 and 403/404, the multiplier 101 in each block, along with the adder 102 in the leftmost block 401, 403 of the two blocks, implement a respective sum 411, 412 of two multiplication operations. Those sums 411, 412 are summed with the rightmost adder of the leftmost pair—i.e., adder 102 of DSP block 402—using multiplexer 211 to select input 202 and using multiplexer 221 to select input 201 (to which the respective output 411/412 has been routed, e.g., using programmable interconnect resources of the PLD outside the blocks 401-404)—to provide a sum of four multiplies. The rightmost adder of the rightmost pair—i.e., adder 102 of DSP block 404 is used to add this sum of four multiplies to the sum of four multiplies from another set of four DSP blocks beginning with DSP block 405 (remainder not shown). For N multipliers there will be N adders, which is sufficient to implement the adder tree of a dot product, which, for a pair of vectors of length N, is the sum of N multiplication operations.

The same DSP block features can be used to implement a complex dot product. Each second pair of DSP blocks would use a subtraction rather than an addition in the first level addition, which can be supported by the floating-point adder (e.g., by negating one of the inputs, in a straightforward manner). The rest of the adder tree is a straightforward sum construction, similar to that described in the preceding paragraph.

For the illustrated method of adder tree implementation, each DSP block output other than the output of the last block is fed back to the input of another DSP block. In some cases the output is fed back to an input of the same block, such as the EF+GH output 412 in FIG. 4. As seen in FIG. 2, an internal bus 250 may be provided to feed the output register of a block back to an input register, saving routing resources in the general-purpose programmable logic portion of the device. FIG. 5 shows in phantom an exemplary selection of datapaths by multiplexers 211, 221, 231 for the dot product application example described earlier in connection with FIG. 4, showing how adder 102 of each block 401-405 adds a product of the multiplier 101 in that block and a product from an adjacent block.

Another embodiment of a dedicated floating-point processing block is a dedicated floating-point adder block. Such a block can be binary (2 input operands) or ternary (3 input operands). FIG. 6 shows a logical block diagram of an exemplary ternary adder block 600. As with the previously described DSP block, pipelining may or may not be used internally, and rounding may be supported either internally or externally in programmable logic. Also as with the DSP block, the adder blocks can be arranged in rows, as shown in the example in FIG. 7, or columns. Alternatively, adder blocks can be interleaved (not shown) with the multiplier-adder DSP blocks described above.

FIG. 8 shows, using labels, exemplary connections used with blocks 600 arranged as in FIG. 7 to make a ternary floating-point adder tree. The ternary adder tree has a depth of log₃ N, which is half that of a binary adder. In this example, N=9, and four blocks are arranged in two levels (depth=log₃(9)=2).

As discussed above, IEEE754-compliant rounding can be provided inside embodiments of the DSP block, or can be implemented in the general-purpose programmable logic portion of the device. FIG. 9 shows as an example the arrangement of FIG. 4 with rounding implemented at 910 outside the block—i.e., in the general-purpose programmable logic portion of the device. The rounding can be implemented with a single level of logic, which may be as simple as a carry-propagate adder, followed by a register. Assuming, as is frequently the case, that all of the outputs of the DSP blocks must be rounded, there would be no disturbance or rebalancing of the datapath required.

As further discussed above, rounding can be implemented partly inside the configurable specialized processing block and partly outside the configurable specialized processing block in the general-purpose programmable logic. Generally, portions of the rounding circuitry that are difficult or inefficient to implement in general-purpose programmable logic could be implemented in fixed logic in a configurable specialized processing block, while other portions of the rounding circuitry could be implemented in the general-purpose programmable logic. Three variants of such a scenario are illustrated in FIGS. 10-12.

In a first variant shown in FIG. 10, portion 1001 of rounding circuitry 1000 is located within configurable specialized processing block 1010, while portion 1002 of rounding circuitry 1000 is located outside configurable specialized processing block 1010, in the general-purpose programmable logic. Portion 1001 is focused on calculation of an overflow condition of the output value, while portion 1002 calculates the value of a final exponent, as well as special or error conditions based on the overflow condition or lack thereof.

Specifically, register 1011 contains the mantissa of the final value calculated in configurable specialized processing block 1010—the final addition result—including normalized mantissa bits having a least-significant bit (LSB), as well as round (R), guard (G) and “sticky” (S) bits beyond the least significant bit, prior to rounding. Register 1012 contains the normalized exponent bits prior to rounding.

“Round” circuit 1013 determines, based on the least-significant, round, guard and sticky bits, whether or not rounding is needed. For example, one condition in which rounding is not needed is where LSB, R, G and S are all ‘0’. Output 1014 of circuit 1013 is routed to circuitry 1002 outside block 1010, and also to overflow detection circuitry 1015 inside block 1010. Overflow detection circuitry 1015 may be implemented, as shown, by AND-gate 1016 that ANDs all of the normalized mantissa bits down to the LSB. If all of those bits are ‘1’, there may be an overflow if there is rounding, so AND-gate 1016 outputs a ‘1’ and otherwise outputs a ‘0’. That output is ANDed at 1017 with the round output 1014 and if the result is a ‘1’, there is an overflow, so that ‘1’ is added at 1018, outside block 1010, to the previously calculated exponent to yield rounded exponent 1019. AND-gates 1016 and 1017 can be replaced with a single larger AND-gate (not shown).

Round output 1014 also is added outside block 1010 in adder 1020, to the normalized mantissa bits to yield rounded mantissa 1021. Rounded mantissa 1021 and rounded exponent 1019 are input to exception handling circuitry 1022 which determines, e.g., whether the result has an absolute value greater than the largest representable number (2¹²⁷ in IEEE754 single-precision arithmetic), and therefore should be set to ±∞, or whether the result has an absolute value smaller than the smallest representable number (2⁻¹²⁶ in IEEE754 single-precision arithmetic), and therefore should be set to ‘0’. The result is the final output mantissa 1023 and final output exponent 1024.

Other exception conditions may also be determined, such as NaN (not a number), but may require additional inputs. For example, an NaN condition is frequently the result of invalid inputs to the operators, so those inputs may also need to be provided directly (not shown) to exception handling circuitry 1022 in addition to being provided to the operators. Similarly, in the case of an NaN condition, the mantissa and exponent outputs 1023, 1024 would be meaningless and a separate NaN output (not shown) from exception handling circuitry 1022 might be provided.

In a second variant shown in FIG. 11, portion 1101 of rounding circuitry 1100 is located within configurable specialized processing block 1010, while portion 1102 of rounding circuitry 1100 is located outside configurable specialized processing block 1010, in the general-purpose programmable logic. Portion 1101 is similar to portion 1001 in FIG. 10, except that exponent adder 1018 has been moved inside block 1010 as part of portion 1101. This is possible because the number of bits in the exponent is much smaller than the number of bits in the mantissa, so that unlike adder 1020, adder 1018 can be efficiently implemented inside block 1010. To maintain timing, rounded exponent register 1019 also is moved into portion 1101 inside block 1010.

In a third variant shown in FIG. 12, portion 1201 of rounding circuitry 1200 is located within configurable specialized processing block 1010, while portion 1202 of rounding circuitry 1200 is located outside configurable specialized processing block 1010, in the general-purpose programmable logic. In this variant, exception handling 1022 as well as final exponent register 1024 are moved into portion 1201 inside block 1010, while only mantissa adder 1020 and final mantissa register 1023 remain in portion 1202 in the general-purpose programmable logic. Multiplexers 1211 and 1221 determine whether the rounded mantissa data or the exception values are output to adder 1020.

By providing configurable specialized processing blocks, including dedicated but configurable floating point operators, the present invention allows the implementation of certain operations, such as the vector dot product described above, with less reliance on programmable logic outside the blocks.

Instructions for carrying out a method according to this invention for programming a programmable device may be encoded on a machine-readable medium, to be executed by a suitable computer or similar device to implement the method of the invention for programming or configuring PLDs or other programmable devices. For example, a personal computer may be equipped with an interface to which a PLD can be connected, and the personal computer can be used by a user to program the PLD using suitable software tools.

FIG. 13 presents a cross section of a magnetic data storage medium 1300 which can be encoded with a machine executable program that can be carried out by systems such as the aforementioned personal computer, or other computer or similar device, or encoded with a library of virtual fabrics. Medium 1300 can be a floppy diskette or hard disk, or magnetic tape, having a suitable substrate 1301, which may be conventional, and a suitable coating 1302, which may be conventional, on one or both sides, containing magnetic domains (not visible) whose polarity or orientation can be altered magnetically. Except in the case where it is magnetic tape, medium 1300 may also have an opening (not shown) for receiving the spindle of a disk drive or other data storage device.

The magnetic domains of coating 1302 of medium 1300 are polarized or oriented so as to encode, in manner which may be conventional, a machine-executable program, for execution by a programming system such as a personal computer or other computer or similar system, having a socket or peripheral attachment into which the PLD to be programmed may be inserted, to configure appropriate portions of the PLD, including its configurable specialized processing blocks, if any, in accordance with the invention.

FIG. 14 shows a cross section of an optically-readable data storage medium 1310 which also can be encoded with such a machine-executable program, which can be carried out by systems such as the aforementioned personal computer, or other computer or similar device, or encoded with a library of virtual fabrics. Medium 1310 can be a conventional compact disk read-only memory (CD-ROM) or digital video disk read-only memory (DVD-ROM) or a rewriteable medium such as a CD-R, CD-RW, DVD-R, DVD-RW, DVD+R, DVD+RW, or DVD-RAM or a magneto-optical disk which is optically readable and magneto-optically rewriteable. Medium 1310 preferably has a suitable substrate 1311, which may be conventional, and a suitable coating 1312, which may be conventional, usually on one or both sides of substrate 1311.

In the case of a CD-based or DVD-based medium, as is well known, coating 1312 is reflective and is impressed with a plurality of pits 1313, arranged on one or more layers, to encode the machine-executable program. The arrangement of pits is read by reflecting laser light off the surface of coating 1312. A protective coating 1314, which preferably is substantially transparent, is provided on top of coating 1312.

In the case of a magneto-optical disk, as is well known, coating 1312 has no pits 1313, but has a plurality of magnetic domains whose polarity or orientation can be changed magnetically when heated above a certain temperature, as by a laser (not shown). The orientation of the domains can be read by measuring the polarization of laser light reflected from coating 1312. The arrangement of the domains encodes the program as described above.

A PLD 90 incorporating configurable specialized processing blocks according to the present invention may be used in many kinds of electronic devices. One possible use is in an exemplary data processing system 900 shown in FIG. 15. Data processing system 900 may include one or more of the following components: a processor 901; memory 902; I/O circuitry 903; and peripheral devices 904. These components are coupled together by a system bus 905 and are populated on a circuit board 906 which is contained in an end-user system 907.

System 900 can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD 90 can be used to perform a variety of different logic functions. For example, PLD 90 can be configured as a processor or controller that works in cooperation with processor 901. PLD 90 may also be used as an arbiter for arbitrating access to a shared resources in system 900. In yet another example, PLD 90 can be configured as an interface between processor 901 and one of the other components in system 900. It should be noted that system 900 is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims.

Various technologies can be used to implement PLDs 90 as described above and incorporating this invention.

It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the various elements of this invention can be provided on a PLD in any desired number and/or arrangement. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims that follow.