Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration

Description

BACKGROUND

1. Field

This disclosure relates generally to non-volatile memory (NVM) cells and other transistor types, and more particularly, integrating NVM cells with logic transistors that have high k gate dielectrics and metal gates and transistors that are high voltage.

2. Related Art

The integration of non-volatile memories (NVMs) with logic transistors has always been a challenge due to the different requirements for the NVM transistors, which store charge, and the logic transistors which are commonly intended for high speed operation. The need for storing charge has been addressed mostly with the use of floating gates but also with nanocrystals or nitride. In any of these cases, the need for this unique layer makes integration of the NVM transistors and the logic transistors difficult. The particular type of charge storage layer can also have a large effect on the options that are available in achieving the integration. A further complication is when the logic transistors are high k, metal gate transistors and high voltage transistors. The high k gate dielectrics typically cannot withstand the high temperatures that are generally best for NVM cells and for high voltage transistors. Further the high voltage transistors typically have relatively thick layers of oxide for the gate dielectrics that, when etched, can cause a corresponding recess of the isolation oxide exposing the sidewall surface of logic transistor channel regions. The exposure of the transistor region sidewall surface makes it difficult to control the threshold voltage of the transistors and accordingly makes for a leakage problem for those transistors.

Accordingly there is a need to provide an integration that improves upon one or more of the issues raised above.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

FIG. 1 is a cross section of a semiconductor structure having a non-volatile memory (NVM) structure and a logic transistor structure at a stage in processing according to an embodiment;

FIG. 2 is a cross section of the semiconductor structure of FIG. 1 at a subsequent stage in processing;

FIG. 3 is a cross section of the semiconductor structure of FIG. 2 at a subsequent stage in processing;

FIG. 4 is a cross section of the semiconductor structure of FIG. 3 at a subsequent stage in processing;

FIG. 5 is a cross section of the semiconductor structure of FIG. 4 at a subsequent stage in processing;

FIG. 6 is a cross section of the semiconductor structure of FIG. 5 at a subsequent stage in processing;

FIG. 7 is a cross section of a semiconductor structure at a stage in processing according to a second embodiment;

FIG. 8 is a cross section of the semiconductor structure of FIG. 7 at a subsequent stage in processing;

FIG. 9 is a cross section of the semiconductor structure of FIG. 8 at a subsequent stage in processing;

FIG. 10 is a cross section of the semiconductor structure of FIG. 9 at a subsequent stage in processing;

FIG. 11 is a cross section of the semiconductor structure of FIG. 10 at a subsequent stage in processing;

FIG. 12 is a cross section of the semiconductor structure of FIG. 11 at a subsequent stage in processing;

FIG. 13 is a cross section of the semiconductor structure of FIG. 12 at a subsequent stage in processing;

FIG. 14 is a cross section of the semiconductor structure of FIG. 13 at a subsequent stage in processing;

FIG. 15 is a cross section of the semiconductor structure of FIG. 14 at a subsequent stage in processing;

FIG. 16 is a cross section of the semiconductor structure of FIG. 15 at a subsequent stage in processing;

FIG. 17 is a cross section of the semiconductor structure of FIG. 16 at a subsequent stage in processing;

FIG. 18 is a cross section of the semiconductor structure of FIG. 17 at a subsequent stage in processing; and

FIG. 19 is a cross section of the semiconductor structure of FIG. 18 at a subsequent stage in processing.

DETAILED DESCRIPTION

In one aspect, an integration of a non-volatile memory (NVM) cell in a NVM portion of an integrated circuit and a logic transistor in a logic portion of the integrated circuit includes forming the gate structure of the NVM cell in the NVM portion, including the charge storage layer, while masking the logic portion. The logic gate is formed while masking the NVM portion with a hard mask that is subsequently used to form sidewall spacers in the NVM portion. Source/drain implants are performed simultaneously in the NVM and logic portions. This is better understood by reference to the drawings and the following written description.

The semiconductor substrate described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOD, silicon, monocrystalline silicon, the like, and combinations of the above. Oxide layer refers to a silicon oxide layer unless otherwise noted. Similarly, nitride layer refers to a silicon nitride layer unless otherwise noted.

Shown in FIG. 1 is a semiconductor structure 10 of an integrated circuit having a substrate 12, an isolation region 14 in substrate 12, an isolation region 16 in substrate 12, an isolation region 18 in substrate 12, an isolation region 20 in substrate 12, and an isolation region 22 in substrate 12. An NVM portion 24 is between isolation regions 14 and 16, a first high voltage portion 26 is between isolation regions 16 and 18, a second high voltage portion 28 is between isolation regions 18 and 20, and a logic portion 30 is between isolation regions 20 and 22. Substrate 12 has a well 32 in NVM portion 24, a well 34 in first and second high voltage portions 26 and 28, and a well 36 in logic portion 30. Wells 32, 34 and 36 may be P type wells and substrate 12 may be P type. N type wells, not shown, may also be present.

Shown in FIG. 2 is semiconductor structure 10 after growing an oxide layer 38 on substrate 12 in NVM portion 24, an oxide layer 40 on substrate 12 in first high voltage portion 26, an oxide layer 42 on substrate 12 in second high voltage portion 28, an oxide layer 44 on substrate 12 in logic portion 30, a polysilicon layer 46 on isolation regions 14, 16, 18, 20, and 22 and on oxide layers 38, 40, 42, and 44, which are relatively thin and may be about 30 Angstroms thick. Oxide layers are grown to be high quality and be grown at a temperature of 900 degress Celsius or even more. Polysilicon layer 46 may be about 600 Angstroms thick.

Shown in FIG. 3 is semiconductor structure 10 after patterning polysilicon layer 46 to leave a portion of polysilicon layer 46 over oxide layer 38 and portions of isolation regions 14 and 16 and to leave a portion of polysilicon layer 46 over oxide layer 44 and portions of isolation regions 20 and 22. This patterning, as is common for patterned etches, uses photoresist as a mask.

Shown in FIG. 4 is semiconductor structure 10 after removing oxide layers 40 and 42 and growing oxide layers 48 and 50 to about 100 Angstroms. With oxide layers 40 and 42 being thin, there is minimal impact on isolation regions 16, 18, and 20 due to the etch that removes oxide layers 40 and 42. Isolation regions 16, 18, and 20, as well as isolation regions 14 and 22, may be about 2500 Angstroms deep. Further, the oxide growth of oxide layers 48 and 50 consumes some of substrate 12 where they are grown. The effect is that the top surface of substrate 12 in high voltage portions 26 and 28 remains nearly coplanar with isolation region 18 and the portions of isolation regions 16 and 20 interfacing with high voltage portions 26 and 28. During the growth of oxide layers 48 and 50, an oxide layer 52 is grown on the portion of polysilicon layer 46 in NVM portion 24, and an oxide layer 54 is grown on the portion of polysilicon layer 46 in logic portion 30.

Shown in FIG. 5 is semiconductor structure 10 after performing a patterned etch of oxide layer 50, 52 and 54. This leaves oxide layer 48 in first high voltage portion 26.

Shown in FIG. 6 is semiconductor structure 10 after growing an oxide layer 60 on the top surface of substrate 12 in second high voltage portion 28 and also growing additional oxide in the first high voltage portion 26 to result in oxide layer 58 that is thicker than oxide layer 48 of first high voltage portion 26 and thicker than oxide layer 60. Oxide layer 60 may be grown to be 125 Angstroms so that the resulting thickness of oxide layer 58 is about 200 Angstroms. The growth rate of oxide decreases as the thickness increases. This oxide growth thickens oxide layers 56 and 62 also. Some consumption of the top surface of substrate 12 in high voltage portions 26 and 28 occurs. Immediately prior to this oxide growth is a pre-clean which will etch exposed oxide. During this pre-clean, isolation regions 14 and 16, where they meet with the top surface of substrate 12 in NVM portion 24, and isolation regions 20 and 22, where they meet with the top surface of substrate 12 in logic portion 30, are protected by the remaining portions of polysilicon layer 46. With oxide layer 58 being thicker than oxide layer 60, second high voltage portion 28 may be considered a medium voltage portion.

Shown in FIG. 7 is semiconductor structure 10 after performing a patterned etch to remove oxide layers 56 and 62 and the remaining portions of polysilicon layer 46. During this etch, isolation regions 16 and 18, where they meet with the top surface of substrate 12 in first high voltage portion 26, and isolation regions 18 and 20, where they meet with the top surface of substrate 12 in second high voltage portion 28, are protected using a photoresist mask.

Shown in FIG. 8 is semiconductor structure 10 after pattern etching to remove oxide layers 38 and 44 which are both quite thin, only about 30 Angstroms. A growth of oxide is then performed on NVM portion 24, high voltage portions 26 and 28, and logic portion 30. The result is an oxide layer 64 in NVM portion 24 and an oxide layer 70 in logic portion 30 both of about 26 to 32 Angstroms in thickness. This causes a further growth of oxide in high voltage portions 26 and 28 of about 15 to 20 Angstroms to result in oxide layer 66 in first high voltage portion 26 and oxide layer 68 in second high voltage portion 28.

Shown in FIG. 9 is semiconductor structure 10 after depositing a polysilicon layer 72 in NVM portion 24, high voltage portions 26 and 28, and logic portion 30 to cover oxide layers 64, 66, 68, and 70 and isolation portions 14, 16, 18, 20, and 22. Polysilicon layer 72 may be about 800 Angstroms in thickness.

Shown in FIG. 10 is semiconductor structure 10 after forming a patterned photoresist layer 74 over high voltage portions 26 and 28 and logic portion 30 and performing an implant so as to form a doped polysilicon layer 78 from polysilicon layer 72. This ensures that control gates subsequently formed from doped polysilicon layer 78 will be sufficiently conductive.

Shown in FIG. 11 is semiconductor structure 10 after doped polysilicon layer 78 is patterned to form a first select gate from the portion of doped polysilicon layer 78 nearer isolation region 14 and a second select gate from the portion of doped polysilicon layer 78 nearer isolation region 16.

Shown in FIG. 12 is semiconductor structure 10 after forming a charge storage layer 80 in NVM portion 24, high voltage portions 26 and 28, and logic portion 30. Charge storage layer 80 is formed from a bottom oxide 82, a plurality of nanocrystals of which nanocrystal 84 is representative, and a top oxide 86 that is between and over the nanocrystals. Charge storage layer is over polysilicon layer 72 in high voltage portions 26 and 28 and in logic portion 30. In NVM portion 24, charge storage layer 80 is over, between, along the sidewalls of the first and second select gates formed from doped polysilicon layer 78. Charge storage layer is over substrate 12 in NVM portion 24 in the regions between the isolation regions 14 and 16 and the select gates formed from doped polysilicon layer 78.

Shown in FIG. 13 is semiconductor structure 10 after depositing a polysilicon layer 88 over charge storage layer 80 in NVM portion 24, high voltage portions 26 and 28, and logic portion 30.

Shown in FIG. 14 is semiconductor structure 10 after a pattered etch of polysilicon layer 88 and charge storage layer 80 to form control gate by leaving a first portion of polysilicon layer 88 as a control gate over and along a right side the first portion of polysilicon layer 78 and a second portion of polysilicon layer 88 over and along a left side of the second portion of polysilicon layer 78. Polysilicon layer 88 is removed over high voltage portions 26 and 28 and logic portion 30. The first portion of polysilicon layer 88 extends laterally to right from the first portion of polysilicon layer 78, and the second portion of polysilicon layer 88 extends laterally to the left from the second portion of polysilicon layer 78. Charge storage layer 80 is between the first portions of polysilicon layers 78 and 88 and between the second portions of polysilicon layers 78 and 88. The result is two gate stacks each of a select gate over oxide layer 64, a control gate having a portion over charge storage layer where charge storage layer is on the top surface of substrate 12, a portion along one side of the select gate, and a portion over a top portion of the select gate in which charge storage layer is between the select gate and the control gate.

Shown in FIG. 15 is semiconductor structure 10 after a patterned etch of polysilicon layer 72 to leave a portion in first high voltage portion 26 as a gate for a high voltage transistor and a portion in second high voltage portion 28 as a gate for a high voltage transistor. Oxide layer 66 is the gate dielectric for the high voltage transistor of first high voltage portion 26 and oxide layer 68 is the gate dielectric for the high voltage transistor of second high voltage portion 28. Polysilicon layer 72 remains over logic portion 30. Thus the gate structures for NVM portion 24 and high voltage portions 26 and 28 are completed.

Shown in FIG. 16 is semiconductor structure 10 after depositing an oxide layer 90, a nitride layer 92, and an oxide layer 94 and then patterning to remove oxide layer 90, nitride layer 92, oxide layer 94, and polysilicon layer 72 from logic portion 30. Oxide layer 90 has a thickness chosen for forming a sidewall spacer that will function as a mask for an extension implant. The result is that the gate structures for NVM portion 24 and high voltage portions 26 and 28 are protected by oxide layer 90, nitride layer 92, and oxide layer 94 and logic portion 30 only has oxide layer 70 which is easily removed by a preclean which also removes oxide layer 94.

Shown in FIG. 17 is semiconductor structure 10 after forming a gate structure 96 having a high k dielectric 98, a work function metal 100, and an upper gate 102 that may be polysilicon. This shows completed gate structures for NVM portion 24, high voltage portions 26 and 28, and logic portion 30. These are achieved with etches that only minimally impact the portions of isolation regions 20 and 22 that adjoin well 36. After the removal oxide layer 70, there are no oxide etches required to reach the result shown in FIG. 17. Beginning with the coplanar structure shown in FIG. 1, the only oxide etches that contact isolation regions 20 and 22 where they adjoin well 36 prior to the formation of gate structure 96 are the ones that remove oxide layer 44 and oxide layer 70 both of which are quite thin and have little impact on the coplanarity between the top surface of substrate 12 in logic portion 30 and the top surfaces of isolation regions 20 and 22. After formation of gate structure 96, the oxide etches that may impact isolation regions 20 and 22 have minimal impact because the gate has already crossed the isolation region so that subsequent etches have minimal if any impact on the type of leakage caused by the etching that results in a significant deviation from coplanarity between isolation regions and active regions. The areas of wells 32, 34, and 36 at and near the surface may be considered active regions.

Shown in FIG. 18 is semiconductor structure 10 after forming sidewall spacers around the gate structures of NVM portion 24 and high voltage portions 26 and 28 using oxide layer 90 as shown in FIGS. 17 and 18. Prior to formation of sidewall spacers from oxide layer 90, a nitride layer and an oxide layer is deposited for use in forming a sidewall spacer 104 of nitride around gate structure 96 and a sidewall spacer 106 of oxide around sidewall spacer 104.

Shown in FIG. 19 after performing extension implants; forming sidewall spacers 108 of oxide around the gate structures of NVM portion 24, high voltage portions 26 and 28, and a logic portion 30; and performing deep source/drain implants. These source/drain implants are effective in making the gates sufficiently conductive. The result is source/drain regions 110, 112, and 114 in NVM portion 24; source/drain regions 115 and 116 in first high voltage portion 26; source/drain regions 118 and 120 in second high voltage portion 28; and source/drain regions 122 and 124 in logic portion 30.

The structure shown in FIG. 15 shows how gates, including gates with varying thicknesses of grown oxide, can be achieved with minimal effect on the isolation regions defining a perimeter of a logic transistor to be formed using a high k dielectric for the gate dielectric and metal directly on the gate dielectric. The most likely oxides to cause a major deviation from coplanarity between active and isolation are the ones for forming thick oxides for high voltage operation which in this case are oxides 66 and 68. Corresponding oxides were not grown in logic portion 30. Also the etching of these oxides were blocked at the active/isolation interface for logic portion 30.

By now it should be appreciated that there has been provided a method of making a semiconductor device. The method includes using a substrate having a non-volatile memory (NVM) portion, a high voltage portion, a medium voltage portion, and a logic portion. The method further includes growing a first oxide on a major surface of the substrate in the NVM portion, the high voltage portion, the medium voltage portion, and logic portion. The method further includes depositing a first conductive layer over the first oxide in the NVM portion, the high voltage portion, the medium voltage portion, and the logic portion. The method further includes patterning and etching the first conductive layer to expose the high voltage portion and the medium voltage portion. The method further includes growing a second oxide in the NVM portion, the high voltage portion, the medium voltage portion, and the logic portion. The method further includes masking the high voltage portion. The method further includes etching the second oxide from the NVM portion, medium voltage portion, and the logic portion while the high voltage portion is masked. The method further includes growing a third oxide in the NVM portion, the high voltage portion, the medium voltage portion, and the logic portion. The method further includes masking the high voltage portion and the medium voltage portion. The method further includes etching the third oxide and the first conductive layer in the NVM portion and the logic portion while the high voltage portion and the medium voltage portion remain masked. The method further includes growing a fourth oxide in the NVM portion, the high voltage portion, the medium voltage portion, and the logic portion. The method further includes fabricating a memory cell requiring high voltage during operation in the NVM portion, the fabricating including using a protective layer over the high voltage portion, the medium voltage portion, and the logic portion when performing an implant in a second conductive layer in the NVM portion. The method further includes removing the protective layer over the high voltage portion, the medium voltage portion, and the logic portion. The method further includes patterning transistor gates in the high voltage portion and the medium voltage portion. The method further includes depositing a protective mask in the NVM portion, the high voltage portion, and the medium voltage portion. The method further includes forming a logic device in the logic portion while the protective mask remains in the NVM portion, the high voltage portion, and the medium voltage portion. The method may have a further characterization by which the fabricating the memory cell further includes forming a select gate by implanting the second conductive layer and patterning the second conductive layer and the fourth oxide, forming a charge storage layer over the select gate and the substrate in the NVM portion, and in the high voltage portion, the medium voltage portion, and the logic portion, depositing a third conductive layer over the charge storage layer in the NVM portion, the high voltage portion, the medium voltage portion, and the logic portion, and patterning the third conductive layer and the charge storage layer to form a control gate over a remaining portion of the charge storage layer and a portion of the select gate in the NVM portion, and to remove the charge storage layer and the third conductive layer in the high voltage portion, the medium voltage portion, and the logic portion. The method may have a further characterization by which. The method may have a further characterization by which the charge storage layer includes one of a group consisting of discrete storage elements between top and bottom layers of dielectric and a continuous storage element between top and bottom layers of dielectric. The method may have a further characterization by which the protective layer includes photoresist. The method may have a further characterization by which the protective mask includes a nitride layer and an oxide layer. The method may have a further characterization by which the forming the logic device includes forming a high k dielectric over the logic portion, forming a barrier layer over the high k dielectric, and patterning the barrier layer. The method may have a further characterization by which the forming the logic device further includes forming a polysilicon layer over the barrier layer and patterning the polysilicon layer and the high k dielectric, wherein the patterning the polysilicon layer and the high k dielectric is aligned with the patterning the barrier layer to leave a gate stack. The method may have a further characterization by which the fabricating the memory cell further includes depositing a layer of polysilicon for the third conductive layer. The method may have a further characterization by which the second oxide is grown on the first conductive layer in the NVM portion and the logic portion.

Also disclosed is a method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a first high voltage portion, a second high voltage portion and a logic portion. The method includes forming a first conductive layer over an oxide layer on a major surface of the substrate in the NVM portion, the first and second high voltage portions, and logic portion. The method further includes fabricating a memory cell in the NVM portion while the first conductive layer remains in the first and second high voltage portions and the logic portion. The method further includes patterning the first conductive layer to form transistor gates in the first and second high voltage portions. The method further includes forming a protective mask over the NVM portion and the first and second high voltage portions. The method further includes forming a transistor gate in the logic portion while the protective mask remains in the NVM portion and the first and second high voltage portions. The method may have a further characterization by which the fabricating the memory cell further includes forming a select gate by implanting a portion of the first conductive layer and patterning the first conductive layer, and forming a charge storage layer over the select gate and the substrate in the NVM portion, and in the first and second voltage portions, and the logic portion, depositing a second conductive layer over the charge storage layer in the NVM portion, the first and second high voltage portions, and the logic portion, patterning the second conductive layer and the charge storage layer to form a control gate over a remaining portion of the charge storage layer and a portion of the select gate in the NVM portion, and to remove the charge storage layer and the second conductive layer in the first and second high voltage portions and the logic portion. The method may have a further characterization by which the charge storage layer includes one of a group consisting of discrete storage elements between top and bottom layers of dielectric and a continuous storage element between top and bottom layers of dielectric. The method may have a further characterization by which the patterning the first conductive layer for the fabricating the memory cell and the patterning the first conductive layer to form the transistor gates in the first and second high voltage portions is performed concurrently. The method may have a further characterization by which the fabricating the memory cell includes patterning the first conductive layer to form a gate for the memory cell, and the patterning the first conductive layer to form the transistor gates in the first and second high voltage portions is performed concurrently with the patterning the first conductive layer to form the gate for the memory cell. The method may have a further characterization by which the protective mask includes a nitride layer and an oxide layer. The method may have a further characterization by which the forming the transistor gate includes forming a high k dielectric, forming a barrier layer over the high k dielectric, forming a polysilicon layer over the barrier layer, and patterning the high k dielectric, the barrier layer, and the polysilicon layer. The method may have a further characterization by which the first conductive layer is a layer of polysilicon. The method may have a further characterization by which the fabricating includes using a protective layer over the first and second high voltage portions and the logic portion when performing an implant in a second conductive layer in the NVM portion. The method may further include, before fabricating the memory cell, patterning and etching the first conductive layer to expose the first and second high voltage portions, growing a second oxide in the NVM portion, the first and second high voltage portions, and the logic portion, masking a first of the high voltage portions, etching the second oxide from the NVM portion, a second of the high voltage portions, and the logic portion while the first of the high voltage portions is masked, growing a third oxide in the NVM portion, the first and second high voltage portions, and the logic portion, masking the first and second high voltage portions, etching the third oxide and the first conductive layer in the NVM portion and the logic portion while the first and second high voltage portions remain masked, and growing a fourth oxide in the NVM portion, the first and second high voltage portions, and the logic portion.

Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, different or additional types of active regions may be used such as further levels of high voltage and different well types and corresponding transistor types. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.

Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.