Power management for data storage device

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. Provisional Application No. 61/859,452, filed on Jul. 29, 2013, which is hereby incorporated by reference in its entirety.

BACKGROUND

Data storage devices (DSDs) are often used in electronic devices such as computer systems to record data onto or to reproduce data from a recording media. As electronic devices such as tablets become more mobile, power requirements become more stringent for DSDs while performance specifications for DSDs such as data transfer rates become more demanding. Improvement in DSD performance often comes at a price of increased power consumption while a reduction of a DSD's power consumption often comes at a price of decreased performance.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the embodiments of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. The drawings and the associated descriptions are provided to illustrate embodiments of the disclosure and not to limit the scope of what is claimed. Reference numbers are reused throughout the drawings to indicate correspondence between referenced elements.

FIG. 1 is a block diagram depicting an electronic device with a data storage device (DSD) according to an embodiment.

FIG. 2 is a flowchart for a power management process according to an embodiment.

FIG. 3 is a flowchart for a power management process according to another embodiment.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth to provide a full understanding of the present disclosure. It will be apparent, however, to one of ordinary skill in the art that the various embodiments disclosed may be practiced without some of these specific details. In other instances, well-known structures and techniques have not been shown in detail to avoid unnecessarily obscuring the various embodiments.

FIG. 1 shows electronic device 100 which includes host 101 and data storage device (DSD) 106 according to an embodiment. Electronic device 100 can be, for example, a computer system (e.g., desktop, mobile/laptop, tablet, smartphone, etc.) or other type of electronic device such as a digital video recorder (DVR). In this regard, electronic device 100 may be a stand-alone system or part of a network. Those of ordinary skill in the art will appreciate that electronic device 100 and/or DSD 106 can include more or less than those elements shown in FIG. 1 and that the disclosed power management processes may be implemented in other environments.

In the embodiment of FIG. 1, DSD 106 is a solid state hybrid drive (SSHD) that includes both magnetic recording media (e.g., disk 134) and solid state recording media (e.g., solid state memory 132) as non-volatile memory (NVM) for storing data. While the description herein refers to solid state memory generally, it is understood that solid state memory may comprise one or more of various types of memory devices such as flash integrated circuits, Chalcogenide RAM (C-RAM), Phase Change Memory (PC-RAM or PRAM), Programmable Metallization Cell RAM (PMC-RAM or PMCm), Ovonic Unified Memory (OUM), Resistance RAM (RRAM), NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory, or any combination thereof), NOR memory, EEPROM, Ferroelectric Memory (FeRAM), Magnetoresistive RAM (MRAM), other discrete NVM (non-volatile memory) chips, or any combination thereof.

In one embodiment, DSD 106 includes controller 120 which includes circuitry such as one or more processors for executing instructions and can include a microcontroller, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), hard-wired logic, analog circuitry and/or a combination thereof. In one implementation, controller 120 can include a system on a chip (SoC).

Host interface 126 is configured to interface DSD 106 with host 101 and may interface according to a standard such as, for example, PCI express (PCle), serial advanced technology attachment (SATA), or serial attached SCSI (SAS). As will be appreciated by those of ordinary skill in the art, host interface 126 can be included as part of controller 120. Although FIG. 1 depicts the co-location of host 101 and DSD 106, in other embodiments the two need not be physically co-located. In such embodiments, DSD 106 may be located remotely from host 101 and connected to host 101 via a network interface.

In the example of FIG. 1, DSD 106 includes rotating magnetic disk 134 which is rotated by spindle motor (SM) 138. DSD 106 also includes head 136 connected to the distal end of actuator 130 which is rotated by voice coil motor (VCM) 132 to position head 136 over disk 134. Controller 120 can include servo control circuitry (not shown) to control the position of head 136 and the rotation of disk 134 using VCM control signal 30 and SM control signal 34, respectively.

Disk 134 comprises a number of radial spaced, concentric tracks for storing data and can form part of a disk pack (not shown) which can include additional disks below disk 134 that rotate about SM 138. Head 136 includes at least a read element (not shown) for reading data from disk 134, and a write element (not shown) for writing data on disk 134.

In operation, host interface 126 receives host read and write commands from host 101 via host interface 126 for reading data from disk 134 and writing data to disk 134. In response to a write command from host 101, controller 120 may buffer the data to be written for the write command in volatile memory 140. A read/write channel (not shown) of controller 120 may then encode the buffered data into write signal 32 which is provided to head 136 for magnetically writing data to the surface of disk 134. In response to a read command from host 101, controller 120 controls head 136 to magnetically read data stored on the surface of disk 134 and to send the read data as read signal 32. The read/write channel of controller 120 can then decode and buffer the data into volatile memory 140 for transmission to host 101 via host interface 126.

In the embodiment of FIG. 1, DSD 106 also includes solid state memory 132 for storing data. Solid state memory 132 stores firmware 10 which can include computer-readable instructions used by DSD 106 to implement the power management processes described below. Solid state memory 132 also stores data 20 which can include data stored in accordance with a host write command and/or data accessed in accordance with a host read command.

Volatile memory 140 can include, for example, a dynamic random access memory (DRAM) which can be used by DSD 106 to temporarily store data. Data stored in volatile memory 140 can include data read from NVM (e.g., disk 134 and solid state memory 132), data to be written to NVM, instructions loaded from firmware 10 for execution by controller 120, and/or data used in executing firmware 10.

As discussed in more detail below, DSD 106 can operate in a power saving mode and a performance mode based on a workload received from host 101 during a predetermined time period. Settings for DSD 106 can differ based on whether DSD 106 is in the power saving mode, the performance mode, or some other mode.

FIG. 2 is a flowchart for a power management process which can be performed by controller 120 to adjust power settings for DSD 106 based on a workload received from host 101 according to one embodiment. The process begins in block 200, and controller 120 in block 202 updates a count of the number of host commands received from host 101 within a predetermined time period.

In block 204, controller 120 determines whether the number of received host commands exceeds a threshold number of commands for the predetermined time period. In this regard, the predetermined time period can be thought of as a sliding window and controller 120 in block 204 checks whether the number of host commands received in the sliding window exceeds a threshold. In one implementation, the threshold number of host commands can be set to 50 and the predetermined time period can be set to two seconds.

If the number of received host commands exceeds the threshold in block 204, at least one timer is set in block 206 to correspond to a performance mode of DSD 106. Generally, at least one timer can be increased in block 206 to improve performance of DSD 106 in the performance mode. DSD 106 may use such timers to initiate various low power states. In one implementation, DSD 106 may move head 136 away from disk 134 (i.e., park head 136) after two seconds of not receiving any commands to read data from or write data to any of the disks in the disk pack including disk 134. This can be part of an idle mode for the hard disk portion of the NVM of DSD 106. After an additional one second or total of no commands for the disks in the past three seconds, DSD 106 may further reduce the angular velocity at which the disk pack spins (i.e., spin down) to further reduce power consumption by the hard disk portion of the NVM.

Low power state timers can also be used for the solid state portion of the NVM. In one implementation, power is decreased to solid state memory 132 after no commands have been received in 100 ms for the solid state memory 132 to reduce power consumption by solid state memory 132. After an additional 200 ms of no commands, power for solid state memory 132 may be further reduced. In this regard, the power for solid state memory 132 may be reduced in a series of stages after the expiration of successive time periods without commands for solid state memory 132.

In addition, a low power state timer can be used for portions of host interface 126 where portions of host interface 126 are no longer powered after receiving no host commands in a specified timeframe.

When setting the timers for the performance mode in block 206, controller 120 may increase the low power state timers of DSD 106 so that the low power states of DSD 106 are delayed. Using the example timers provided above, controller 120 in block 206 may set the timers for the performance mode by increasing the timer for parking head 136 from two seconds to three seconds after not receiving any commands for use of the disks and by increasing the timer for spinning down the disk pack from three seconds to four seconds after not receiving any commands for the disks.

For the solid state portion of the NVM, controller 120 may, for example, increase a first timer for reducing power for solid state memory 132 from 100 ms to 150 ms after receiving no commands for solid state memory 132. A time limit for powering off portions of host interface 126 may also be increased in block 206. Additional low power state timers may also be increased in block 206.

By increasing timers for the low power states in the performance mode, DSD 106 can ordinarily complete host commands quicker by delaying DSD 106 from entering a low power state. Since periods of increased host commands usually have host commands clustered together, it is generally more likely that additional host commands may soon follow a time period when the threshold number of host commands has been exceeded. A timer or timers for entering a low power state are therefore increased in block 206 to allow for quicker performance of host commands that may soon follow a period of increased host commands.

In block 207, a deferred writing capability of DSD 106 is disabled to further improve performance of host commands. The deferred writing capability allows DSD 106 to write data for host commands that are to be written to the disk pack to solid state memory 132 instead and then later write the data to its intended location in the disk pack. This deferred writing can ordinarily allow for servicing of host write commands for writes intended for the disk pack while performing other operations in the disk pack. However, writing data to solid state memory, such as solid state memory 132, is typically slower than writing data to disk 134 when disk 134 is spun up to a speed in performance mode at which data is usually written to or read from disk 134 (e.g., an operating speed of 5,400 RPM). The slower time to write data to solid state memory 132 can be due to additional operations involved in identifying and preparing appropriate blocks in solid state memory 132 for receiving data.

Deferred writing is therefore disabled for performance mode in block 207 since the disk pack is at its full operating speed and deferring a write command by writing the data to solid state memory 132 would usually take more time than writing the data to the disk pack.

In block 208, controller 120 checks if any low power state timers have expired. If so, controller 120 in block 210 extends the low power state timer or timers that have expired while in performance mode in order to more quickly perform any host commands that may soon follow.

After extending any expired timers in block 210, or if it is determined in block 208 that no low power state timers have expired, the process returns to block 202 to update the count of received host commands during a new predetermined time period (i.e., a new sliding window) and to determine whether the number of host commands received in the new predetermined time period exceeds the threshold in block 204.

If controller 120 determines in block 204 that the number of host commands received in the predetermined time period does not exceed the threshold, controller 120 sets the timers for a power saving mode in block 212. More specifically, some or all of the timers adjusted in block 206 may be decreased in block 212 so that DSD 106 will enter a low power state more quickly. With reference to the above example timers, controller 120 in block 212 may decrease the timer for parking head 136 from two seconds to one second and decrease the timer for spinning down the disk pack from three seconds to two seconds. The hard disk portion of the NVM will then generally enter these different low power states more quickly with the decreased timers set in block 212.

In block 214, controller 120 enables deferred writing if the disk pack has been spun down to below its operating speed. In this way, controller 120 can determine whether to store data on the disk or in the solid state memory based on whether the number of commands within the predetermined time period exceeds the threshold number of commands. As discussed above, deferred writing can allow for writing of data for host write commands intended for disk 134, for example, to solid state memory 132 and then for later writing the data to its intended location on disk 134. Although not as fast as writing data to disk 134 when it is spun up to its operating speed, enabling deferred writing in block 214 can often allow for quicker writing of the data since disk 134 has spun down below the operating speed. In addition, deferred writing can allow for less power consumption by only having to power solid state memory 132 in the power saving mode and not having to spin up disk 134 and move head 136 which typically requires more power than powering solid state memory 132.

Furthermore, since less than the threshold number of host commands have been received in block 204, it is more likely that host commands received in the power saving mode will be more isolated or less frequent than host commands received when DSD 106 is not in the power saving mode. These generally less frequent host commands received during the power saving mode can often be handled with deferred writing by powering solid state memory 132 on an as-needed basis without having to consume more power by spinning up the disk pack and actuating head 136.

After block 214, the process returns to block 202 to update the count of host commands received in a new predetermined time period.

FIG. 3 is a flowchart for a power management process which can be performed by controller 120 according to another embodiment. The process of FIG. 3 begins in block 300 and controller 120 in block 302 updates a count of the number of host commands received from host 101 within a predetermined time period.

In block 304, controller 120 determines whether there have been more than M consecutive time periods with more than the threshold number of host commands to determine whether to set a performance mode. In one implementation, M can equal three so that controller 120 changes power settings for a performance mode after at least three consecutive time periods (i.e., sliding windows) each having more than the threshold number of received host commands.

If it is determined in block 304 that there have not been more than M consecutive time periods with more than the threshold number of received host commands, controller 120 in block 312 determines whether there have been more than N consecutive time periods with less than the threshold number of received host commands. If so, controller 120 adjusts power settings of DSD 106 for a power saving mode in blocks 314 and 316.

By using different values for M and N above, it is ordinarily possible to control how quickly DSD 106 switches to performance mode and power saving mode. For example, if electronic device 100 can allow more power consumption by DSD 106, a smaller value of M can be used so that DSD 106 will enter the performance mode quicker with less consecutive time periods having more than the threshold number of host commands. A higher value for N can also be used in such an example so that more consecutive windows of less than the threshold number of host commands are needed before switching DSD 106 to the power saving mode. Such a change in M and N will typically allow DSD 106 to perform host commands quicker but will likely increase power consumption of DSD 106. Of course, M and N can be adjusted in the opposite direction to conserve more power at a cost in performance.

If controller 120 determines in block 304 that there have been more than M consecutive time periods with more than the threshold number of host commands, controller 120 adjusts the power settings in blocks 306, 307 and 310 for the performance mode. A further description of blocks 306, 307 and 310 can be obtained with reference to the description of similar blocks 206, 207, and 210 provided above for FIG. 2.

On the other hand, if controller 120 determines in block 312 that there have been more than N consecutive time periods with less than the threshold number of host commands, the process proceeds to blocks 314 and 316 to adjust power settings for the power saving mode. A further description of blocks 314 and 316 can be obtained with reference to the description of similar blocks 212 and 214 provided above for FIG. 2.

By determining whether the number of host commands received by DSD 106 has exceeded a threshold within a predetermined time period, it is ordinarily possible to adjust settings for DSD 106 to better adapt to a workload from host 101. Thus, the foregoing power management processes can better balance performance and power requirements for DSD 106 based on the host workload.

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks, modules, and processes described in connection with the examples disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. Furthermore, the foregoing processes can be embodied on a computer readable medium which causes a processor or computer to perform or execute certain functions.

To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, and modules have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those of ordinary skill in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, units, modules, and controllers described in connection with the examples disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The activities of a method or process described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The steps of the method or algorithm may also be performed in an alternate order from those provided in the examples. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable media, an optical media, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC).

The foregoing description of the disclosed example embodiments is provided to enable any person of ordinary skill in the art to make or use the embodiments in the present disclosure. Various modifications to these examples will be readily apparent to those of ordinary skill in the art, and the principles disclosed herein may be applied to other examples without departing from the spirit or scope of the present disclosure. The described embodiments are to be considered in all respects only as illustrative and not restrictive and the scope of the disclosure is, therefore, indicated by the following claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.