Disk drive measuring down-track spacing of read sensors

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to provisional U.S. Patent Application Ser. No. 61/909,913, filed on Nov. 27, 2013, which is hereby incorporated by reference in its entirety.

BACKGROUND

Disk drives comprise a disk and a head connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. The disk comprises a plurality of radially spaced, concentric tracks for recording user data sectors and servo sectors. The servo sectors comprise head positioning information (e.g., a track address) which is read by the head and processed by a servo control system to control the actuator arm as it seeks from track to track.

FIG. 1 shows a prior art disk format 2 as comprising a number of servo tracks 4 defined by servo sectors 6₀-6_N recorded around the circumference of each servo track. Each servo sector 6_i comprises a preamble 8 for storing a periodic pattern, which allows proper gain adjustment and timing synchronization of the read signal, and a sync mark 10 for storing a special pattern used to symbol synchronize to a servo data field 12. The servo data field 12 stores coarse head positioning information, such as a servo track address, used to position the head over a target data track during a seek operation. Each servo sector 6_i further comprises groups of servo bursts 14 (e.g., N and Q servo bursts), which are recorded with a predetermined phase relative to one another and relative to the servo track centerlines. The phase based servo bursts 14 provide fine head position information used for centerline tracking while accessing a data track during write/read operations. A position error signal (PES) is generated by reading the servo bursts 14, wherein the PES represents a measured position of the head relative to a centerline of a target servo track. A servo controller processes the PES to generate a control signal applied to a head actuator (e.g., a voice coil motor) in order to actuate the head radially over the disk in a direction that reduces the PES.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a prior art disk format comprising a plurality of servo tracks defined by servo sectors.

FIG. 2 shows a disk drive according to an embodiment comprising a head actuated over a disk.

FIG. 3 shows an embodiment wherein the head comprises a plurality of read sensors separated by a down-track spacing.

FIG. 4 shows control circuitry according to an embodiment for measuring a first temp-stamp (TS1) when a first read sensor passes over a sync mark, and measuring a second time stamp (TS2) when a second read sensor passes over the sync mark.

FIG. 5 is a flow diagram according to an embodiment wherein a calibration value representing the down-track spacing between the first and second read sensors is generated based on the TS1 and the TS2.

FIGS. 6A and 6B show an embodiment wherein existing infrastructure of a timing recovery circuit is leveraged to generate the time-stamps TS1 and TS2.

FIG. 7 shows an embodiment wherein the down-track spacing (measured in time) between read sensors is measured at different radial locations across the disk.

FIG. 8 shows an embodiment wherein an analog delay is configured based on the measured down-track spacing so as to align first and second analog read signals generated by first and second read sensors.

FIG. 9A shows an embodiment wherein first signal samples of a first read signal are combined with second signal samples of the second read signal by configuring a digital delay based on the measured down-track spacing.

FIG. 9B shows an embodiment wherein a two-dimensional equalization of the first signal samples and the second signal samples is executed prior to data detection within a read channel.

DETAILED DESCRIPTION

FIG. 2 shows a hard disk drive (HDD) according to an embodiment comprising a head 16 and a disk 18 comprising a plurality of servo tracks 20, wherein each servo track comprises a plurality of servo sectors 22₀-22_N. The disk drive further comprises control circuitry 24 comprising a servo control system operable to actuate the head over the disk in response to the servo sectors 22₀-22_N. The disk is rotated by a spindle motor 46 at a rotational speed that is controlled by the control circuitry 24, for example, a motor driver of the control circuitry 24.

In the embodiment of FIG. 2, the control circuitry 24 processes a read signal 32 emanating from the head 16 to demodulate the servo sectors 22₀-22_N and generate a position error signal (PES) representing an error between the actual position of the head and a target position relative to a target track. In one embodiment, the target track comprises a target data track defined relative to the servo tracks 20, wherein the data tracks may be recorded at the same or different radial density than the servo tracks 20. The control circuitry 24 filters the PES using a suitable compensation filter to generate a control signal 34 applied to a voice coil motor (VCM) 36 which rotates an actuator arm 38 about a pivot in order to actuate the head 16 radially over the disk 18 in a direction that reduces the PES. The control circuitry 24 may also generate a control signal 40 applied to a microactuator 42 in order to actuate the head 16 over the disk 18 in fine movements. Any suitable microactuator 42 may be employed in the embodiments, such as a piezoelectric actuator. In addition, the microactuator 42 may actuate the head 16 over the disk 18 in any suitable manner, such as by actuating a suspension relative to the actuator arm, or actuating a slider relative to the suspension. The servo sectors 22₀-22_N may comprise any suitable head position information, such as a track address for coarse positioning and servo bursts for fine positioning. The servo bursts may comprise any suitable pattern, such as an amplitude based servo pattern or a phase based servo pattern.

To accomplish reading and writing of data to and from the disk, the control circuitry may include a read channel configured to process the read signal 32 from the head 16 and a write channel to prepare write signal 32 for sending to the head 16 for writing.

In one embodiment, the head 16 may comprise a two-dimensional magnetic recording (TDMR) head, in which there can be multiple reader elements (read sensors) within the TDMR head. In such a situation, there is an inherent down-track separation between the individual read sensors which can vary greatly over process, for each head. For any TDMR data or servo operation, the separation of the read sensors is preferably obtained for optimal digital signal processing (DSP) of the signals from the different read sensors. In some implementations it is preferable that this read sensor separation be measured with high precision at different radial locations on the disk (e.g., adjusting for different actuator positions). Some embodiments of the invention introduce methods to measure this down-track separation. In some embodiments, the measurements are performed after final assembly, after the drive is operational.

TDMR is a read-back optimized technology. The advent of multiple readers on the same slider gives the opportunity to extract multiple read signals and subsequently improved signal-to-noise (SNR) gains via signal processing the signal out of multiple read sensors (read sensors can read the same track or adjacent tracks). TDMR gains are expected when either reading mainly the same track or processing signal from a main track and its adjacent tracks.

FIG. 3 shows an example read sensor configuration 60 according to one embodiment. The read sensors within the head are labeled in the figure as Sensor #1, #2, and #3. The tracks on the disk are represented by the vertical rectangles 62, 64, and 66. The figure shows the down-track spacing (DTS) between the individual read sensors, as well as the cross-track spacing (CTS) between the sensors. Both the DTS and CTS may be significantly different for every head due to manufacturing variances. In addition, real-time operating conditions such as temperature, touchdown condition, and head skew angle can also contribute to variances at different times.

Having real-time measurements of DTS allows tracking of any perturbations (both thermal and mechanical) and enables optimal timing-alignment of the signals coming from multiple readers, which translates to better SNR and an improvement in servo-positioning. Thus, described below are various embodiments that use time-stamps from multiple read sensors to accurately measure DTS.

One embodiment leverages existing infrastructure within the read channel circuitry to enable the use of time-stamps to measure DTS. In some read channel implementations there may exist a free running counter running off of a main time-base. The counter may be reset by servo sync mark (SSM) detection. Once the time-stamp is enabled, for each of the subsequent SSM detections, the count is captured and stored. The capturing of the count when the SSM is detected is referred to as a “time-stamp.” Knowing the number of counts between each SSM (the difference in counts) can represent the down-track spacing between the read sensors. Alternatively, for the purpose of generating DTS values, such a time-stamp mechanism can be implemented outside of the read channel circuitry as an independent component.

In one embodiment, the sync mark (SM) used can be either a spiral sync mark, a servo sync mark, or a read data sync mark. Indeed, the type of sync mark used can vary, as long as the sync marks on the disk are aligned and/or the skew is controlled. In one embodiment, the time-stamp is derived by a counter internal to the channel (or an independent time-stamping mechanism as described above) that provides sub-T resolution (e.g., T/4 to T/128), where T represents the data rate period of the sync mark bits. In one embodiment, time-stamps from different read sensors can be derived from one counter. In another embodiment, time-stamps from different read sensors can be derived from different counters that are properly synchronized. Either way, this ensures that the time-stamp difference translates to a precise measurement of spatial separation between the read sensors. The difference calculation of these counters (time-stamps) can be used to provide a continuous measurement called a “calibration value” representing the down-track spacing between read sensors.

In one embodiment, one of the read sensors is programmed as the “primary” sensor and the other is programmed as the secondary sensor. If the primary sensor detects the SM first, then the “calibration” value will be positive. If the secondary sensor detects the SM first, then the “calibration” value will be negative.

FIG. 4 depicts an example timing circuit implementation 70 in which calibration values are derived from time-stamps according to one embodiment. As described above, the timing circuit implementation 70 may include components that may already exist within a read channel implementation, or may be implemented separately as a mechanism independent from the read channel circuitry. In one embodiment, a “TimeStamp Counter Circuit” block 72 is reset when the sync mark (SM) is detected at block 74 in response to the Read Sensor 1 (e.g., by the “RESET on SMF” block 76 as shown). Next, the “TimeStamp Counter Circuit” block 72 is armed (e.g., by the “Arm SMF Time-stamp” block 78 as shown) to capture the time-stamp values as the sync mark (SM) is detected by the following read sensors (e.g., detected at block 80 in response to Read Sensor 2). In one embodiment, a “TimeBase Generator” block 81 provides a base timing clock, which is supplied to the “TimeStamp Counter Circuit” block 72. Once the time-stamps have been generated, “Calibration Value” block 83 processes the time-stamps to generate a calibration value representing the down-track spacing between the read sensors, for example, based on a difference between the time-stamps.

As the track moves under the head, the SM may pass under the first “leading” sensor and the channel may detect the SM with detector one (“SM DET 1” block 74 in the figure). This may cause the circuit to capture the first time-stamp value and store. This same sync mark may then pass under the second “trailing” sensor and the channel may detect the SM with detector two (“SM DET 2” block 80 in the figure), which may cause the circuit to capture the second time-stamp value and store. As shown in the figure, the time-stamp counter circuit can be used to determine the difference of the two time-stamp values and output a difference. As shown, the difference may be calculated and used (e.g., by the read channel or some other external logic) to determine a calibration value. Such a calibration value can be used on-the-fly by the channel for timing-alignment. In one embodiment, it may be stored in a register for firmware access which can be used by an external DSP or other operations to improve SNR. The calibration value can be used to align the signals inside the read channel or by external DSP circuitry or software.

FIG. 5 shows a conceptual flowchart of a calibration value generation process according to an embodiment. In block 82, a first SM is detected using the first read sensor of a TDMR head. In block 84, timing information TS1 is generated. In block 86, a second SM is detected using the second read sensor of the TDMR head. In block 88, timing information TS2 is generated. In block 90, a calibration value is determined based at least in part on the generated timing information TS1 and TS2. In one embodiment, the process may be implemented in and/or executed by the control circuitry 24 of FIG. 2. In one embodiment, the process may be implemented in and/or executed by the read channel circuitry of FIG. 4. Those skilled in the art will appreciate that the process can be extended to generate calibration values for more than one pair of TDMR read sensors. In other embodiments, three or more time-stamps may be used to generate calibration value(s) for three read sensors as shown in the example of FIG. 3.

FIG. 6A shows control circuitry according to an embodiment comprising a timing recovery circuit 92 operable to generate a sampling clock 94 applied to a signal sampler 96 which samples the read signal 32 to generate signal samples 98. An equalizer filter 100 filters the signal samples 98 according to a desired response (e.g., a partial response), and the equalized signal samples 102 are processed by a sequence detector 104 to detect data recorded on the disk 18. In one embodiment, the timing recovery circuit 92 generates the sampling clock 94 synchronous with the data rate of the recorded data so that the signal samples 98 are substantially synchronous with the data rate.

Any suitable timing recovery circuit 92 may be employed to generate the synchronous signal samples, and in one embodiment the timing recovery circuit 92 may be leveraged to generate the timestamps for measuring the down-track spacing of the read sensors. FIG. 6B shows an embodiment of a timing recovery circuit wherein a reference clock 106 (e.g., generated by a resonator, oscillator, crystal, etc.) is processed by a first phase-locked loop (PLL) 108 to generate the sampling clock 94 applied to the signal sampler 96 (analog-to-digital converter). A phase error detector 110 processes the equalized signal samples 102 to measure a phase error 112 that adjusts the first PLL 108 so as to synchronize the sampling clock 94 to the data rate. A zero-phase start (ZPS) block 114 processes the signal samples 98 (e.g., of a preamble) to generate a zero-phase start value 116 representing an initial phase error of the signal samples which is used to initialize the phase error detector 110. That is, the zero-phase start value 116 represents an initial fraction of the sampling clock 94 cycling substantially at the data rate of period T. A sync mark detector 118 processes the equalized signal samples 102 and generates a sync mark detected signal 120 at the resolution of the sampling clock 94. The reference clock 106 is processed by a second PLL 122 which generates a fixed frequency clock 124 (substantially at the data rate) used to clock a counter 126. A timestamp generator 128 combines the output of the counter 126 when the sync mark is detected (which represents an integer value for the timestamp) with the zero-phase start value 114 (which represents a fractional value for the timestamp) to generate a high resolution timestamp. This embodiment enables a very accurate, sub-T measurement of the down-track spacing between the read sensors by leveraging existing infrastructure of the timing recovery circuit 92.

In one embodiment, the down-track spacing of the read sensors may vary based on the radial location of the head 16 due to the skew angle of the head 16 as well as the varying linear velocity of the tracks. For example, in one embodiment the linear velocity of the tracks (and sync mark within a track) increases toward the outer diameter of the disk due to the increasing circumference of the tracks, and therefore the down-track spacing as measured relative to a reference clock will decrease since it will take fewer clock cycles for the sync mark to travers the physical gap between the read sensors. Accordingly, in one embodiment illustrated in FIG. 7 the down-track spacing for at least two of the read elements may be measured at a plurality of different radial locations (represented by black dots), and these data points curve fitted to a suitable function, such as a suitable polynomial. The down-track spacing may then be estimated for any radial location of the head based on this curve-fitted function.

As described above, in one embodiment the calibration value representing the down-track spacing between the read sensors may be used to combine the read signals from the respective heads in either the analog or digital domain in order to improve the performance of the read channel. FIG. 8 shows an embodiment wherein a first read sensor 130A generates a first read signal 132A and a second read sensor 130B generates a second read signal 132B. The first read signal 132A is delayed using an analog delay circuit 134 to generate a delayed read signal 136 that is added to the second read signal 132B at analog adder 138. The analog delay circuit 134 is configured with an adjustable delay corresponding to the down-track spacing of the first and second read sensors 130A and 1308 so that the first and second read signals 132A and 132B are aligned in time, and in one embodiment the analog delay is adjusted based on the radial location of the head to account for the varying down-track spacing as shown in FIG. 7. The resulting combined read signal 140 is then processed by read channel 142 to detect data recorded on the disk 18.

In another embodiment, the first and second read signals 132A and 132B may be combined in the digital domain. FIG. 9A shows an example of this embodiment wherein the first read signal 132A is low pass filtered 144A and sampled 146A to generate first signal samples 148A, and the second read signal 132B is low pass filtered 144B and sampled 146B to generate second signal sample 148B. The first signal samples 148A are delayed using digital delay circuitry 150 for delaying the first read signal 132A in discrete time. The delayed signal samples 152 are combined at digital adder 154 with the second signal samples 148B to generate combined signal samples 156 that are processed by read channel 158. Any suitable digital delay circuit 150 may be employed to generate an integer and fractional sample period delay representing the down-track spacing of the read sensors. In one embodiment, the integer delay may be implemented with a shift register and the fractional delay implemented using a phase-offset sampling clock for clocking the sampling device 146B relative to sampling device 146A, or an interpolating filter for phase shifting the first signal samples 148A. In one embodiment the digital delay is adjusted based on the radial location of the head to account for the varying down-track spacing as shown in FIG. 7. The resulting combined signal samples 156 are then processed by read channel 158 to detect data recorded on the disk 18.

FIG. 9B shows an alternative embodiment wherein the delayed signal samples 152 and the second signal samples 148B are processed by a two-dimensional (2D) equalizer 160. In one embodiment, the 2D equalizer 160 outputs two sequences 162 of signal samples that are processed by a 2D read channel 164 (e.g., using a 2D Viterbi detector). In another embodiment, the 2D equalizer 160 outputs a sequence of signal samples 162 with inter-track interference (ITI) attenuated so that the sequence of signal samples 162 may be processed with a one-dimensional (1D) read channel 164 (e.g., using a 1D Viterbi detector).

Some embodiments of the invention thus provide an accurate on-the-fly methodology to track inter-reader down-track separation, enabling SNR gain for data detection (e.g., due to precise timing-alignment of signals feeding 2D equalizer as described above) and improving servo-positioning. Along with this is the possibility of reducing the size of the servo-format by reducing burst length and hence gaining SNR. The logic can also enable/simplify specific applications and test-process. A good example would be measuring coherence of the write process (i.e. speed-up process time during servo-filler). In other embodiments, the down-track spacing measurements may be used to characterize and/or validate the manufacturing tolerances and fabrication process of the read sensors.

Any suitable control circuitry may be employed to implement the flow diagrams in the above embodiments, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain operations described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into a SOC.

In one embodiment, the control circuitry or DSP comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.

The various features and processes described above may be used independently of one another, or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of this disclosure. In addition, certain method, event or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate. For example, described tasks or events may be performed in an order other than that specifically disclosed, or multiple may be combined in a single block or state. The example tasks or events may be performed in serial, in parallel, or in some other manner. Tasks or events may be added to or removed from the disclosed example embodiments. The example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed example embodiments.

While certain example embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the embodiments disclosed herein. Thus, nothing in the foregoing description is intended to imply that any particular feature, characteristic, step, module, or block is necessary or indispensable. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the embodiments disclosed herein.