Data storage device using branch metric from adjacent track to compensate for inter-track interference

Description

BACKGROUND

Data storage devices such as disk drives comprise a disk and a head connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. The disk comprises a plurality of radially spaced, concentric tracks for recording user data sectors and servo sectors. The servo sectors comprise head positioning information (e.g., a track address) which is read by the head and processed by a servo control system to control the actuator arm as it seeks from track to track.

FIG. 1 shows a prior art disk format 2 as comprising a number of servo tracks 4 defined by servo sectors 6₀-6_N recorded around the circumference of each servo track. Each servo sector 6_i comprises a preamble 8 for storing a periodic pattern, which allows proper gain adjustment and timing synchronization of the read signal, and a sync mark 10 for storing a special pattern used to symbol synchronize to a servo data field 12. The servo data field 12 stores coarse head positioning information, such as a servo track address, used to position the head over a target data track during a seek operation. Each servo sector 6_i further comprises groups of servo bursts 14 (e.g., N and Q servo bursts), which are recorded with a predetermined phase relative to one another and relative to the servo track centerlines. The phase based servo bursts 14 provide fine head position information used for centerline tracking while accessing a data track during write/read operations. A position error signal (PES) is generated by reading the servo bursts 14, wherein the PES represents a measured position of the head relative to a centerline of a target servo track. A servo controller processes the PES to generate a control signal applied to a head actuator (e.g., a voice coil motor) in order to actuate the head radially over the disk in a direction that reduces the PES.

Data is typically written to data sectors within a data track by modulating the write current of a write element, for example, using a non-return to zero (NRZ) signal, thereby writing magnetic transitions onto the disk surface. A read element (e.g., a magnetoresistive (MR) element) is then used to transduce the magnetic transitions into a read signal that is demodulated by a read channel. The recording and reproduction process may be considered a communication channel, wherein communication demodulation techniques may be employed to demodulate the read signal.

When reading data from the disk, a read channel typically samples the read signal to generate signal samples that are equalized according to a target response (e.g., a partial response). A sequence detector (e.g., a Viterbi detector) detects an estimated data sequence from the equalized samples, and errors in the estimated data sequence are corrected, for example, using a Reed-Solomon error correction code (ECC) or using a Low Density Parity Check (LDPC) code.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a prior art disk format comprising servo tracks defined by servo sectors.

FIG. 2A shows a data storage device in the form of a disk drive according to an embodiment comprising a head actuated over a disk.

FIG. 2B shows an embodiment wherein the head comprises a first read element positioned over a first data track and a second read element positioned over a second data track.

FIG. 2C is a flow diagram according to an embodiment wherein a second branch metric in a second trellis sequence detector is generated when detecting a second data sequence based on second signal samples and a first branch metric generated by a first trellis sequence detector.

FIG. 3A shows an example state transition diagram for a sixteen state trellis sequence detector according to an embodiment.

FIG. 3B illustrates an embodiment for generating the branch metrics for the branch transitions of two states of a second trellis sequence detector based on an expected sample corresponding to a branch selected by a first trellis sequence detector.

FIG. 4A illustrates an embodiment wherein the signal samples are equalized using a two-dimensional (2D) equalizer, and the equalized samples processed by respective trellis sequence detectors.

FIG. 4B illustrates an embodiment wherein when generating the branch metrics, each trellis sequence detector iterates based on the branch selected by the other trellis sequence detector.

FIG. 5 shows an embodiment wherein the head comprises three read elements for generating a read signal from three adjacent data tracks, and three trellis sequence detectors that iterate based on the branches selected in the adjacent trellis sequence detectors.

DETAILED DESCRIPTION

FIG. 2A shows a data storage device in the form of a disk drive according to an embodiment comprising a disk 16 comprising a plurality of data tracks 18, and a head 20 actuated over the disk 16, the head 20 comprising a plurality of read elements including a first read element 22A and a second read element 22B (FIG. 2B). The disk drive further comprises control circuitry 24 configured to execute the flow diagram of FIG. 2C, wherein a first data track (FIG. 2B) is read using the first read element to generate a first read signal (block 26), and the first read signal is sampled to generate first signal samples (block 28). A first branch metric is generated in a first trellis sequence detector when detecting a first data sequence based on one of the first signal samples (block 30). A second data track adjacent the first data track (FIG. 2B) is read using the second read element to generate a second read signal (block 32), and the second read signal is sampled to generate second signal samples (block 34). A second branch metric is generated in a second trellis sequence detector when detecting a second data sequence based on one of the second signal samples and the first branch metric (block 36).

In the embodiment of FIG. 2A, a plurality of concentric servo tracks are defined by embedded servo sectors 38₀-38_N, wherein the data tracks 18 are defined relative to the servo tracks at the same or different radial density. The control circuitry 24 processes at least one read signal 40 emanating from the head 20 to demodulate the servo sectors and generate a position error signal (PES) representing an error between the actual position of the head and a target position relative to a target track. The control circuitry 24 filters the PES using a suitable compensation filter to generate a control signal 42 applied to a voice coil motor (VCM) 44 which rotates an actuator arm 46 about a pivot in order to actuate the head 20 radially over the disk 16 in a direction that reduces the PES. The control circuitry 24 may also generate a control signal applied to a microactuator (not shown) in order to actuate the head 20 over the disk 16 in fine movements. Any suitable microactuator may be employed, such as a piezoelectric actuator. In addition, the microactuator may actuate the head 20 over the disk 16 in any suitable manner, such as by actuating a suspension relative to the actuator arm, or actuating a slider relative to the suspension. The servo sectors 38₀-38_N may comprise any suitable head position information, such as a track address for coarse positioning and servo bursts for fine positioning. The servo bursts may comprise any suitable pattern, such as an amplitude based servo pattern or a phase based servo pattern.

The data is typically recorded in a data track using partial response signaling meaning that the waveform response of each recorded bit overlaps with the waveform response of one or more of the linear adjacent bits resulting in a controlled amount of downtrack interference (DTI) in the read signal (also referred to as intersymbol interference (ISI)). Demodulating the read signal involves sampling the read signal and estimating a data sequence based on the likelihood that the signal samples correspond to the expected samples of a possible data sequences. To facilitate this demodulation, a trellis type sequence detector is typically employed comprising a state machine that corresponds to the possible data sequences based on the length of the DTI (number of bits affected). FIG. 3A shows an example state transition diagram for a sixteen state trellis that corresponds to a DTI length of four bits. At any given state, a branch metric is computed (e.g., a Euclidean metric) representing a likelihood of the next downtrack bit being a “0” or a “1”. As the bits in the read signal are evaluated, a number of survivor sequences are tracked through the corresponding trellis which eventually merge into a most likely data sequence based on the accumulated branch metrics for each survivor sequence.

As the data tracks 20 are squeezed closer together in an attempt to increase the capacity of the disk 16, the data bits recorded in the first data track may induce an intertrack interference (ITI) in the read signal of the second data track (and vise versa). Accordingly, in one embodiment a trellis type sequence detector is employed that takes into account the intertrack interference caused by the data sequence recorded in at least one adjacent data track. FIG. 3B illustrates an example embodiment wherein a second branch metric (BM) computed for each state of the state transition diagram of a second trellis sequence detector is computed based on an expected sample corresponding to a first branch selected by a first trellis sequence detector. In this example, the second branch metric (BM₂) is computed as a Euclidean metric:
BM₂=∥₂(k)−d₂−αd₁∥²
where y₂(k) represents a second signal sample generated by sampling a second read signal, d₂ represents a second expected sample corresponding to a second branch of the second trellis sequence detector, d₁ represents a first expected sample corresponding to a first branch selected by the first trellis sequence detector based on a first branch metric when detecting a first data sequence, and α is a scalar. In an embodiment described below, the second branch metric (BM₂) may also be computed based on an expected sample corresponding to a third branch of a third trellis detector configured to detect a third data sequence in a third data track adjacent the second data track.

In the above Euclidean metric equation, the expected sample d₁ of the adjacent data track is scaled by a scalar α to account for the degree the ITI affects the read signal sample of the second data track as determined by the radial spacing of the first data track relative to the second data track. That is, the scalar α increases as the spacing between the data tracks decreases. In one embodiment, the scalar α may be calibrated during a manufacturing procedure, and/or tuned during normal read operations such as during retry operations. For example, the scalar α may be tuned relative to a suitable quality metric, such as a bit error rate of the sequence detector. In one embodiment, the spacing of the data tracks may vary over the radius of the disk, and/or the spacing between the read elements may change as the skew angle of the head changes, and therefore the scalar α may be calibrated and then configured during normal read operations based on the radial location of the head.

FIG. 4A shows control circuitry according to an embodiment wherein the first signal samples 48A of the first read signal and the second signal samples 48B of the second read signal are equalized by a two-dimensional (2D) equalizer 50 to generate first equalized samples 52A and second equalized samples 52B. A first trellis sequence detector 54A processes the first equalized samples 52A to detect a first data sequence 56A, and a second trellis sequence detector 54B processes the second equalized samples 52B to detect a second data sequence 56B. During the sequence detection process when each trellis sequence detector reaches a particular point in the trellis corresponding to a particular signal sample y(k) of each data track, the trellis sequence detectors 54A and 54B pass an expected sample d to the other trellis sequence detector, where the expected sample d corresponds to a branch that would be selected by the other trellis sequence detector. In one embodiment, the trellis sequence detectors 54A and 54B may iterate on the expected samples d until both trellis sequence detectors converge to a final answer for the branch metrics.

FIG. 4B illustrates an example of this embodiment wherein the first trellis sequence detector 54A processes a signal sample y₁(k) to select a first branch metric BM₁ based on an expected sample d₁ corresponding to each branch (e.g., selects one of two branches based on the minimum branch metric). The expected sample d₁ corresponding to the first branch metric BM₁ is passed to the second trellis sequence detector 54B which processes a signal sample y₂(k) to select a second branch metric BM₂ based on an expected sample d₂ corresponding to each branch as well as the expected sample d₁ received from the first trellis sequence detector 54A. The expected sample d₂ corresponding to the second branch metric BM₂ is passed to the second trellis sequence detector 54B which updates the computations of the first branch metric for each branch as illustrated in FIG. 4B. After updating the branch metrics based on the expected sample d₂ received from the second trellis sequence detector 54B, the first trellis sequence detector 54A may select a different branch corresponding to a different branch metric BM₁ and corresponding different expected sample d₁. The updated expected sample d₁ is then passed to the second trellis sequence detector 54B which updates its branch metrics accordingly. This process may be iterated any number of times, for example, until both trellis sequence detectors 54A and 54B converge to a final answer for the best branch to select.

FIG. 2C illustrates an embodiment wherein the first read element 24A may be offset from the second read element 24B by a downtrack spacing as well as a cross-track spacing. Accordingly, in one embodiment the control circuitry may compensate for the downtrack spacing by time aligning (through a delay) the signal samples of the first and second read signals prior to, or as part of, the 2D equalizer 50 shown in FIG. 4A. In one embodiment, the signal samples from one or both read signals may be buffered to facilitate the time aligning of the signals.

In one embodiment, buffering the signal samples may also compensate for the latency of the trellis sequence detectors 54A and 54B due to the iterations when computing the branch metrics as described above. In one embodiment, the number of iterations allowed for each signal sample may also be limited based on the free space available in the signal samples buffer. That is, as the free space decreases due to the latency of the trellis sequence detectors 54A and 54B, the number of iterations allowed at each signal sample may be reduced. In yet another embodiment, the number of iterations may range from zero to N based on a confidence metric associated with each branch metric selected. For example, if the difference between the branch metrics for two branches is significant, indicating a high confidence in the minimum branch metric, then to reduce the latency the trellis sequence detectors 54A and 54B may skip the step of updating the branch metrics based on expected samples passed between the trellis sequence detectors as described above.

FIG. 5 shows an embodiment wherein head 20 comprises a third read element and the control circuitry 24 is further configured to read a third data track using the third read element to generate a third read signal, and sample the third read signal to generate third signal samples 48C. A third branch metric is generated in a third trellis sequence detector 54C when detecting a third data sequence 56C based on one of the third signal samples 48C. The second branch metric is generated in the second trellis sequence detector 54B when detecting the second data sequence 56B based on one of the second signal samples 48B, the first branch metric, and the third branch metric. In one embodiment, the second trellis sequence detector 54B is configured to generate the second branch metric when detecting the second data sequence 56B based on a third expected sample d₃ corresponding to a third branch selected by the third trellis sequence detector 54C based on the third branch metric when detecting the third data sequence 56C. Similarly, the third trellis sequence detector 54C may be configured to generate the third branch metric when detecting the third data sequence 56B based on the second expected sample d₂ corresponding to the second branch selected by the second trellis sequence detector 54B based on the second branch metric when detecting the second data sequence 56B. In one embodiment, the three trellis sequence detectors 54A-54C shown in FIG. 5 may iterate any suitable number of times as described above with reference to FIG. 4B.

In one embodiment, the 2D equalizer 50 shown in the examples of FIGS. 4A and 5 may equalize the signal samples to generate one-dimensional (1D) equalized samples processed by 1D trellis sequence detectors. That is, the 2D equalizer 50 may perform 2D-to-1D equalization, and the trellis sequence detectors may perform 1D sequence detection based on a single stream of equalized samples corresponding to a single data track. In another embodiment, the 2D equalizer 50 may comprise a 2D-to-2D equalizer that equalizes the signal samples to generate 2D equalized samples processed by 2D trellis sequence detectors. That is, the trellis sequence detectors may perform 2D sequence detection based on multiple (e.g., two or three) streams of equalized samples corresponding to multiple data tracks.

Any suitable control circuitry may be employed to implement the flow diagrams in the above embodiments, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain operations described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into a SOC.

In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.

While the above examples concern a disk drive, the various embodiments are not limited to a disk drive and can be applied to other data storage devices and systems, such as magnetic tape drives, solid state drives, hybrid drives, etc. In addition, some embodiments may include electronic devices such as computing devices, data server devices, media content storage devices, etc. that comprise the storage media and/or control circuitry as described above.

The various features and processes described above may be used independently of one another, or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of this disclosure. In addition, certain method, event or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate. For example, described tasks or events may be performed in an order other than that specifically disclosed, or multiple may be combined in a single block or state. The example tasks or events may be performed in serial, in parallel, or in some other manner. Tasks or events may be added to or removed from the disclosed example embodiments. The example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed example embodiments.

While certain example embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions disclosed herein. Thus, nothing in the foregoing description is intended to imply that any particular feature, characteristic, step, module, or block is necessary or indispensable. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the embodiments disclosed herein.