Data storage device erasing multiple adjacent data tracks to recover from inter-track interference

Description

BACKGROUND

Data storage devices such as disk drives comprise a disk and a head connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. The disk comprises a plurality of radially spaced, concentric tracks for recording user data sectors and servo sectors. The servo sectors comprise head positioning information (e.g., a track address) which is read by the head and processed by a servo control system to control the actuator arm as it seeks from track to track.

FIG. 1 shows a prior art disk format 2 as comprising a number of servo tracks 4 defined by servo sectors 6₀-6_N recorded around the circumference of each servo track. Each servo sector 6_i comprises a preamble 8 for storing a periodic pattern, which allows proper gain adjustment and timing synchronization of the read signal, and a sync mark 10 for storing a special pattern used to symbol synchronize to a servo data field 12. The servo data field 12 stores coarse head positioning information, such as a servo track address, used to position the head over a target data track during a seek operation. Each servo sector 6_i further comprises groups of servo bursts 14 (e.g., N and Q servo bursts), which are recorded with a predetermined phase relative to one another and relative to the servo track centerlines. The phase based servo bursts 14 provide fine head position information used for centerline tracking while accessing a data track during write/read operations. A position error signal (PES) is generated by reading the servo bursts 14, wherein the PES represents a measured position of the head relative to a centerline of a target servo track. A servo controller processes the PES to generate a control signal applied to a head actuator (e.g., a voice coil motor) in order to actuate the head radially over the disk in a direction that reduces the PES.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a prior art disk format comprising a plurality of servo tracks defined by servo sectors.

FIG. 2A shows a data storage device in the form of a disk drive according to an embodiment comprising a head actuated over a disk comprising a plurality of data tracks.

FIG. 2B is a flow diagram according to an embodiment wherein during a retry operation for a target data track an adjacent data track is incrementally erased toward the target data track.

FIGS. 3A and 3B illustrate a prior art technique for performing a retry operation by erasing an adjacent data track one time which may erase part of the target data track.

FIGS. 4A-4F illustrate an embodiment wherein an adjacent data track is partially and incrementally erased toward a target data track during the retry operation so as not to erase part of the target data track.

FIG. 5 is a flow diagram according to an embodiment wherein after each incremental erase of the adjacent data track the target data track is read multiple times using different radial offsets during the retry operation.

FIG. 6 illustrates an embodiment wherein the read element is positioned at different radial offsets when reading the target data track during the retry operation.

FIG. 7 illustrates an embodiment wherein an AC erase signal used to erase the adjacent data track comprises a frequency higher than the frequency of the target data recorded in the target data track.

DETAILED DESCRIPTION

FIG. 2A shows a data storage device in the form of a disk drive according to an embodiment comprising a disk 16 comprising a plurality of data tracks 18, and a head 20 actuated over the disk 16. The disk drive further comprises control circuitry 22 configured to execute the flow diagram of FIG. 2B, wherein when a retry operation for a target data track is needed (block 24), the head is positioned at a first radial location (block 26) and at least part of a first data track adjacent the target data track is first erased (block 28). After the first erasing, the target data track is first read to first recover target data recorded in the target data track (block 30). When the first recovery fails (block 32), the head is positioned at a second radial location (block 34) and more of the first data track is second erased (block 36). After the second erasing, the target data track is second read to second recover the target data recorded in the target data track (block 38).

In the embodiment of FIG. 2A, a plurality of servo tracks are defined by embedded servo sectors 40₀-40_N, wherein the data tracks 18 are defined relative to the servo tracks at the same or different radial density. The control circuitry 22 processes a read signal 42 emanating from the head 20 to demodulate the servo sectors and generate a position error signal (PES) representing an error between the actual position of the head and a target position relative to a target track. The control circuitry 22 filters the PES using a suitable compensation filter to generate a control signal 44 applied to a voice coil motor (VCM) 46 which rotates an actuator arm 48 about a pivot in order to actuate the head 20 radially over the disk surface 16 in a direction that reduces the PES. The servo sectors 40₀-40_N may comprise any suitable head position information, such as a track address for coarse positioning and servo bursts for fine positioning. The servo bursts may comprise any suitable pattern, such as an amplitude based servo pattern or a phase based servo pattern.

During a write operation, a disturbance affecting the servo control system that positions the head radially over the disk may cause the head to deviate from the center of the target data track resulting in an off-track write. A disturbance that causes an off-track write may manifest for any number of reasons, such as a physical shock to the disk drive due to being bumped or dropped, a vibration affecting the disk drive such as an audio signal, random electronic noise when reading the servo sectors, a grown defect in one or more servo sectors, etc. FIG. 3A shows an example of an off-track write wherein the write element 52 deviates from the center of a target data track 50A thereby overwriting part of adjacent data track 50B. The off-track write shown in FIG. 3A may span only part of a single data sector, or it may span multiple data sectors such as the data sectors between consecutive servo sectors, or it may span an entire data track. In any event, when attempting to read the target data track 50A, the data recorded in the adjacent data track 50B may interfere with the read signal (referred to as inter-track interference). If the target data track 50A is unrecoverable during a read operation, the prior art has suggested to perform a retry operation by positioning the write element 52 over the center of the adjacent data track 50B and erasing the adjacent data track 50B as shown in FIG. 3B. After erasing the adjacent data track 50B, the target data track 50A is read again with the inter-track interference attenuated, thereby improving the chance of a successful read. However, positioning the write element 52 at the center and erasing the adjacent data track 50B as illustrated in FIG. 3B may also erase part of the target data track at the off-track write location, which may render the target data permanently unrecoverable.

Accordingly, in one embodiment illustrated in FIG. 4A during a retry operation the write element 52 is positioned offset from the center of the adjacent data track 50B away from the target data track 50A. Part of the adjacent data track 50B is then erased as illustrated in FIG. 4B without erasing the target data at the off-track write location. The control circuitry 22 attempts to read the target data from the target data track, and if the target data is still unrecoverable, the write element 52 is positioned closer toward the target data track as shown in FIG. 4C and more of the adjacent data track 50B is erased as shown in FIG. 4D. If the target data is still unrecoverable, the processes is repeated as shown in FIGS. 4E and 4F such that even more of the adjacent data track 50B is erased without erasing the target data at the off-track write location. As more of the adjacent data track 50B is erased, the inter-track interference is reduced until the target data at the off-track write location may be successfully recovered.

FIG. 5 is a flow diagram according to an embodiment which extends on the flow diagram of FIG. 2B, wherein when a retry operation is needed (block 24) data is read from the first adjacent data track 50B as well as from the next adjacent data track 50C and stored in a temporary location (e.g., in a different data track). In this manner, the data is saved before erasing part of the first adjacent data track 50B and the next adjacent data track 50C at block 28. If the retry read of the target data track fails (block 56), the radial location of the head is adjusted toward the target data track (block 58) and more of the first adjacent data track is erased (block 60). The target data track is read again (block 62), and if the retry read fails again (block 64), the flow diagram is repeated from block 58. If the retry read is successful at block 64, the saved data is rewritten back to the first adjacent data track 50B as well as data in the next adjacent data track 50C (block 66).

In one embodiment illustrated in FIG. 6, after erasing part of the adjacent data track at block 60 of FIG. 5 and when executing the retry read at block 62, the read element 68 may be positioned at a plurality of different radial locations relative to the target data track and the target data track read at each radial location. This embodiment attempts to find the radial location of the target data track where the signal-to-noise ratio at the off-track write location is maximized, thereby improving the chances of successfully recovering the target data at the off-track write location. Accordingly, this embodiment executes an outer loop wherein the radial offset for erasing the adjacent data track 50B is incrementally adjusted toward the target data track, and an inner loop wherein the radial offset for reading the target data track 50A is adjusted in an attempt to recover the target data.

In one embodiment, the adjacent data track 50B is erased using a suitable erase pattern comprising a frequency range that is different than a frequency range spanned by the target data recorded in the target data track. FIG. 7 illustrates an example of this embodiment which shows an example frequency range 70 for the target data when using linear magnetic recording (LMR) and an example frequency range 72 for the target data when using perpendicular magnetic recording (PMR). FIG. 7 also illustrates an embodiment wherein the erase pattern comprise an AC pattern having a frequency that is higher than the frequency range spanned by the target data. In one embodiment, erasing the adjacent data track 50B using an out-of-band erase pattern (e.g., a higher frequency AC pattern) helps attenuate inter-track interference that may be caused by the erase pattern when reading the target data from the target data track.

The embodiment illustrated in FIGS. 4A-4F shows the adjacent data track 50B on one side (right side) of the target data track being erased. In another embodiment, the adjacent data track on both sides of the target data track may be erased in a similar manner (by incrementally erasing from left to right and from right to left). This embodiment helps compensate for off-track writes that may occur on either or both sides of the target data track. Also in this embodiment, the radial offsets of the read element 68 as shown in FIG. 6 may include offsets toward both of the left and right adjacent data tracks.

Any suitable control circuitry may be employed to implement the flow diagrams in the above embodiments, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain operations described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into a SOC.

In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.

While the above examples concern a disk drive, the various embodiments are not limited to a disk drive and can be applied to other data storage devices and systems, such as magnetic tape drives, solid state drives, hybrid drives, etc. In addition, some embodiments may include electronic devices such as computing devices, data server devices, media content storage devices, etc. that comprise the storage media and/or control circuitry as described above.

The various features and processes described above may be used independently of one another, or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of this disclosure. In addition, certain method, event or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate. For example, described tasks or events may be performed in an order other than that specifically disclosed, or multiple may be combined in a single block or state. The example tasks or events may be performed in serial, in parallel, or in some other manner. Tasks or events may be added to or removed from the disclosed example embodiments. The example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed example embodiments.

While certain example embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions disclosed herein. Thus, nothing in the foregoing description is intended to imply that any particular feature, characteristic, step, module, or block is necessary or indispensable. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the embodiments disclosed herein.