Self-adaptive voltage scaling

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of U.S. Provisional Application No. 61/904,423 filed Nov. 14, 2013, the disclosure of which is hereby incorporated in its entirety by reference.

BACKGROUND

1. Technical Field

Apparatuses and methods consistent with the present inventive concept relate to power supplies, and more particularly to self-adaptive voltage scaling for power supply regulation.

2. Related Art

A System-On-Chip (SOC) may provide the components necessary to control operation of a storage device, for example, a hard disk drive, a hybrid hard drive, etc. The SOC may have different operational modes, for example, an idle mode during which the SOC consumes a least amount of power and an active mode during which the SOC consumes significantly more power than the idle mode.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects and features of the present inventive concept will be more apparent by describing example embodiments with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a power system according to example embodiments of the present inventive concept;

FIG. 2 is a graph illustrating an output voltage response to a load for a conventional regulated power supply;

FIG. 3 is a circuit diagram illustrating a regulator circuit according to example embodiments of the present inventive concept;

FIG. 4 is a block diagram illustrating a logic circuit according to example embodiments of the present inventive concept;

FIG. 5 is a graph illustrating an output voltage response to a load for a regulated power supply in a self-adaptive voltage scaling mode according to example embodiments of the present inventive concept;

FIG. 6 is a circuit diagram illustrating a regulator circuit according to example embodiments of the present inventive concept;

FIG. 7 is a flow chart illustrating a method according to example embodiments of the present inventive concept; and

FIG. 8 is a flow chart illustrating another method according to example embodiments of the present inventive concept.

DETAILED DESCRIPTION

While certain embodiments are described, these embodiments are presented by way of example only, and are not intended to limit the scope of protection. The methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and changes in the form of the example methods and systems described herein may be made without departing from the scope of protection.

Overview

During the active mode of the SOC, SOC operation can cause high power supply loads and large load steps. Power supply regulators must be designed to handle maximum output current, for example, 2 amps (A) as well as sudden load increases, for example, a load step from 200 mA to 2 A (i.e., a load step of 1.8 A) within microseconds, while maintaining the output voltage within upper and lower specification limits.

However, the storage device may be operating in idle mode at low current for an extended period of time. If the power supply regulator output voltage is set to handle a large current step while staying within specification during a load step, but the load step does not happen for a long time, power is wasted.

FIG. 1 is a block diagram illustrating a power system according to example embodiments of the present inventive concept. Referring to FIG. 1, a power integrated circuit (IC) 110 may include one or more regulators 140a-140c to provide regulated output voltages and/or currents. One or more regulated output voltages may be supplied to various devices, i.e., loads, for example, but not limited to, an SOC 120, a memory 130, etc. Each load may have voltage and current requirements that a regulator 140a-140c maintains within predetermined upper and lower limits.

FIG. 2 is a graph illustrating an output voltage response to an SOC load for a conventional regulated power supply. As illustrated in FIG. 2, a power supply regulator provides an output voltage 200 between an upper voltage limit 210 and a lower voltage limit 215. With the storage device operating in idle mode for an extended period of time, the SOC may require only a low operating current 220, for example, about 200 mA, and the power supply regulator operates to maintain a specified output voltage 205.

However, a transition of the storage device to an active mode may result in a step 225 in load current, for example, up to 2 A 230, by the SOC. As a result of the step 225 in load current, the specified output voltage 205 may drop 235 and then achieve a steady state voltage 240 lower than the specified output voltage 205 during idle mode operation. Similarly, when the storage device returns to idle mode operation, the load current requirement of the SOC drops 245 causing a large spike 250 in the output voltage 200 before the output voltage achieve a steady state 255.

Some embodiments of the present inventive concept provide apparatuses and methods for self-adaptive voltage scaling for power supply regulation.

Regulator Circuit

FIG. 3 is a circuit diagram illustrating a regulator circuit according to example embodiments of the present inventive concept. The regulator circuit 300 may include a switching circuit 305, a current detector 315, a logic circuit 320, a digital-to-analog converter (DAC) 330, and an adjustment circuit 340.

The switching circuit 305 may be configured to generate a duty cycle to regulate an output voltage 390. The current detector 315 may be configured to sense a load current 325 and convert the sensed load current to a DC current sense signal 317. The DC current sense signal 317 may be a voltage signal.

The adjustment circuit 340 may include a logic circuit 320, and a digital-to-analog converter (DAC) 330. The logic circuit 320 may be configured to input the DC current sense signal 317 and generate an adjustment signal 322 based on the DC current sense signal 317. The DAC 330 may be configured to input the adjustment signal 322 and generate an output voltage control signal 332 based on the adjustment signal 322. If the DC current sense signal 317 is increasing, the output voltage control signal 332 may provide an increasing feedback voltage to the switching circuit 305 that is proportional to the increasing load current 325. If the DC current sense signal 317 is decreasing, the output voltage control signal 332 may provide a decreasing feedback voltage to the switching circuit 305 that is proportional to the decreasing load current 325.

The output voltage control signal 332 generated by the DAC 330 may cause the output voltage 390 to increase or decrease within predetermined upper and lower limits. In various embodiments, the output voltage 390 may be adjusted within the predetermined upper and lower voltage limits proportionally to changes in the DC current sense signal 317.

FIG. 4 is a block diagram illustrating a logic circuit according to example embodiments of the present inventive concept. Referring to FIGS. 3 and 4, the logic circuit 320 may include an analog-to-digital converter (ADC) 421, a digital controller 423, a serial port register 425, and a switch 427.

The ADC 421 may be configured to input the DC current sense signal 317 and based on the DC current sense signal 317 generate an ADC output signal 424 to the digital controller 423. The serial port register 425 may be user-programmable. Upper and lower output voltage limits may be programmed in the serial port register 425. The serial port register 425 may be configured to generate a register output signal 426 to the digital controller 423 indicating the predetermined upper and lower output voltage limits. The serial port register 425 may be further configured to generate a first DAC setting signal 429.

The digital controller 423 may be configured to input the ADC output signal 424 from the ADC 421 and the register output signal 426 from the serial port register 425 and based on those signals determine a setting for the DAC 330 and output a second DAC setting signal 428.

The switch 427 may be configured to select a first position “A” or to a second position “B”. With the switch 427 in position “A”, the first DAC setting signal 429 from the serial port register 425 may be output from the logic circuit as the adjustment signal 322 to the DAC 330.

With the switch 427 in position “B”, the regulator circuit 300 may be in a self-adaptive voltage scaling mode according to various embodiments, and the second DAC setting signal 428 from the digital controller may be output from the logic circuit 320 as the adjustment signal 322 to the DAC 330.

In various embodiments, the adjustment circuit 340 may be configured to adjust the output voltage 390 to a predetermined minimum output voltage in response to a value of the DC current sense signal 317 less than a threshold value, and to adjust the output voltage 390 higher than the predetermined minimum output voltage in response to a value of the DC current sense signal 317 equal to or greater than the threshold value.

FIG. 5 is a graph illustrating an output voltage response to a load for a regulated power supply operating in a self-adaptive voltage scaling mode according to example embodiments of the present inventive concept. FIG. 5 shows the output voltage 390 response to changes in the DC current sense signal 317 resulting from changes in the load current 325. Referring to FIGS. 3-5, a regulator circuit 300 operating in a self-adaptive voltage scaling mode may operate to maintain an output voltage 390 between a predetermined upper voltage limit 510 and a predetermined lower voltage limit 515. For a low load current 325, for example, about 200 mA, the value 520 of the DC current sense signal 317 may be less than a predetermined threshold value 525.

In response to a value of the DC current sense signal 317 less than the predetermined threshold value 525, the regulator circuit 300 may adjust the output voltage 390 to a predetermined minimum output voltage 530. When the load current 325 increases, the value of the DC current sense signal 317 may increase to a value 535 equal to or greater than the predetermined threshold value 525. In response, the regulator circuit 300 may adjust the output voltage 390 to a value 540 higher than the predetermined minimum output voltage 530. Similarly, when the load current 325 again decreases, the value of the DC current sense signal 317 may decrease to a value 545 below the predetermined threshold value 525, the regulator circuit 300 may adjust the output voltage 390 back to the predetermined minimum output voltage 530.

It should also be noted that for step increases and decreases in load current 325, output voltage 390 undershoot 550 and overshoot 555 may be reduced for the regulator circuit 300 operating in a self-adaptive voltage scaling mode according to various embodiments as compared to conventional regulator circuit operation.

FIG. 6 is a circuit diagram illustrating a regulator circuit according to example embodiments of the present inventive concept. The regulator circuit 600 may include a switching circuit 305, a logic circuit 320, a digital-to-analog converter (DAC) 330, an adjustment circuit 340, and an amplifier 610.

The switching circuit 305, logic circuit 320, DAC 330, and adjustment circuit 340 operate as described with respect to FIG. 3 and their operation will not be further explained here.

The amplifier 610 may be configured to sense a voltage drop across a first resistive element 620 resulting from a load current 625 flowing through the first resistive element 620. The first resistive element 620 may be, for example, but not limited to, one or more fixed or trimmable resistors, or other resistive device producing a voltage drop proportional to current through the device.

The amplifier 610 may be configured to convert the sensed load current 625 to a DC current sense signal 617. The DC current sense signal 617. may be a voltage signal. The DC current sense signal 617 may be input to the logic circuit 320 in the adjustment circuit 340, and operation of the regulator circuit 600 may be as explained with respect to FIGS. 3 and 5, where the DC current sense signal 617 from the amplifier 610 may be input to the logic circuit 320 in place of the DC current sense signal 317 from the current detector 315.

FIG. 7 is a flow chart illustrating a method according to example embodiments of the present inventive concept. Referring to FIGS. 3-7, the upper and lower output voltage limits may be set by programming the serial port register 425. The serial port register 425 may be configured to generate a register output signal 426 to the digital controller 423 indicating the predetermined upper and lower output voltage limits (710).

In some embodiments, load current 325 may be monitored using a current detector 315 that may be configured to sense the load current 325 and convert the sensed load current to a DC current sense signal 317 (720). In some embodiments, load current 625 may be monitored using an amplifier 610 that may be configured to sense a voltage drop across a first resistive element 620 resulting from the load current 625 flowing through a first resistive element 620 and generate a DC current sense signal 617 (720).

If the load current 325, 625 is increasing (730), the DAC 330 may generate an output voltage control signal 332 to increase feedback voltage to the switching circuit 305 (740). The logic circuit 320 may generate an adjustment signal 322 to the DAC 330 based on the DC current sense signal 317, 617 to generate an increasing feedback voltage to the switching circuit 305 that is proportional to the increasing load current 325, 625.

If the load current 325, 625 is decreasing (750), the DAC 330 may generate an output voltage control signal 332 to decrease feedback voltage to the switching circuit 305 (760). The logic circuit 320 may generate an adjustment signal 322 to the DAC 330 based on the DC current sense signal 317, 617 to generate a decreasing feedback voltage proportional to the decreasing load current 325, 625.

FIG. 8 is a flow chart illustrating another method according to example embodiments of the present inventive concept. Referring to FIGS. 3-8, in some embodiments, load current may be sensed using a current detector 315 that may be configured to sense a load current 325 and convert the sensed load current to a DC current sense signal 317 (810). In some embodiments, load current may be sensed using an amplifier 610 that may be configured to sense a voltage drop across a first resistive element 620 resulting from the load current 625 flowing through a first resistive element 620 and generate a DC current sense signal 617.

The DC current sense signal 317, 617 may be input to a logic circuit 320 in an adjustment circuit 340, and the logic circuit 320 may generate an adjustment signal 322 based on the DC current sense signal 317, 617 (820).

The adjustment signal 322 may be input to a DAC 330, and based on the adjustment signal 322 the DAC 330 may generate an output voltage control signal 332 (830). The output voltage control signal 332 generated by the DAC 330 may cause the output voltage 390, 690 to increase or decrease within predetermined upper and lower limits (840). In various embodiments, the output voltage 390, 690 may be adjusted within the predetermined upper and lower voltage limits proportionally to changes in the DC current sense signal 317.

The output voltage 390, 690 may be adjusted to a predetermined minimum output voltage in response to a value of the sensed load current 325, 625 less than a threshold value, and the output voltage 390, 690 may be adjusted higher than a predetermined minimum output voltage in response to the value of the sensed load current 325, 625 equal to or greater than a threshold value.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the protection. The methods and systems described herein may be embodied in a variety of other forms. Various omissions, substitutions, and/or changes in the form of the example methods and systems described herein may be made without departing from the spirit of the protection.

The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the protection. For example, the example systems and methods disclosed herein can be applied to hard disk drives, hybrid hard drives, and the like. As another example, the various components illustrated in the figures may be implemented as software and/or firmware on a processor, ASIC/FPGA, or dedicated hardware. Also, the features and attributes of the specific example embodiments disclosed above may be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure.

Although the present disclosure provides certain example embodiments and applications, other embodiments that are apparent to those of ordinary skill in the art, including embodiments which do not provide all of the features and advantages set forth herein, are also within the scope of this disclosure. Accordingly, the scope of the present disclosure is intended to be defined only by reference to the appended claims.