Method and apparatus for estimating and compensating for in-phase and quadrature (IQ) mismatch in a receiver of a wireless communication device

Description

CROSS REFERENCE TO RELATED APPLICATION

This disclosure claims the benefit of the priority of U.S. Provisional Application Ser. No. 61/858,024, filed Jul. 24, 2013 and entitled “Receiver IQ Mismatch Estimation and Calibration.” The above-identified application is incorporated herein by reference in its entirety.

BACKGROUND

Communication devices can use analog quadrature down-mixing on a received signal to produce signals on an in-phase (I) branch and a quadrature (Q) branch. Due to hardware imperfections or differences between the I and Q branches, there may exist an in-phase/quadrature (IQ) mismatch between the I and Q branches. Devices can use one or more techniques to estimate and compensate for the IQ mismatch. Such techniques can include blind estimation, non-blind estimation, adaptive estimation, or non-adaptive estimation.

Devices such as wireless communication devices can use one or more wireless communication technologies such as orthogonal frequency division multiplexing (OFDM), code division multiple access (CDMA), or direct-sequence spread spectrum (DSSS). Wireless communication devices can communicate based on one or more wireless standards such as Bluetooth, wireless local area network (WLAN) standards such as IEEE 802.11 standards, or a ZigBee standard. Various examples of wireless communication devices include mobile phones, smart phones, wireless routers, wireless hubs, base stations, and access points. In some cases, wireless communication electronics are integrated with data processing equipment such as laptops, personal digital assistants, and computers.

SUMMARY

The present disclosure includes systems and techniques related to IQ mismatch estimation and compensation.

According to an aspect of the described systems and techniques, a method for IQ mismatch estimation and compensation includes obtaining samples of a received signal via circuitry having an IQ mismatch, the samples including (i) first samples, including in-phase first samples and quadrature first samples, of a training signal of the received signal and (ii) second samples, including in-phase second samples and quadrature second samples, of a data signal of the received signal; determining an estimated gain imbalance parameter for the IQ mismatch based on an in-phase average value and a quadrature average value, the in-phase average value being based on the in-phase first samples, and the quadrature average value being based on the quadrature first samples; determining an estimated phase imbalance parameter for the IQ mismatch based on a combined average value, the estimated gain imbalance parameter, and a squared average value, the combined average value being based on a pair-wise multiplication of the in-phase first samples and the quadrature first samples, the squared average value being based on squared versions of the in-phase first samples; updating the in-phase second samples based on the estimated gain imbalance parameter to produce updated in-phase second samples; and updating the quadrature second samples by respectively adding thereto quadrature update values to produce updated quadrature second samples, the quadrature update values being respectively based on the estimated phase imbalance parameter and the updated in-phase second samples. Other implementations are directed to systems, devices and computer-readable, storage mediums.

These and other implementations can include one or more of the following features. Determining the estimated gain imbalance parameter can include calculating in accordance with

ɛ est = E ⁡ [ Q ′ ] E ⁡ [ I ′ ] - 1 ,
where ε_est represents the estimated gain imbalance parameter, E[Q′] represents the quadrature average value, and E[I′] represents the in-phase average value. Determining the estimated phase imbalance parameter can include calculating in accordance with

ϕ est = E ⁡ [ I ′ · Q ′ ] - E ⁡ [ I ′ ⁢ ⁢ 2 ] · ( 1 + ɛ est ) / 4 ,
where φ_est represents the estimated phase imbalance parameter, E[I′·Q′] represents the combined average value, and E[I′²] represents the squared average value. Updating the in-phase second samples can include multiplicatively applying a factor based on ε_est to each of the in-phase second samples. Updating the quadrature second samples can include multiplicatively applying a factor based on φ_est to each of the updated in-phase second samples to respectively produce the quadrature update values. Determining the estimated phase imbalance parameter can include calculating in accordance with

ϕ est = arcsin ⁡ ( E ⁡ [ I ′ · Q ′ ] - E ⁡ [ I ′ ⁢ ⁢ 2 ] · ( 1 + ɛ est ) / 4 ) ,
where φ_est represents the estimated phase imbalance parameter, E[I′·Q′] represents the combined average value, and E[I′²] represents the squared average value. In some implementations, the training signal can include a single tone signal. In some implementations, the training signal corresponds to a preamble portion of a packet, and the data signal corresponds to a data portion of the packet.

In another aspect, a method for IQ mismatch estimation and compensation includes obtaining I samples and Q of a training signal received via circuitry having an IQ mismatch; estimating an IQ gain imbalance for the circuitry using an approximation formed from a summation of Q samples in relation to a summation of I samples; estimating an IQ phase imbalance for the circuitry using an approximation formed from a summation of a combination of the Q samples and the I samples; using the estimated IQ gain imbalance to update a gain compensation on an I branch of the circuitry; and using the estimated IQ phase imbalance and the updated gain compensation on the I branch to update a phase compensation on a Q branch of the circuitry.

The described systems and techniques can be implemented in electronic circuitry, computer hardware, firmware, software, or in combinations of them, such as the structural means disclosed in this specification and structural equivalents thereof. This can include at least one computer-readable medium embodying a program operable to cause one or more data processing apparatus (e.g., a signal processing device including a programmable processor) to perform operations described. Thus, program implementations can be realized from a disclosed method, system, or apparatus, and apparatus implementations can be realized from a disclosed system, computer-readable medium, or method. Similarly, method implementations can be realized from a disclosed system, computer-readable medium, or apparatus, and system implementations can be realized from a disclosed method, computer-readable medium, or apparatus.

For example, one or more disclosed embodiments can be implemented in various systems and apparatus, including, but not limited to, a special purpose data processing apparatus (e.g., a wireless communication device such as a wireless access point, a remote environment monitor, a router, a switch, a computer system component, a medium access unit), a mobile data processing apparatus (e.g., a wireless client, a cellular telephone, a smart phone, a personal digital assistant (PDA), a mobile computer, a digital camera), a general purpose data processing apparatus such as a computer, or combinations of these.

In another aspect, an apparatus for IQ mismatch estimation and compensation can include first circuitry and second circuitry coupled with the first circuitry. The first circuitry can be configured to determine an in-phase average value based on (i) in-phase first samples of a training signal received via circuitry having an IQ mismatch, (ii) a quadrature average value based on quadrature first samples of the training signal, (iii) a squared average value based on squared versions of the in-phase first samples, and (iv) a combined average value based on a pair-wise multiplication of the in-phase first samples and the quadrature first samples; determine an estimated gain imbalance parameter for the IQ mismatch based on the in-phase average value and the quadrature average value; and determine an estimated phase imbalance parameter for the IQ mismatch based on (i) the combined average value, (ii) the estimated gain imbalance parameter, and (iii) the squared average value. The second circuitry can be configured to update in-phase second samples of a data signal received via the circuitry having the IQ mismatch based on the estimated gain imbalance parameter to produce updated in-phase second samples, and update quadrature second samples of the data signal by respectively adding quadrature update values to the quadrature second samples to produce updated quadrature second samples, the quadrature update values being respectively based on (i) the estimated phase imbalance parameter and (ii) the updated in-phase second samples.

In another aspect, a system for IQ mismatch estimation and compensation can include a downconverter configured to receive signals including a training signal and a data signal; an analog-to-digital convertor coupled with the downconverter, and configured to produce samples based on the receive signals, the samples including (i) first samples of the training signal and (ii) second samples of the data signal, the first samples including (i) in-phase first samples and (ii) quadrature first samples, the second samples including (i) in-phase second samples and (ii) quadrature second samples; and a processor coupled with the convertor. The processor can be configured to perform operations including: determining an in-phase expected value based on (i) the in-phase first samples, (ii) a quadrature expected value based on the quadrature first samples, (iii) a squared expected value based on squared versions of the in-phase first samples, and (iv) a combined expected value based on a pair-wise multiplication of the in-phase first samples and the quadrature first samples; determining an estimated gain imbalance parameter for an IQ mismatch associated with at least the downconverter based on (i) the in-phase expected value and (ii) the quadrature expected value; determining an estimated phase imbalance parameter for the IQ mismatch based on (i) the combined expected value, (ii) the estimated gain imbalance parameter, and (iii) the squared expected value; updating the in-phase second samples based on the estimated gain imbalance parameter to produce updated in-phase second samples; and updating the quadrature second samples by respectively adding thereto quadrature update values to produce updated quadrature second samples, the quadrature update values being respectively based on the estimated phase imbalance parameter and the updated in-phase second samples.

Particular configurations of the technology described in this disclosure can be implemented so as to realize one or more of the following potential advantages. A described IQ mismatch estimation and compensation technique can achieve a high image rejection ratio such as better than −60 dBc (decibels relative to carrier). A described IQ mismatch estimation and compensation technique can be implemented using low-complexity circuitry, algorithms, or both, which correspond to efficient approximations of IQ mismatch estimation and calibration that can enable lower-cost devices to be manufactured. Practical analog front-end impairments can be considered in the design, and competitive performance can be achieved in the practical scenarios for device deployment.

Details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages may be apparent from the description and drawings, and from the claims.

DRAWING DESCRIPTIONS

FIG. 1 shows an architecture for an example of a wireless communication device, which includes an IQ mismatch estimator and an IQ mismatch compensator.

FIG. 2 shows an example of a wireless network with two wireless communication devices.

FIG. 3 shows a layout for an example of a packet transmitted by a device.

FIGS. 4A and 4B show a simplified diagram for an example of a device configured to perform IQ estimation and compensation on a received version of the packet of FIG. 3.

FIG. 5 shows a graph for an example of mirror frequency interference caused by an IQ mismatch.

FIG. 6 shows a flowchart for an example of an IQ mismatch estimation process.

FIG. 7 shows a flowchart for an example of an IQ mismatch compensation process.

FIG. 8 shows a flowchart for an example of an IQ mismatch estimation and compensation process.

FIG. 9 shows a graph depicting the image rejection performance of a described technology.

FIG. 10 shows another graph depicting the image rejection performance of a described technology.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

FIG. 1 shows an architecture for an example of a wireless communication device 101, which includes an IQ mismatch estimator 145 and IQ mismatch compensator 150. The device further includes an antenna 105, analog front-end circuitry 110, mixers 115a-b, local oscillator 120, phase shifter 125, filters 130a-b, analog-to-digital converters (ADCs) 135a-b, and a digital baseband processor 140. The analog front-end circuitry 110 can include a downconverter to convert a carrier band signal into a baseband signal. The mixers 115a-b can further downconvert the baseband signal into an I signal and a Q signal respectively. The processor 140 can be configured to perform IQ mismatch estimation and compensation via estimator 145 and compensator 150 respectively. The estimator 145 can estimate parameters for an IQ mismatch associated with circuitry such IQ circuitry of the device 101 which can include mixers 115a-b, local oscillator 120, phase shifter 125, filters 130a-b, ADCs 135a-b, or a combination thereof.

An IQ mismatch or imbalance can exist between the mixers 115a-b due to factors such as manufacturing imperfections or variations in a device's physical characteristics. The input to the I mixer 115a can be modeled as cos(2πf_LOt), where f_LO represents a frequency of the local oscillator 120. The input to the Q mixer 115b can be modeled as −α·sin(2πf_LOt+φ). The IQ imbalance includes a gain imbalance ε=α−1, and a phase imbalance φ. An image rejection ratio (IRR) can be defined as follows:

IRR = ⁢ 1 + ( 1 + ɛ ) 2 - 2 ⁢ ( 1 + ɛ ) ⁢ cos ⁢ ⁢ ϕ 1 + ( 1 + ɛ ) 2 + 2 ⁢ ( 1 + ɛ ) ⁢ cos ⁢ ⁢ ϕ ≈ ⁢ ɛ 2 + ϕ 2 4 .
In some implementations, a −60 dBc IRR can be targeted such that after an IQ mismatch calibration, a residual gain imbalance and a residual phase imbalance should satisfy the following respectively: ε_r<10⁻³ and φ_r<0.05. Other tolerances for residual imbalances are possible and can be based on one or more design goals of a device.

In some implementations, the digital baseband processor 140 includes two or more processor cores. In some implementations, the device 101 includes a system-on-a-chip (SoC). For example, the SoC can include a host processor and a digital signal processor configured as the digital baseband processor 140. In some implementations, the antenna 105 is one of many antennas, which can be configured for multiple-in-multiple-out (MIMO) wireless communications.

FIG. 2 shows an example of a wireless network with two wireless communication devices. Wireless communication devices 205, 207 such as an access point (AP), base station (BS), wireless headset, access terminal (AT), client station, or mobile station (MS) can include circuitry such as processor electronics 210, 212. Circuitry such as processor electronics 210, 212 can include one or more processors that implement one or more techniques presented in this disclosure. Wireless communication devices 205, 207 include circuitry such as transceiver electronics 215, 217 to send and receive wireless signals over one or more antennas 220a-b, 222a-b. In some implementations, transceiver electronics 215, 217 include integrated transmitting and receiving circuitry. Wireless communication devices 205, 207 include one or more memories 225, 227 configured to store information such as data, instructions, or both. In some implementations, wireless communication devices 205, 207 include dedicated circuitry for transmitting and dedicated circuitry for receiving. The transceiver electronics 215, 217 can include circuitry having an IQ mismatch. Further, the memories 225, 227 can store an IQ estimation and compensation technique as described herein to handle the IQ mismatch.

FIG. 3 shows a layout for an example of a packet 300 transmitted by a device. The packet 300 includes a preamble portion 310 and a data portion 320. The preamble portion 310 includes a baseband waveform 330 having a single tone signal that represents one or more training symbols. The data portion 320 includes one or more data symbols. In some implementations, the baseband waveform 330 is based on s(t)=exp(j·2πf_sigt), where f_sig is a frequency component of the baseband waveform 330. Hence, the baseband waveform 330 has an I branch component of I=cos(2πf_sigt) and a Q branch component of Q=sin(2πf_sigt). Baseband signals representing the packet 300 can be up-converted to a carrier band for transmission.

FIGS. 4A and 4B show a simplified diagram for an example of a device 401 configured to perform IQ estimation and compensation on a received version of the packet of FIG. 3. FIG. 4A shows a diagram of a portion of the device 401 that includes an IQ mismatch estimator 435. The device 401 includes an antenna 405, low-noise amplifier (LNA) 410, mixer 415, analog low pass filter (LPF) 420, baseband (BB) circuitry 425, ADC 430, and IQ mismatch estimator 435. The mixer 415 can perform a downconversion from a carrier band signal into a baseband signal. In some implementations, the ADC 430 is operated at 12 Mhz, other frequencies are possible. In some implementations, the circuitry 425 includes the ADC 430. The circuitry 425 can include an I branch and a Q branch that respectively include an I mixer and a Q mixer that are configured to downconvert an output of the LPF 420 into I and Q signals respectively. In some implementations, the ADC 430 includes a first ADC for converting the I branch signals and a second ADC for converting the Q branch signals.

During an estimation mode, the device 401 uses the IQ mismatch estimator 435 to produce estimated parameters for an IQ mismatch associated with at least circuitry 425. After IQ downconversion, an IQ mismatch is introduced which can be modeled as

I ′ = 1 2 ⁢ I
and

Q ′ = - 1 + ɛ 2 ⁢ sin ⁢ ⁢ ϕ · I + 1 + ɛ 2 ⁢ cos ⁢ ⁢ ϕ · Q ,
where I′ and Q′ respectively represent the IQ mismatch versions of I and Q. The gain imbalance can be estimated as follows. Note that

{ E ⁡ [ I ′ ⁢ ⁢ 2 ] = 1 4 ⁢ E ⁡ [ I 2 ]     E ⁡ [ Q ′ ⁢ ⁢ 2 ] = ( 1 + ɛ ) 2 4 ⁢ E ⁡ [ Q 2 ] + sin ⁢ ⁢ 2 ⁢ ϕ ⁢ ⁢ E ⁡ [ I · Q ] = ( 1 + ɛ ) 2 4 ⁢ E ⁡ [ I 2 ] ⁢
where E[·] represents an expected value function. This pair of expected value equations can be substituted with:

{ E ⁡ [ I ′ ] = 1 2 ⁢ E ⁡ [ I ] E ⁡ [ Q ′ ] = ( 1 + ɛ ) 2 ⁢ E ⁡ [ I ]
and the estimated gain imbalance can be computed as follows:

ɛ est = E ⁡ [ Q ′ ] E ⁡ [ I ′ ] - 1.
In some implementations, an expected value of the I samples is based on an average of the I samples, and an expected value of the Q samples is based on an average of the Q samples. In some implementations, the estimated gain imbalance is calculated based on a sum of Q samples and a sum of I samples. The phase imbalance can be estimated as follows. Note that

E ⁡ [ I ′ · Q ′ ] = - ( 1 + ɛ est ) 4 ⁢ sin ⁢ ⁢ ϕ · E ⁡ [ I 2 ]
and the estimated phase imbalance can be computed as follows:

ϕ est = arcsin ⁡ ( E ⁡ [ I ′ · Q ′ ] - E ⁡ [ I ′ ⁢ ⁢ 2 ] · ( 1 + ɛ est ) / 4 ) .
For small θ, arcsin(θ) can be approximated by using θ itself. As a result,

ϕ est ≈ E ⁡ [ I ′ · Q ′ ] - E ⁡ [ I ′ ⁢ ⁢ 2 ] · ( 1 + ɛ est ) / 4
The IQ mismatch estimator 435 can provide parameters including ε_est and φ_est to an IQ mismatch compensator.

FIG. 4B shows a diagram of a portion of the device 401 that includes an IQ mismatch compensator 440. During a compensation mode, the device 401 uses an IQ mismatch compensator 440 to update samples received from the ADC 430 based on the estimated parameters determined by the IQ mismatch estimator 435. In some implementations, IQ mismatch estimator 435 retrieves parameters including ε_est and φ_est from the IQ mismatch estimator 435 via a memory (not shown). The IQ mismatch compensator 440 can perform gain compensation on the I branch based on

I update = ( 1 + ɛ est ) ⁢ I ′ 2 .
For phase compensation on the Q branch, note that

Q ′ = - 1 + ɛ 2 ⁢ sin ⁢ ⁢ ϕ · I + 1 + ɛ 2 ⁢ cos ⁢ ⁢ ϕ · Q ;
also note that

Q update = ( 1 + ɛ est ) ⁢ Q 2
should hold. As a result, the IQ mismatch compensator 440 can perform phase compensation on the Q branch based on

Q update = Q ′ + 1 + ɛ est 2 ⁢ sin ⁢ ⁢ ϕ est · I ′ cos ⁢ ⁢ ϕ est .
Using an approximation, the IQ mismatch compensator 440 can perform phase compensation on the Q branch based on Q_update≈Q′+φ_est·I_update.

FIG. 5 shows a graph 501 for an example of mirror frequency interference caused by an IQ mismatch. An IQ mismatch is commonly seen in a RF front-end that uses analog quadrature down-mixing. It results in mirror frequency interference. As shown in a frequency domain, strong subband signals 510a-b can generate severe interference to weaker subband signals 520a-b in mirror positions. In this example, the mirror frequency interferences corresponding to the strong subband signals 510a-b are shown by interference signals 530a-b. The mirror frequency interferences corresponding to the weaker subband signals 520a-b are shown by interference signals 540a-b. Since the strong subband signals 510a-b produce strong interference signals 530a-b that overlap with the weaker subband signals 520a-b, a high detection error rate can occur for the weaker subband signals 520a-b. In some implementations, the strong subband signals 510a-b can correspond to WLAN signals, and the weaker subband signals 520a-b can correspond to Zigbee signals.

FIG. 6 shows a flowchart for an example of an IQ mismatch estimation process. At 605, the process obtains samples of a received training signal (referred to herein as “training samples”) via circuitry having an IQ mismatch. The training samples can include in-phase training samples and quadrature training samples. Obtaining training samples can include retrieving in-phase samples from an ADC associated with an in-phase branch and retrieving quadrature samples from an ADC associated with a quadrature branch. In some implementations, in-phase training samples and quadrature training samples are placed in two respective arrays in a memory. In some implementations, a training signal is a single tone signal; the tone signal can be predetermined and known to both sides. In some implementations, a training signal is located within a preamble portion of a packet.

At 610, the process determines an in-phase average value based on the in-phase training samples. Determining the in-phase average value can include averaging N in-phase samples, where N is greater than one. At 615, the process determines a quadrature average value based on the quadrature training samples. Determining the quadrature average value can include averaging N quadrature samples. At 620, the process determines a squared average value based on squared versions of the in-phase training samples. Determining the squared average value can include squaring N in-phase samples, and averaging over the resulting values.

At 625, the process determines a combined average value based on a pair-wise multiplication of the in-phase training samples and the quadrature training samples. The pair-wise multiplication can include computing c_i=a_i·b_i, i=1, 2, . . . , N where a_i represents an in-phase training sample and b_i represents a quadrature training sample. Determining the combined average value can include computing

c ^ = 1 N ⁢ ∑ 1 N ⁢ ⁢ c i .

At 630, the process determines an estimated gain imbalance parameter for the IQ mismatch based on the in-phase average value and the quadrature average value. Determining the estimated gain imbalance parameter can include calculating

ɛ est = E ⁡ [ Q ′ ] E ⁡ [ I ′ ] - 1 ,
where E[Q′] represents the quadrature average value, and E[I′] represents the in-phase average value.

At 635, the process determines an estimated phase imbalance parameter for the IQ mismatch based on the combined average value, the estimated gain imbalance parameter, and the squared average value. Determining the estimated phase imbalance parameter can include calculating:

ϕ est = arcsin ⁡ ( E ⁡ [ I ′ · Q ′ ] - E ⁡ [ I ′2 ] · ( 1 + ɛ est ) / 4 ) ,
where E[I′·Q′] represents the combined average value, and E[I′²] represents the squared average value. In some implementations, determining the estimated phase imbalance parameter can include calculating:

ϕ est = E ⁡ [ I ′ · Q ′ ] - E ⁡ [ I ′ 2 ] · ( 1 + ɛ est ) / 4 .
The process can include storing the estimated phase imbalance parameter and the estimated gain imbalance parameter for use by an IQ mismatch compensation process

FIG. 7 shows a flowchart for an example of an IQ mismatch compensation process. At 705, the process retrieves an estimated gain imbalance parameter and an estimated phase imbalance parameter associated with circuitry having an IQ mismatch. Retrieving the parameters can include accessing values from a memory. At 710, the process obtains samples of a received data signal (referred to herein as “data samples”) via the circuitry having the IQ mismatch. The data samples can include in-phase data samples and quadrature data samples. Obtaining data samples can include retrieving in-phase samples from an ADC associated with an in-phase branch and retrieving quadrature samples from an ADC associated with a quadrature branch. In some implementations, in-phase data samples and quadrature data samples are placed in two respective arrays in a memory. In some implementations, a data signal corresponds to a data portion of a packet, where the data portion includes information content that is not predetermined.

At 715, the process updates the in-phase data samples based on the estimated gain imbalance parameter to produce updated in-phase data samples. Updating the in-phase data samples can include multiplicatively applying a factor based on ε_est to each of the in-phase data samples. In some implementations, the applied factor is (1+ε_est)/2.

At 720, the process determines quadrature update values based on the estimated phase imbalance parameter and the updated in-phase data samples. Determining the quadrature update values can include calculating U_i=φ_estI″_i for i=1, 2 . . . M, where I″_i represents an updated in-phase data sample and U_i represents a quadrature update value. At 725, the process updates the quadrature data samples by respectively adding thereto the quadrature update values to produce updated quadrature data samples. Updating the quadrature data samples can include calculating Q″_i=Q′_i+U_i for i=1, 2, . . . , M, where Q′_i represents a quadrature data sample. In some implementations, M corresponds to a number of data samples corresponding to a data portion of a packet.

FIG. 8 shows a flowchart for an example of an IQ mismatch estimation and compensation process. At 805, the process detects an incoming signal. In some implementations, detecting the incoming signal can include using a preamble detector. At 810, the process receives a training signal of the incoming signal. In some implementations, the training signal is within a preamble portion of the incoming signal. At 815, the process determines whether to perform an IQ mismatch estimation. Determining whether to perform the IQ mismatch estimation can include determining whether IQ mismatch estimation parameters have been or have not been previously calculated. In some implementations, IQ mismatch estimation can be performed for every detected incoming signal. In some implementations, IQ mismatch estimation can be performed for one out of every K detected incoming signals, where K is a predetermined parameter. If IQ mismatch estimation is not required, the process continues at 830. Otherwise, at 820, the process performs the IQ mismatch estimation using the training signal. At 825, the process stores IQ mismatched estimated parameters. At 830, the process retrieves the IQ mismatch estimated parameters. At 835, the process receives a data signal of the incoming signal. At 840, the process performs IQ mismatch compensation on the data signal based on the IQ mismatch estimated parameters.

FIG. 9 shows a graph 901 depicting the image rejection performance of a described technology. The graph 901 includes three different plots 910a-c corresponding to different signal-to-noise-ratios (SNRs) of 20 dB, 30 dB, and 40 dB, respectively. The graph 901 shows a probability density function (PDF) output for each of the plots 910a-c against IRR (dB).

FIG. 10 shows another graph 1001 depicting the image rejection performance of a described technology. The graph 1001 includes three different plots 1010a-c corresponding to different signal-to-noise-ratios (SNRs) of 20 dB, 30 dB, and 40 dB, respectively. The graph 1001 shows a cumulative distribution function (CDF) output for each of the plots 1010a-c against IRR (dB). Note that at the 0.90 level for CDF, the IRR performance is about −65 dB for plot 1010b, which has a SNR of 30 dB.

A few embodiments have been described in detail above, and various modifications are possible. The disclosed subject matter, including the functional operations described in this specification, can be implemented in electronic circuitry, computer hardware, firmware, software, or in combinations of them, such as the structural means disclosed in this specification and structural equivalents thereof, including potentially a program operable to cause one or more data processing apparatus to perform the operations described (such as a program encoded in a computer-readable medium, which can be a memory device, a storage device, a machine-readable storage substrate, or other physical, machine-readable medium, or a combination of one or more of them).

The term “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

A program (also known as a computer program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.

While this specification contains many specifics, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments.

Other embodiments fall within the scope of the following claims.