Identification of data with predetermined data pattern

Description

BACKGROUND

Data Storage Devices (DSDs) are often used to record data onto or to reproduce data from storage media. DSDs can include different types of storage media, such as solid-state memory (e.g., flash memory) or a rotating magnetic disk. For such storage media, the DSD may use a logical to physical mapping that maps logical addresses for data to physical addresses indicating where the data is stored on the storage media.

In the case of solid-state memory, the DSD may use an indirection system to facilitate the rewriting of data associated with a particular logical address at different physical locations on the storage media. Such an indirection system may, for example, provide for wear leveling so that the solid-state memory is more evenly used to prolong a usable life of the solid-state memory.

A disk storage media may also use an indirection system to facilitate the rewriting of data associated with a particular logical address at different physical locations on the storage media. Such an indirection system may, for example, provide for sequential writing on the disk so that tracks can be written in an overlapping pattern using Shingled Magnetic Recording (SMR) to increase the amount of data stored in a given area on the disk. In such SMR DSDs, data is generally written sequentially to avoid rewriting an overlapped track on the disk since such rewriting would also adversely affect data written in an adjacent track.

Since the data capacity of storage media is generally limited, there is a need to conserve the physical space used for storing data on the storage media. This need is heightened for DSDs using an indirection system where data associated with a particular logical address is not rewritten in the same physical location on the storage media. The conservation of physical storage space typically becomes more important for such storage media since invalid or previous versions of data often remain in their old physical locations on the storage media until a maintenance operation such as garbage collection is performed to reclaim the portions of the storage media storing the invalid or obsolete data.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the embodiments of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. The drawings and the associated descriptions are provided to illustrate embodiments of the disclosure and not to limit the scope of what is claimed.

FIG. 1 is a block diagram depicting a data storage system including a Redundant Array of Independent Disks (RAID) according to an embodiment.

FIG. 2 is a block diagram depicting a Data Storage Device (DSD) of FIG. 1 according to an embodiment.

FIG. 3A is a conceptual diagram providing an example of the identification of a data pattern and the modification of a translation table to indicate that the data is associated with the data pattern according to an embodiment.

FIG. 3B is a conceptual diagram providing an example of data patterns stored in a memory according to an embodiment.

FIG. 3C is a conceptual diagram providing an example of the identification of the data pattern of FIG. 3A and further modification of the translation table of FIG. 3A according to an embodiment.

FIG. 4 is a flowchart for a data pattern identification process according to an embodiment.

FIG. 5 is a flowchart for a data pattern identification process for data received from a write command according to an embodiment.

FIG. 6 is a flowchart for a data pattern identification process for data previously stored in a DSD according to an embodiment.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth to provide a full understanding of the present disclosure. It will be apparent, however, to one of ordinary skill in the art that the various embodiments disclosed may be practiced without some of these specific details. In other instances, well-known structures and techniques have not been shown in detail to avoid unnecessarily obscuring the various embodiments.

Overview of Example System Environment

FIG. 1 shows data storage system 100 according to an embodiment which includes Redundant Array of Independent Disks (RAID) controller 101 in communication with Data Storage Devices (DSDs) 102, 104, 105, and 108 via communication bus 110. System 100 can be, for example, a data center storage system or a cloud-based storage system. In this regard, data storage system 100 may be a stand-alone system or part of a network, which can, for example, be a local or wide area network, or the Internet. In addition, RAID controller 101 and DSDs 102, 104, 105, and 108 need not be physically in the same location.

Those of ordinary skill in the art will appreciate that system 100 can include more or less than those elements shown in FIG. 1 and that the disclosed processes can be implemented in other environments

In the example embodiment of FIG. 1, RAID controller 101 can be implemented using one or more processors for executing instructions including a microcontroller, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), hard-wired logic, analog circuitry and/or a combination thereof. RAID controller 101 communicates with each of DSDs 102, 104, 105, and 108 to direct the storage of data among DSDs 102, 104, 105, and 108. As will be appreciated by those of ordinary skill in the art, RAID controller 101 may use a particular storage scheme or RAID level (e.g., RAID 0, 1, 5, 6) in determining which data to store on which DSD. The various storage schemes may provide for data redundancy and/or improved performance in accessing data from system 100.

Each of DSDs 102, 104, 105, and 108 can include storage media such as rotating magnetic disks and/or solid-state memory for storing data. As shown in the example of FIG. 1, each of DSDs 102, 104, 105, and 108 store approximately the same amount of data as indicated by the grey shading at the bottom of each of DSDs 102, 104, 105, and 108.

In the example of FIG. 1, DSD 105 is replaced by DSD 106. The replacement of DSD 105 may be due to a failure of DSD 105 or as a preventive measure to protect against the loss of data. When replacing DSD 105 with DSD 106, the data of DSDs 102, 104, and 108 can be used to reconstruct the data of DSD 105 in DSD 106 as part of a DSD rebuild process. As shown in FIG. 1, each of DSDs 102, 104, 105, and 108 includes a used portion 10 and an unused portion 12. In conventional rebuild processes, both used portion 10 and unused portion 12 would be used to generate data 14 for DSD 106 since neither a conventional RAID controller or DSD controller would recognize the difference between unused portions 12 and used portions 10. The conventional RAID rebuild process described above has a detrimental effect since it causes the additional consumption of the physical storage media of DSD 106. Such a RAID rebuild process can also add entries to a translation table used by DSD 106 for mapping logical addresses for unused portion 12 to physical addresses indicating storage locations in DSD 106.

In addition, the disproportionate consumption of physical media in DSD 106 relative to the other DSDs 102, 104, and 108 can create an imbalance of a garbage collection load across the DSDs when the rebuild operation is complete. As noted above, garbage collection can be performed to reclaim portions of the storage media storing invalid or obsolete data. In this case, the storage of data generated from unused portions 12 reduces the amount of free space available in DSD 106 and can increase the urgency for performing garbage collection.

The present disclosure provides for identifying a data pattern of particular data to be stored or already stored and indicating that the particular data is associated with the data pattern in a translation table. This arrangement ordinarily allows for a quicker rebuild process since unused portions 12 can be identified and do not need to be used to generate data for storage in DSD 106. The foregoing arrangement also allows for more over-provisioning with more unused space in DSD 106, which can improve the performance of DSD 106. In addition, the data pattern identification processes discussed below can ordinarily improve garbage collection by leveling the amount of data stored across the DSDs and decreasing the overall amount of garbage collection needed.

Although an example of a RAID rebuild process is provided in FIG. 1, other example applications exist where the disclosed data pattern identification processes can prevent invalid data from being written to a DSD. One example application is a full formatting of a Hard Disk Drive (HDD) using an operating system. In a conventional full formatting, the operating system scans for defective portions of the storage media by attempting to access each physical location on the storage media. The accessed data is rewritten to the storage media with zeros written to the storage media for the unused portions that were accessed.

By identifying a particular pattern of data, such as a pattern of all zeros, the formatting process can be performed quicker and consume less physical space on the storage media. For DSDs using an indirection system where data associated with a particular logical address is not rewritten in the same physical location, less garbage collection will ordinarily need to be performed. When garbage collection is performed, it can be done more efficiently since there is more free space available in the storage media.

FIG. 2 depicts a block diagram of DSD 106 according to an embodiment. In the embodiment of FIG. 2, DSD 106 is a Solid-State Hybrid Drive (SSHD) with a first storage media including magnetic recording media (e.g., disks in disk pack 150) and a second storage media including a solid-state media (e.g., solid-state memory 128). In other embodiments, each of disk pack 150 or solid-state memory 128 may be replaced by multiple HDDs or multiple Solid-State Drives (SSDs), respectively, so that DSD 106 includes pools of HDDs and/or SSDs. In addition, DSD 106 in other embodiments can include different types of recording media or may only include solid-state memory 128 or disk pack 150.

While the description herein refers to solid-state memory generally, it is understood that solid-state memory may comprise one or more of various types of memory devices such as flash integrated circuits, Chalcogenide RAM (C-RAM), Phase Change Memory (PC-RAM or PRAM), Programmable Metallization Cell RAM (PMC-RAM or PMCm), Ovonic Unified Memory (OUM), Resistance RAM (RRAM), NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory, or any combination thereof), NOR memory, EEPROM, Ferroelectric Memory (FeRAM), Magnetoresistive RAM (MRAM), other discrete NVM (non-volatile memory) chips, or any combination thereof.

DSD 106 includes DSD controller 120 which includes circuitry such as one or more processors for executing instructions and can include a microcontroller, a DSP, an ASIC, an FPGA, hard-wired logic, analog circuitry and/or a combination thereof. In one implementation, DSD controller 120 can include a system on a chip (SoC). In one embodiment, an SSD controller may be utilized that operates in conjunction with DSD controller 120 for controlling operation of solid-state memory 128.

Host interface 126 is configured to interface DSD 106 with RAID controller 101 and may interface according to a standard such as, for example, PCIe, SATA, or SAS. In a non-RAID environment, DSD 106 may communicate with a host, such as a host computer, instead of RAID controller 101 using host interface 126. As will be appreciated by those of ordinary skill in the art, host interface 126 can be included as part of controller 120. Although FIGS. 1 and 2 depict the co-location of RAID controller 101 and DSD 106, in other embodiments the two need not be physically co-located. In such embodiments, DSD 106 may be located remotely from RAID controller 101 and connected to RAID controller 101 via a network interface.

In the example of FIG. 2, the first memory of DSD 106 includes rotating magnetic disks arranged in disk pack 150 which is rotated by a spindle motor (not shown). DSD 106 also includes Head Stack Assembly (HSA) 136 connected to the distal end of actuator 130 which is rotated by Voice Coil Motor (VCM) 132 to position HSA 136 in relation to disk pack 150. DSD controller 120 can include servo control circuitry (not shown) to control the position of HSA 136 and the rotation of disk pack 150 using VCM control signal 30 and SM control signal 33, respectively.

Disk pack 150 comprises multiple disks that are radially aligned so as to rotate about a spindle motor. Each disk in disk pack 150 includes a number of radially spaced, concentric tracks 152 for storing data. HSA 136 includes multiple heads each arranged to read data from and write data to a corresponding surface of a disk in disk pack 150.

In some implementations, tracks 152 may overlap as a result of Shingled Magnetic Recording (SMR). SMR can provide a way of increasing the amount of data that can be stored in a given area on a disk by increasing the number of Tracks Per Inch (TPI). SMR increases TPI by using a relatively wide shingle write head to overlap tracks like roof shingles. The non-overlapping portion then serves as a narrow track that can be read by a narrower read head.

Although a higher number of TPI is ordinarily possible with SMR, the overlap in tracks can create a problem when writing data since new writes to a previously overlapped track affects data written in the overlapping track. For this reason, SMR tracks are generally sequentially written to avoid affecting previously written data.

Managing sequentially written data for SMR media typically includes the DSD using an indirection system to translate between different addressing schemes to ensure that data is sequentially written. When data is modified for a particular Logical Block Address (LBA), the indirection system allows the DSD to sequentially write the modified data to a new location and remap the LBA for the data to the new location. The old version of the data at the previous location becomes obsolete or invalid data.

In other implementations, tracks 152 may not overlap with SMR, but indirection may still be used to manage data stored in disk pack 150. One such example can involve using indirection to manage data stored in a media cache where physical addresses for certain data may be redirected to a location in the media cache storing a copy of the data.

Disk pack 150 also includes reserved area 154 which can be reserved for storing data patterns. As discussed in more detail below, one or more data patterns can be stored in reserved area 154 without having to store multiple copies of the data pattern in other areas of disk pack 150. Reserved area 154 is shown near an inner diameter position of disk pack 150. In other embodiments, the location of reserved area 154 can vary. In one such embodiment, reserved area 154 can be located in solid-state memory 128.

In the example of FIG. 2, DSD 106 also includes volatile memory 140. Volatile memory 140 can include, for example, a Dynamic Random Access Memory (DRAM) which can be used by DSD 106 to temporarily store data. Data stored in volatile memory 140 can include data read from Non-Volatile Memories (NVMs) (which may include disk pack 150 and solid-state memory 128), data to be written to NVMs, instructions loaded from DSD firmware 16 for execution by DSD controller 120, and/or data used in executing DSD firmware 16.

In the example of FIG. 2, volatile memory 140 is shown as storing DSD firmware 16, data pattern buffer 18, comparison buffer 20, translation table 22, and lookup table 24. DSD firmware 16 includes computer-executable instructions that can be executed by DSD controller 120 to perform the data pattern identification processes discussed below and to control operation of DSD 106.

As described in more detail below, data pattern buffer 18 and comparison buffer 20 can be used in implementing the data pattern identification processes disclosed herein. In more detail, data pattern buffer 18 can store a data pattern to be identified and comparison buffer 20 can store data to be compared with the data pattern stored in data pattern buffer 18 to determine whether the data stored in comparison buffer 20 includes the data pattern.

Translation table 22 can be used as part of an indirection system for disk pack 150 and/or for solid-state memory 128 to allow for the reassignment of logical addresses to different physical locations. DSD controller 120 may use translation table 22 to map logical addresses such as LBAs to physical addresses corresponding to locations where data is stored in disk pack 150 and/or solid-state memory 128. Translation table 22 may also be copied to NVM such as disk pack 150 or solid-state memory 128 so that translation table 22 is available across power cycles of DSD 106.

Lookup table 24 can store data patterns or definitions for certain data patterns so that the data patterns can be accessed or referenced when needed, such as in response to a read command from a host or RAID controller 101. In other embodiments, the data patterns may only be stored in data pattern buffer 18 or reserved area 154. In this regard, other embodiments may include one or more of data pattern buffer 18, lookup table 24, and reserved area 154. In yet other embodiments, a data pattern can be encoded as part of DSD firmware 16, controller hardware, or stored as part of translation table 22 without storing the data pattern in data pattern buffer 18, lookup table 24, or reserved area 154 (or other non-volatile memory location).

Solid-state memory 128 may use indirection to provide wear-leveling of cells 129 so that the usage of cells 129 is more evenly distributed. DSD controller 120 may use translation table 22 to map LBAs for data stored in cells 129 to different physical locations. Modified data can then be written to a new physical location in solid-state memory 128 and the LBA for the modified data is remapped from a previous physical location to the new physical location.

In operation, host interface 126 receives read and write commands from a host or from RAID controller 101 via host interface 126 for reading data from and writing data to NVMs such as disk pack 150 and solid-state memory 128. In response to a write command, DSD controller 120 may buffer the data to be written for the write command in a buffer such as comparison buffer 20 of volatile memory 140.

For data to be written to disk pack 150, a read/write channel (not shown) of DSD controller 120 may then encode the buffered data into write signal 32 which is provided to a head of HSA 136 for magnetically writing data to a disk surface of disk pack 150.

In response to a read command for data stored on a disk surface of disk pack 150, DSD controller 120 controls a head of HSA 136 to magnetically read data stored on the surface of disk pack 150 and to send the read data as read signal 32. A read/write channel of DSD controller 120 can then decode and buffer the data into volatile memory 140 for transmission to a host or RAID controller 101 via host interface 126.

For data to be stored in solid-state memory 128, DSD controller 120 receives data from host interface 126 and may buffer the data in a buffer of volatile memory 140, such as comparison buffer 20. In one implementation, the data is then encoded into charge values for charging cells 129 of solid-state memory 128 to store the data.

In response to a read command for data stored in solid-state memory 128, DSD controller 120 in one implementation reads current values for cells 129 in solid-state memory 128 and decodes the current values into data that can be transferred or copied to a host or RAID controller 101. Such data may be buffered by DSD controller 120 before transferring or copying the data to a host or RAID controller 101 via host interface 126.

Data Pattern Identification Examples

FIG. 3A provides an example of the identification of a data pattern and a corresponding modification of translation table 22 to indicate that particular data is associated with the data pattern according to an embodiment. As shown in FIG. 3A, translation table 22 includes entries with a starting LBA, a length, and a starting Physical Block Address (PBA). The LBAs provide a logical address that may be used by a host or RAID controller 101 in identifying data, and the PBAs indicate a physical location in DSD 106 where the data for a particular LBA is stored. In other embodiments, translation table 22 may instead include ranges of LBAs and/or PBAs rather than providing a length with starting LBAs and starting PBAs.

In the example of FIG. 3A, DSD controller 120 receives one or more write commands to store data associated with LBAs 10 and 20. The data associated with LBA 10 has an A data pattern and the data associated with LBA 20 differs from data pattern A, denoted as data B for LBA 20.

In receiving the one or more write commands, DSD controller 120 stores the data for each of LBAs 10 and 20 in comparison buffer 20 of volatile memory 140 for comparison with one or more data patterns stored in data pattern buffer 18 before writing any of the data to an NVM such as disk pack 150 or solid-state memory 128. The data pattern can include an all zero pattern that may result from a RAID rebuild process or from a full format process of an operating system as described above. In other embodiments, the data pattern can differ, such as a data pattern of all ones, a consecutive data pattern, or a repeating sequence.

In the example of FIG. 3A, data pattern A matches a data pattern stored in data pattern buffer 18, but data B does not match a data pattern stored in data pattern buffer 18. DSD controller 120 indicates that the particular data for LBA 10 is associated with the data pattern by mapping LBA 10 to a predetermined value of 999 in translation table 22. LBA 20, on the other hand, is mapped to a PBA of 12 where the data for LBA 12 is stored in DSD 106.

In some implementations, the predetermined value can be, for example, a physical address beyond a range of available physical addresses in DSD 106 or provide a pointer to a definition for the data pattern in lookup table 24. In other implementations, the predetermined value can be a physical address for a location where the data pattern is stored in reserved area 154 or other area reserved for storing data patterns. In yet other implementations, the predetermined value can be a flag in translation table 22 that identifies the data pattern for DSD firmware 16. In one embodiment, translation table 22 may itself store the data pattern.

By identifying the data pattern for LBA 10, DSD controller 120 can avoid having to write data that may be invalid or repeatedly write the same data pattern, and thereby conserve storage space in DSD 106. As noted above, this can also reduce an amount of garbage collection needed for DSD 106 and more evenly spread garbage collection among a set of DSDs as in the RAID implementation of FIG. 1.

FIG. 3B provides an example of data patterns stored in a memory according to an embodiment. As shown in FIG. 3C, data patterns A and D are associated with PBAs 999 and 1,000. Depending on the implementation, FIG. 3C can represent any of data pattern buffer 18, lookup table 24, or reserved area 154. When data for an LBA associated with a data pattern (e.g., data pattern A or D) is requested, translation table 22 can direct DSD controller 120 to retrieve the data pattern from data pattern buffer 18, lookup table 24, or reserved area 154 using the PBA for the data pattern (e.g., PBA 999 or 1,000). In other embodiments, the data pattern may instead be included as part of DSD firmware 16.

FIG. 3C is a conceptual diagram providing an example of the identification of the A data pattern for subsequent write commands and the further modification of translation table 22 according to an embodiment. As shown in FIG. 3B, DSD controller 120 receives additional write commands to store data for LBAs 30, 40, and 50. The data for LBA 30 is denoted as C data, and the data for LBAs 40 and 50 has the A data pattern.

As in the example of FIG. 3A, DSD controller 120 indicates in translation table 22 that LBAs 40 and 50 are associated with the A data pattern. DSD controller 120 maps both LBA 40 and LBA 50 to the predetermined value of 999 in translation table by consolidating both LBAs into a single entry in translation table 22. As shown in FIG. 3B, LBA 30 is mapped to PBA 24, and LBA 40 is mapped to PBA 999. In addition, the length of the entry for LBA 40 is extended to 20 to cover LBA 50 since both LBAs map to the predetermined value of 999. In this way, DSD controller 120 is able to consolidate translation table 22 by using less entries.

FIG. 4 is a flowchart for a data pattern identification process that can be performed by DSD controller 120 executing DSD firmware 16 according to an embodiment. In block 402, DSD controller 120 maintains translation table 22 mapping logical addresses (e.g., LBAs) to physical addresses (e.g., PBAs) corresponding to locations where data for the logical addresses is stored in DSD 106. DSD controller 120 can maintain translation table 22 by updating translation table 22 to include new physical addresses for remapped logical addresses and adding new entries for newly written LBAs.

In block 404, DSD controller 120 identifies a data pattern of particular data to be stored in or already stored in a memory of DSD 106 such as disk pack 150 or solid-state memory 128. The identification of a data pattern for data already stored in the memory of DSD 106 can be associated with the performance of a maintenance operation of DSD 106 where data is read from the memory. Such an identification process is further described with reference to FIG. 6 below.

In block 406, DSD controller 120 indicates in translation table 22 that the particular data is associated with the data pattern. The indication in translation table 22 can include mapping one or more LBAs for the particular data to a predetermined value, as in the examples of FIGS. 3A and 3C.

FIG. 5 is a flowchart for a data pattern identification process that can be performed by DSD controller 120 executing DSD firmware 16 according to an embodiment. The data identification process of FIG. 5 involves identifying a data pattern for particular data to be stored in DSD 106.

In block 502, DSD controller 120 maintains translation table 22 mapping logical addresses (e.g., LBAs) to physical addresses (e.g., PBAs) corresponding to locations where data for the logical addresses is stored in DSD 106. DSD controller 120 can maintain translation table 22 by updating translation table 22 to include new physical addresses for remapped logical addresses and adding new entries for newly written LBAs.

In block 504, DSD controller 120 receives a write command via host interface 126 to store write data including particular data with a data pattern. In block 506, DSD controller 120 identifies the data pattern of the particular data in the write data. This can be accomplished using data pattern buffer 18 and comparison buffer 20 as described above. In other embodiments, host interface 126 may identify the data pattern without involving DSD controller 120.

In block 508, DSD controller 120 indicates in translation table 22 that at least one logical address for the particular data is associated with the data pattern. The indication can include, for example, generating an entry in translation table 22 for the logical address of the particular data that is mapped to a predetermined value. In the example of FIG. 3A discussed above, DSD controller 120 indicates that the particular data for LBA 10 is associated with the data pattern by generating an entry for LBA 10 that is associated with the predetermined value of 999 for data pattern A.

In other examples, DSD controller 120 may indicate in translation table 22 that at least one logical address for the particular data is associated with the data pattern by modifying an existing entry in translation table 22. With reference to the example of FIG. 3B discussed above, DSD controller 120 may indicate that the particular data for an LBA 60 is associated with data pattern A by modifying the entry for LBA 40 to increase its length to 30 to cover LBA 60. LBAs 40 to 60 would then map to the predetermined value of 999 to indicate data pattern A.

In block 510, DSD controller 120 writes the write data in disk pack 150 or solid-state memory 128 without writing the particular data associated with the data pattern. In this regard, DSD controller 120 may not write the particular data if it is associated with a data pattern (e.g., all zeros) or if the data pattern is already stored in reserved area 154, lookup table 24, or other memory location, or encoded into DSD firmware 16 or controller hardware. In block 512, DSD controller 120 optionally controls HSA 136 to write the particular data in reserved area 154 if the particular data has not been previously written in reserved area 154.

By not having to write the particular data or by only having to write the particular data once, it is ordinarily possible to conserve storage space in DSD 106 and to improve a performance of DSD 106.

FIG. 6 is a flowchart for a data pattern identification process for data previously stored in DSD 106 according to an embodiment. The process of FIG. 6 can be performed by DSD controller 120 executing DSD firmware 16.

In block 602, DSD controller 120 maintains translation table 22 as described above for block 502 of FIG. 5. In block 604, DSD controller 120 performs a maintenance operation on a memory of DSD 106 such as disk pack 150 or solid-state memory 128. The maintenance operation can include, for example, a garbage collection operation for reclaiming portions of disk pack 150 or solid-state memory 128 that store obsolete data. In performing the maintenance operation, data stored in the memory is read and can be compared to one or more data patterns.

In some embodiments, DSD controller 120 may learn a new data pattern by comparing data stored in DSD 106 with other data stored in DSD 106. For example, DSD 106 may recognize a new data pattern when performing the maintenance operation. If so, DSD controller 120 may rewrite or keep only one instance of the data pattern and modify translation table 22 to map multiple logical addresses to the one copy of the data pattern.

In block 606, DSD controller 120 identifies the data pattern of the particular data previously stored in the memory as a result of performing the maintenance operation. In block 608, at least one logical address for the particular data is associated with the data pattern in translation table 22. This association may include modifying an existing entry for one or more logical addresses for the particular data to map them to a predetermined value indicating the data pattern. As with the example embodiment of FIG. 5 discussed above, the predetermined value may serve as a pointer to a definition for the data pattern in lookup table 24 or may provide a physical address for a location storing the data pattern.

In block 610, DSD controller 120 modifies translation table 22 to indicate that at least one physical address for the particular data is available for storing different data. Since the at least one logical address for the particular data now maps to the predetermined value, the old physical address or addresses where the particular data was stored becomes available for storing other data. This can ordinarily allow for conserving storage space in DSD 106 since multiple instances of different logical addresses for the data pattern can be physically stored in one location rather than multiple locations.

Other Embodiments

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks, modules, and processes described in connection with the examples disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. Furthermore, the foregoing processes can be embodied on a computer readable medium which causes a processor or computer to perform or execute certain functions.

To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, and modules have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those of ordinary skill in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, units, modules, and controllers described in connection with the examples disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The activities of a method or process described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The steps of the method or algorithm may also be performed in an alternate order from those provided in the examples. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable media, an optical media, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC).

The foregoing description of the disclosed example embodiments is provided to enable any person of ordinary skill in the art to make or use the embodiments in the present disclosure. Various modifications to these examples will be readily apparent to those of ordinary skill in the art, and the principles disclosed herein may be applied to other examples without departing from the spirit or scope of the present disclosure. The described embodiments are to be considered in all respects only as illustrative and not restrictive and the scope of the disclosure is, therefore, indicated by the following claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.