Write-through media caching

Description

BACKGROUND

Data Storage Devices (DSDs) are often used to record data on or to reproduce data from a recording media. As one type of DSD, a disk drive can include a rotating magnetic disk and a head actuated over the disk to magnetically write data to and read data from the disk. Such disks include a plurality of radially spaced, concentric tracks for recording data.

Shingled Magnetic Recording (SMR) has been introduced as a way of increasing the amount of data that can be stored in a given area on a disk by increasing the number of Tracks Per Inch (TPI). SMR increases TPI by using a relatively wide shingle write head to overlap tracks like roof shingles. The non-overlapping portion then serves as a narrow track that can be read by a narrower read head.

Although a higher number of TPI is ordinarily possible with SMR, the higher track density can create additional problems. For example, the closer spacing of tracks in an SMR region can worsen Adjacent Track Interference (ATI) where the writing of data on an adjacent track negatively affects the data written on a target track.

Another problem encountered with SMR involves Wide Area Track Erasure (WATER). WATER results in data being erased from adjacent tracks near a track being written due to interference from the magnetic field of the write head. DSDs using SMR are ordinarily more susceptible to WATER than conventional disk drives due to the combination of narrower tracks and a wider shingle write head having a stronger magnetic field. In addition, the closer spacing of tracks can also make writing data more susceptible to errors when writing due to vibration or mechanical shock.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the embodiments of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. The drawings and the associated descriptions are provided to illustrate embodiments of the disclosure and not to limit the scope of what is claimed.

FIG. 1 is a block diagram depicting a Data Storage Device (DSD) according to an embodiment.

FIG. 2A is a conceptual diagram illustrating a track with a lower servo bandwidth and a lower margin of allowable deviation according to an embodiment.

FIG. 2B is a conceptual diagram illustrating a track with a higher servo bandwidth and a greater margin of allowable deviation according to an embodiment.

FIG. 3 is a flowchart for a write through media caching process according to an embodiment.

FIG. 4 is a flowchart for a determining when to activate a write through media caching process according to an embodiment.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth to provide a full understanding of the present disclosure. It will be apparent, however, to one of ordinary skill in the art that the various embodiments disclosed may be practiced without some of these specific details. In other instances, well-known structures and techniques have not been shown in detail to avoid unnecessarily obscuring the various embodiments.

System Overview

FIG. 1 shows system 100 according to an embodiment that includes host 101 and Data Storage Device (DSD) 106. System 100 can be, for example, a computer system (e.g., server, desktop, mobile/laptop, tablet, smartphone, etc.) or other electronic device such as a digital video recorder (DVR). In this regard, system 100 may be a stand-alone system or part of a network. Those of ordinary skill in the art will appreciate that system 100 and DSD 106 can include more or less than those elements shown in FIG. 1 and that the disclosed processes can be implemented in other environments.

In the example embodiment of FIG. 1, DSD 106 includes both solid-state memory 128 and disk 150 for storing data. In this regard, DSD 106 can be considered a Solid-State Hybrid Drive (SSHD) in that it includes both solid-state Non-Volatile Memory (NVM) media and disk NVM media. In other embodiments, each of disk 150 or solid-state memory 128 may be replaced by multiple Hard Disk Drives (HDDs) or multiple Solid-State Drives (SSDs), respectively, so that DSD 106 includes pools of HDDs or SSDs. In yet other embodiments, DSD 106 may include disk 150 without solid-state memory 128.

DSD 106 includes controller 120 which comprises circuitry such as one or more processors for executing instructions and can include a microcontroller, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), hard-wired logic, analog circuitry and/or a combination thereof. In one implementation, controller 120 can include a System on a Chip (SoC).

Host interface 126 is configured to interface DSD 106 with host 101 and may interface according to a standard such as, for example, PCI express (PCIe), Serial Advanced Technology Attachment (SATA), or Serial Attached SCSI (SAS). As will be appreciated by those of ordinary skill in the art, host interface 126 can be included as part of controller 120.

In the example of FIG. 1, disk 150 is rotated by a spindle motor (not shown). DSD 106 also includes head 136 connected to the distal end of actuator 130, which is rotated by Voice Coil Motor (VCM) 132 to position head 136 in relation to disk 150. Controller 120 can control the position of head 136 and the rotation of disk 150 using VCM control signal 30 and SM control signal 34, respectively. In this regard, controller 120 includes servo controller circuitry for controlling the position of head 136 and the rotation of disk 150.

As appreciated by those of ordinary skill in the art, disk 150 may form part of a disk pack with additional disks radially aligned below disk 150. In addition, head 136 may form part of a head stack assembly including additional heads with each head arranged to read data from and write data to a corresponding surface of a disk in a disk pack.

Disk 150 includes a number of radial spaced, concentric tracks (not shown) for storing data on a surface of disk 150. The tracks on disk 150 may be grouped together into zones of tracks with each track divided into a number of sectors that are spaced circumferentially along the tracks.

As shown in the example of FIG. 1, disk 150 includes first region 152 with a first track density and second region 154 with a second track density greater than the first track density. The first track density in first region 152 is less than the second track density in that the centers of tracks in second region 154 are closer together and can store more data in a given area of disk 150. In some implementations, second region 154 may be written using Shingled Magnetic Recording (SMR) such that the tracks in second region 154 overlap, while first region 152 can be written using Conventional Magnetic Recording (CMR) such that the tracks in first region 152 do not overlap. In other implementations, the tracks in both first region 152 and second region 154 may be written using SMR or CMR, but with a higher track density in second region 154.

The example embodiment of FIG. 1 depicts first region 152 in a Middle Diameter (MD) portion of disk 150. In this regard, first region 152 with a lower track density may be located in an MD portion since locating a higher track density region in other portions of disk 150, such as an Outer Diameter (OD) or Inner Diameter (ID) portion, can result in an increased data capacity than locating the higher track density region in an MD portion. In other embodiments, first region 152 and second region 154 may be located in other portions of disk 150 or may have different relative areas on disk 150.

First region 152 or second region 154 may be contiguous regions or may be non-contiguous regions as in the example of FIG. 1, where second region 154 is located on both sides of first region 152. In addition, disk 150 is shown in FIG. 1 as having two regions with different track densities, however, other embodiments may include a different number of regions with different track densities.

In addition to disk 150, the NVM media of DSD 106 also includes solid-state memory 128 for storing data. While the description herein refers to solid-state memory generally, it is understood that solid-state memory may comprise one or more of various types of memory devices such as flash integrated circuits, Chalcogenide RAM (C-RAM), Phase Change Memory (PC-RAM or PRAM), Programmable Metallization Cell RAM (PMC-RAM or PMCm), Ovonic Unified Memory (OUM), Resistance RAM (RRAM), NAND memory (e.g., Single-Level Cell (SLC) memory, Multi-Level Cell (MLC) memory, or any combination thereof), NOR memory, EEPROM, Ferroelectric Memory (FeRAM), Magnetoresistive RAM (MRAM), other discrete NVM chips, or any combination thereof.

In FIG. 1, volatile memory 140 can include, for example, a Dynamic Random Access Memory (DRAM), which can be used by DSD 106 to temporarily store data. Data stored in volatile memory 140 can include data read from NVM media (e.g., disk 150 or solid-state memory 128) or data to be written to NVM media. As shown in FIG. 1, volatile memory 140 includes write buffer 12 for temporarily storing data to be written to disk 150. In other embodiments, write buffer 12 may be stored in other locations such as in solid-state memory 128.

Volatile memory 140 can also store instructions loaded from firmware 16 for execution by controller 120 or data used in executing firmware 16. In this regard, volatile memory 140 in FIG. 1 is shown as temporarily storing firmware 16 which can include instructions for execution by controller 120 to implement the write through caching processes discussed below. Firmware 16 may be stored in one of the non-volatile storage media shown in FIG. 1 such as solid-state memory 128 and/or rotating magnetic media including disk 150.

In operation, host interface 126 receives read and write commands from host 101 via host interface 126 for reading data from and writing data to the NVM media of DSD 106. In response to a write command from host 101, controller 120 may buffer the data to be written for the write command in volatile memory 140.

For data to be stored in solid-state memory 128, controller 120 receives data from host interface 126 and may buffer the data in a write buffer of volatile memory 140. In one implementation, the data is then encoded into charge values for charging cells (not shown) of solid-state memory 128 to store the data.

In response to a read command for data stored in solid-state memory 128, controller 120 in one implementation reads current values for cells in solid-state memory 128 and decodes the current values into data that can be transferred to host 101. Such data may be buffered by controller 120 in a read buffer of volatile memory 140 before transferring the data to host 101 via host interface 126.

In response to a read command for data stored on disk 150, controller 120 positions head 136 via VCM control signal 30 to magnetically read the data stored on the surface of disk 150. Head 136 sends the read data as read signal 32 to controller 120 for decoding, and the data can be buffered in a read buffer of volatile memory 140 for transferring to host 101.

For data to be written to disk 150, controller 120 can encode data buffered in write buffer 12 into write signal 32 which is provided to head 136 for magnetically writing data to the surface of disk 150. As discussed in more detail below, the write through caching of the present disclosure can include writing the data for the write command in first region 152 and then writing the data for the write command in second region 154 without reading the data for the write command from first region 152. In this regard, first region 152 with its lower track density is used as a write through media cache on disk 150.

Since second region 154 has a higher track density, it is more susceptible than first region 152 to errors caused by vibration, shock, Adjacent Track Interference (ATI), Wide Area Track Erasure (WATER), or adjacent track encroachment issues due to the close proximity of tracks. By writing data in a more protected first region 152 before writing the data in a less protected second region 154, data can ordinarily be safely stored on disk 150 while still allowing for the data capacity savings of second region 154 with its higher track density.

In addition, the disk media caching discussed below is “write through” in that writing data to second region 154 is not deferred. In more detail, data can be written directly from write buffer 12 to second region 154 without having to read the data from first region 152. In contrast to other disk caching where writing data a second time on the disk is deferred, the write through caching of the present disclosure can reduce the overall amount of disk operations since data does not need to be read from first region 152 (i.e., the disk media cache) to write the data in second region 154 from write buffer 12. This can ordinarily allow for a lower overall power consumption and lower wear on head 136 since a read operation does not need to be performed in first region 152 to write the data in second region 154. An overall performance time for storing data in both first region 152 and second region 154 is also usually less since accessing data from write buffer 12 is generally quicker than reading data from first region 152.

The write through caching discussed below also allows for a more steady and predictable performance cost in terms of performing garbage collection and defragmentation in first region 152. Since data is written in second region 154 without being deferred, the first copy of the data in first region 152 can typically be overwritten sooner because a copy of the data is ordinarily available sooner in second region 154. In write caching where writing the second time to the disk is deferred, defragmentation and garbage collection may also end up being deferred until the amount of invalid data or fragmentation in the disk media cache reaches a critical level. At that point, other commands may be delayed for a longer period of time in order to perform garbage collection or defragmentation, which may also occur at an inconvenient time with respect to the performance of DSD 106.

Track Examples for First Region and Second Region

FIGS. 2A and 2B illustrate example tracks from each of first region 152 and second region 154, respectively, to compare differences between the regions. In FIG. 2A, track 202 of first region 152 includes servo wedges spaced every four sectors as indicated by the servo wedge sectors with “SW” and user data sectors indicated with a “D.” Each servo wedge may include servo information that can be read from disk 150 by head 136 to determine the position of head 136 over disk 150. For example, each servo wedge may include a pattern of alternating magnetic transitions (servo burst), which may indicate a particular wedge number on disk 150.

The spacing of the servo wedges in track 202 may be slightly different than for other tracks in first region 152 due to differences in the radial location of the tracks. Although the physical spacing of the servo wedges may vary slightly among tracks within first region 152, the frequency at which the servo wedges are read by head 136 during an operation of head 136 (e.g., reading or writing data in first region 152), is approximately the same throughout first region 152 to provide a substantially uniform servo bandwidth in first region 152. As used herein, a servo bandwidth refers to the frequency at which servo wedges are read by head 136 during an operation of head 136.

FIG. 2A also depicts write unsafe limit 204 and predicted write unsafe limit 206 with dashed lines. Write unsafe limit 204 provides a margin of an allowable deviation from the center of track 202 when writing data. If head 136 travels outside of write unsafe limit 204 while writing data, head 136 will stop writing data and treat the write as a write error. Such deviation from track 202 may occur, for example, during a vibration condition of DSD 106 (e.g., speakers of system 100 creating a significant amount of vibration) or during a mechanical shock event of DSD 106 (e.g., when system 100 is bumped). To reduce future write errors, DSD 106 may also use predicted write unsafe limit 206 to trigger a corrective action to reposition head 136 closer to the center of track 202.

In comparison to track 202 of FIG. 2A, track 208 depicted in FIG. 2B is a wider track, has a higher servo bandwidth, and a larger margin of allowable deviation from the center of track 208. As shown in FIG. 2B, servo wedges are spaced at every other sector in track 208 rather than at every fourth sector. The closer spacing of servo wedges provide a higher servo bandwidth in first region 152 so that servo wedges are read more frequently by head 136 when performing an operation in first region 152 than in second region 154. The higher servo bandwidth of first region 152 ordinarily allows for better control of head 136 since position information is available more frequently.

As will be appreciated by those of ordinary skill in the art, the foregoing examples of servo wedge spacing in tracks 202 and 208 are used to illustrate a difference in servo bandwidth. Actual servo wedge spacing may differ from those shown in FIGS. 2A and 2B.

In addition, track 208 includes a wider or larger margin of allowable deviation from the center of track 208 when compared to track 202 of FIG. 1. This is illustrated in FIG. 2B with write unsafe limit 210 and predicted write unsafe limit 212 being spaced farther from the center of track 208 when compared to the limits shown in FIG. 2A for track 202. Track 208 can have a larger margin of allowable deviation due to the lower track density in first region 152, which can result from one or both of having wider tracks and a wider spacing between tracks.

As a result of one or both of the higher servo bandwidth and the larger margin of allowable deviation in first region 152, head 136 can ordinarily write without errors during vibration or shock conditions that would otherwise cause errors in the higher track density region of second region 154.

Example Write Through Caching Process

FIG. 3 is a flowchart for a write caching process that can be performed by controller 120 executing firmware 16 according to an embodiment. In block 302, controller 120 receives a write command from host 101 via host interface 126. The write command can include data to be stored in DSD 106 and may or may not specify a location in DSD 106 for storing the data.

In block 304, controller 120 temporarily stores the data for the write command in write buffer 12 of volatile memory 140. In block 306, controller 120 controls head 136 to write the data for the write command from write buffer 12 to first region 152 with a first track density that is less than a second track density of second region 154.

In block 308, controller 120 determines whether there was an error in writing the data in first region 152. This may occur, for example, if head 136 travels outside of write unsafe limit 210. In some implementations, controller 120 may perform a write verify operation in block 308 to read the data written in first region 152 and verify that the data can be accessed from first region 152.

If there was an error in writing the data in first region 152, controller 120 rewrites the data from the command in first region 152 by returning to block 306. The servo bandwidth and/or the margin of allowable deviation in first region 152 can be set so that write errors occur less frequently in first region 152 than in second region 154 for a given vibration or shock condition of DSD 106. Accordingly, errors in first region 152 are ordinarily expected less than in second region 154 and first region 152 can be used as a safer or more protected portion of disk 150 for performing the initial writing or caching of data on disk 150.

In this regard, a data capacity size of first region 152 can be based on a predetermined amount of time for writing data in first region 152 when writing the data would not be possible in second region 154 due to an environmental condition such as vibration or shock. For example, first region 152 may be sized so that it can store a certain amount of data that corresponds to a predetermined time that second region 154 is unavailable. In such a case, data could continue to be written in first region 152 until it becomes full, thereby providing time for the environmental condition to end.

In other implementations, first region 152 may be sized based on the size of write buffer 12. In one such implementation, a data capacity size of first region 152 is approximately equal to a data capacity size of write buffer 12. This can ordinarily allow for substantially all of the data stored in write buffer 12 to be written to first region 152 while limiting the storage capacity cost of first region 152 to the overall storage capacity of disk 150. In other words, since first region 152 has a lower track density than second region 154, disk 150 can accommodate more data by limiting the size of first region 152 to a smaller area on disk 150. By sizing first region 152 to approximately the same size as write buffer 12, first region 152 does not have to be overwritten to store all of the data from write buffer 12 without consuming extra space on disk 150.

Returning to FIG. 3, if no error occurs in writing the data in first region 152, controller 120 in block 310 controls head 136 to write the data from write buffer 12 in second region 154. As discussed above, such write through caching where data is directly provided from write buffer 12 typically avoids having to read the data from first region 152 as in a deferred caching process. As a result, a lifetime expectancy of head 136 is typically longer, an overall power consumption of DSD 106 is typically less, and an overall performance time for writing data in both regions is typically less. In addition, and as discussed above, maintenance operations in first region 152 are generally more predictable by not deferring the second write to disk 150.

In block 312, controller 120 determines whether there was an error in writing the data in second region 154. This may occur, for example, if head 136 travels outside of write unsafe limit 204 in FIG. 2A. In some implementations, controller 120 may perform a write verify operation in block 312 to read the data written in second region 154 and verify that the data can be accessed from second region 154.

If it is determined that there was an error in writing data in second region 154, controller 120 returns to block 310 to rewrite the data in second region 154. On the other hand, if there was no error in block 312, the process of FIG. 3 ends in block 314.

Selectively Applying the Write Through Caching Process

In one embodiment, the write through caching is selectively applied to an incoming data workload. One selection factor involves steering sequential writes to the write through caching mode. In one embodiment, the detection of sequential writes involves detecting when a certain number of sequential data blocks (e.g., 64) is encountered. This may be part of an automation handling in the data storage device. In one example, when this occurs, automation is used to handle the write commands to speed up operation, and as part of the automation trigger, the write through caching mode can be activated.

An aggregator may be used in the detection. In one embodiment, there are other conditions indicative of random writes (e.g., host not sending data in several revolutions of the disk, not enough sequential count, etc.) that the aggregator looks for in making the determination. So, for example, if the host provides a small sequential sequence of write commands and invalidates it, write through would not be enabled. The aggregator may be run-time configurable. This may be helpful in improving write-all applications, video stream writing applications, drive duplicator applications, back-up applications, or any applications in which large sequential writes may be involved.

FIG. 4 is a flowchart for selectively determining the activation of a write through caching process that can be performed by controller 120 executing firmware 16 according to an embodiment. In block 402, write commands are received. In block 404, a detection process (e.g., an aggregator with configurable options) can be applied to monitor the incoming stream of write commands to detect sequential writes, as discussed above. If detected at block 406, write through caching mode is triggered at block 408. Otherwise, at block 410, the controller continues to process write commands in a non-write through caching mode. This means that the controller may write data to a first region, and later read the same data from the first region and write the read data to a second region with a higher track density.

Other Embodiments

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks, modules, and processes described in connection with the examples disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. Furthermore, the foregoing processes can be embodied on a computer readable medium which causes a processor or computer to perform or execute certain functions.

To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, and modules have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those of ordinary skill in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, units, modules, and controllers described in connection with the examples disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The activities of a method or process described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The steps of the method or algorithm may also be performed in an alternate order from those provided in the examples. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable media, an optical media, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC).

The foregoing description of the disclosed example embodiments is provided to enable any person of ordinary skill in the art to make or use the embodiments in the present disclosure. Various modifications to these examples will be readily apparent to those of ordinary skill in the art, and the principles disclosed herein may be applied to other examples without departing from the spirit or scope of the present disclosure. The described embodiments are to be considered in all respects only as illustrative and not restrictive and the scope of the disclosure is, therefore, indicated by the following claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.