Power loss mitigation for data storage device

Description

BACKGROUND

Data Storage Devices (DSDs) are often used to record data onto or to reproduce data from a storage media. One type of storage media includes a rotating magnetic disk where a magnetic head of the DSD can read and write data in tracks on a surface of the disk, such as in a Hard Disk Drive (HDD). Another type of storage media can include a solid-state memory where cells are charged to store data.

In writing data to a disk, an unexpected power loss can cause an incomplete write of data to a sector in a track. Data in the sector is then typically not readable after the incomplete write and the data is usually lost after the unexpected power loss.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the embodiments of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. The drawings and the associated descriptions are provided to illustrate embodiments of the disclosure and not to limit the scope of what is claimed.

FIG. 1 is a block diagram depicting a Data Storage Device (DSD) according to an embodiment.

FIG. 2 is a diagram depicting a track on a disk according to an embodiment.

FIG. 3A is a diagram depicting a portion of an unqualified sector range according to an embodiment.

FIG. 3B is a diagram depicting a write abort in a portion of an unqualified sector range according to an embodiment.

FIG. 3C is a diagram depicting a write retry of the portion of the unqualified sector range of FIG. 3B according to an embodiment.

FIG. 4 is a flowchart for a disk write process according to an embodiment.

FIG. 5 is a flowchart for a power loss process according to an embodiment.

FIG. 6 is a flowchart for a power-up process according to an embodiment.

FIG. 7A illustrates an example of a physical sector written in a 512e format according to an embodiment.

FIG. 7B illustrates an example of a physical sector including new data and runt data according to an embodiment.

FIG. 7C illustrates an example of an interruption while writing the physical sector of FIG. 7B according to an embodiment.

FIG. 8 is a flow chart for a write process for writing new data and runt data in a physical sector according to an embodiment.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth to provide a full understanding of the present disclosure. It will be apparent, however, to one of ordinary skill in the art that the various embodiments disclosed may be practiced without some of these specific details. In other instances, well-known structures and techniques have not been shown in detail to avoid unnecessarily obscuring the various embodiments.

System Overview

FIG. 1 depicts a block diagram of Data Storage Device (DSD) 106 according to an embodiment where DSD 106 includes Non-Volatile Memory (NVM) in the form of rotating magnetic disk 200 and Non-Volatile Solid-State Memory (NVSM) 128. In this regard, DSD 106 can be considered a Solid-State Hybrid Drive (SSHD) since it includes both solid-state and disk media. In other embodiments, each of disk 200 or NVSM 128 may be replaced by multiple Hard Disk Drives (HDDs) or multiple Solid-State Drives (SSDs), respectively, so that DSD 106 includes pools of HDDs and/or SSDs. Other embodiments may include different components than those shown in FIG. 1.

DSD 106 includes controller 120 which includes circuitry such as one or more processors for executing instructions and can include a microcontroller, a DSP, an Application-Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), hard-wired logic, analog circuitry and/or a combination thereof. In one implementation, controller 120 can include a System on a Chip (SoC).

Host interface 126 is configured to interface DSD 106 with host 101 and may interface according to a standard such as, for example, Serial Advanced Technology Attachment (SATA), PCI express (PCIe), Small Computer System Interface (SCSI), or Serial Attached SCSI (SAS). As will be appreciated by those of ordinary skill in the art, host interface 126 can be included as part of controller 120. Although FIG. 1 depicts the co-location of host 101 and DSD 106, in other embodiments the two need not be physically co-located. In such embodiments, DSD 106 may be located remotely from host 101 and connected to host 101 via a network interface.

In the example of FIG. 1, disk 200 is rotated by a Spindle Motor (SM) 154 and head 136 is positioned to read and write data on the surface of disk 200. In more detail, head 136 is connected to the distal end of actuator 130 which is rotated by Voice Coil Motor (VCM) 132 to position head 136 over disk 200 to read or write data in tracks 202.

As shown in FIG. 1, disk 200 includes a number of radially spaced, concentric tracks 202 for storing data. In some implementations, tracks 202 may be written using Shingled Magnetic Recording (SMR) such that tracks 202 overlap. In other implementations, tracks 202 may not overlap or disk 200 may include both overlapping and non-overlapping tracks 202. Disk 200 also includes servo wedges 204₀ to 204_N that are used to control the position of head 136 in relation to disk 200.

Servo system 121 controls the rotation of disk 200 with SM control signal 31 and controls the position of head 136 with VCM control signal 30. In more detail, FIG. 2 illustrates an example of a track 202 on disk 200 that includes servo wedges 204 spaced every four sectors as indicated by the servo wedge sectors with “SW” and user data sectors indicated with a “D.” Each servo wedge 204 may include servo information that can be read from disk 200 by head 136 to determine the position of head 136 over disk 200. For example, each servo wedge may include a pattern of alternating magnetic transitions (a servo burst), which may indicate a particular wedge number on disk 200.

FIG. 2 also depicts write unsafe thresholds 208 with dashed lines that are a threshold distance from the center of track 202. In other embodiments, write unsafe thresholds in addition to write unsafe thresholds 208 can be used to provide different margins of deviation from the center of track 202 when writing data.

In the example of FIG. 2, if head 136 travels outside of write unsafe thresholds 208 while writing data, head 136 will stop or abort writing data and treat the write as a write error. Such deviation from track 202 may occur, for example, during a vibration condition of DSD 106 or during a mechanical shock event of DSD 106.

Returning to FIG. 1, DSD 106 also includes NVSM 128 for storing data across power cycles. While the description herein refers to solid-state memory generally, it is understood that solid-state memory may comprise one or more of various types of memory devices such as flash integrated circuits, Chalcogenide RAM (C-RAM), Phase Change Memory (PC-RAM or PRAM), Programmable Metallization Cell RAM (PMC-RAM or PMCm), Ovonic Unified Memory (OUM), Resistance RAM (RRAM), NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory, or any combination thereof), NOR memory, EEPROM, Ferroelectric Memory (FeRAM), Magnetoresistive RAM (MRAM), other discrete NVM (non-volatile memory) chips, or any combination thereof. In FIG. 1, NVSM 128 includes first segment 142 and second segment 144, which can be used to store different instances of unqualified data from volatile memory 140, as discussed in more detail below with reference to the processes of FIGS. 5 and 6.

DSD 106 includes volatile memory 140, which can include, for example, a Dynamic Random Access Memory (DRAM). Volatile memory 140 can be used by DSD 106 to temporarily store data. Data stored in volatile memory 140 can include data read from NVM such as disk 200 or NVSM 128, data to be stored in NVM, instructions loaded from DSD firmware 10 for execution by controller 120, and/or data used in executing DSD firmware 10. Volatile memory 140 can also be used to temporarily store data for write commands intended for disk 200 in write buffer 16.

As discussed in more detail below, certain data stored in volatile memory 140 may have been in the process of being written on disk 200 at the time of an unexpected power loss and could be at risk of causing a write splice (i.e., a corrupted data sector on the disk) after the unexpected power loss. In addition, this unqualified data is also at risk of being lost after an unexpected power loss. The present disclosure therefore includes transferring to NVSM 128 a portion of unqualified data that has not been qualified as written on disk 200 in the event of an unexpected power loss. In some implementations, servo system 121 can be used to qualify data written on disk 200 by providing an indication of whether the data was written within a threshold distance from a center of a track 202 on disk 200 (e.g., within write unsafe thresholds 208 in FIG. 2).

In one implementation, data for performing host write commands is stored in write buffer 16 and a portion of the unqualified data from write buffer 16 is identified or marked through the use of a flag or other indicator as being unqualified data that is at risk of causing a write splice (i.e., a corrupted sector). Such unqualified data can include data that has not been qualified as written between a current servo wedge 204 and a next servo wedge 204. Location information 18 stored in volatile memory 140 can include a current servo wedge number indicating the last servo wedge 204 read by head 136. Controller 120 can then indicate that the unqualified data following the current servo wedge to a next servo wedge is at risk of causing a write splice. In other implementations, the unqualified data at risk can include unqualified data from the current servo wedge up to a different number of following servo wedges such as unqualified data up to the next two servo wedges. In addition, controller 120 maintains qualified sector count 14 to indicate which data stored in write buffer 16 is qualified data. In more detail, qualified sector count 14 can provide a count of sectors written on disk 200 that have been qualified as written.

Controller 120 can then transfer the unqualified data at risk of causing a write splice to NVSM 128 after an unexpected power loss so that the unqualified data can be correctly written after powering up. In one implementation, kinetic energy from the rotation of SM 154 can be used to temporarily power NVSM 128 to facilitate the transfer of unqualified data from volatile memory 140 to NVSM 128. The transfer of data to NVSM 128 ordinarily reduces later uncorrectable read errors caused by write splices formed by writing during an unexpected power loss. In addition, the unqualified data transferred to NVSM 128 is ordinarily protected from being lost after the power loss.

In normal operation, host interface 126 receives host read and write commands from host 101 for reading data from and writing data to NVM. In response to a write command from host 101, controller 120 may buffer the data to be written for the write commands in write buffer 16.

For data to be written on disk 200, a read/write channel (not shown) of controller 120 may encode the buffered data into write signal 32 which is provided to head 136 for magnetically writing data on disk 200. Servo system 121 can provide VCM control signal 30 to VCM 132 to position head 136 over a particular track 202 for writing the data. Servo wedges 204 may be read from disk 200 to provide servo system 121 with feedback for positioning head 136 in relation to disk 200.

In response to a read command for data stored on disk 200, servo system 121 positions head 136 over a particular track 202. Controller 120 controls head 136 to magnetically read data stored in the track and to send the read data as read signal 32. A read/write channel of controller 120 can then decode and buffer the data into volatile memory 140 for transmission to host 101 via host interface 126. In addition, servo wedges 204 can be read from disk 200 to provide feedback to servo system 121 for positioning head 136 in relation to disk 200.

For data to be stored in NVSM 128, controller 120 receives data from host interface 126 and may buffer the data in volatile memory 140. In one implementation, the data is then encoded into charge values for charging cells (not shown) of NVSM 128 to store the data.

In response to a read command for data stored in NVSM 128, controller 120 in one implementation reads current values for cells in NVSM 128 and decodes the current values into data that can be transferred to host 101 via host interface 126.

Write Splice Mitigation Examples

FIG. 3A is a diagram depicting an unqualified sector range that is at risk according to an embodiment. In the example of FIG. 3A, sectors 0 to 7 are written to disk 200 under a write gate. While writing the sectors, servo system 121 determines a position of head 136 with respect to track 202 during a servo gate and makes adjustments to VCM control signal 30 to better align head 136 with the center of track 202. As discussed above, this can be accomplished by reading servo wedges 204 during the servo gate and using position information recorded in servo wedges 204 to determine a relative position of head 136. Based on a current position of head 136, servo system 121 qualifies that the sectors following a previous servo wedge 204 were within a data track tolerance (e.g., within write unsafe thresholds 208 in FIG. 2). The qualification of sectors generally lags the writing of sectors by one or more servo wedges 204.

In the example of FIG. 3A, sectors 0 and 1 have been qualified as written on disk 200 and form part of a qualified sector range. Sectors 2 to 7 have been written on disk 200 but have not yet been qualified as written so they form an unqualified sector range at risk that may include a write splice. If the data for a sector has been successfully written within the threshold distance, the sector is qualified and an indication is provided to controller 120 to update qualified sector count 14.

FIG. 3B provides an example where the writing of sector 6 in the unqualified sector range at risk is aborted according to an embodiment. The halting of the write gate could have occurred due to head 136 traveling outside of write unsafe thresholds 208. Sector 6 then contains a write splice since writing data to the sector was interrupted. If a power loss were to occur in a conventional DSD before the data of sector 6 is successfully written on disk 200 during a write retry, the data of sector 6 may cause an uncorrectable read error since the data for this sector remains in an unreadable sector. The present disclosure therefore transfers the unqualified data at risk from volatile memory 140 to NVSM 128 in the event of an unexpected power loss to protect against uncorrectable read errors and data loss that may otherwise occur due to an incomplete write in a sector.

If there is not an unexpected power loss, DSD 106 may attempt a write retry to write the unqualified sector range of sectors 2 to 6. FIG. 3C is an example of a write retry of the unqualified sector range according to an embodiment. In attempting the write retry, head 136 waits until disk 200 returns to the previously attempted location on disk 200 for writing the unqualified sector range. The wait for head 136 to return to the previously attempted location can add to the vulnerability of the data to be written in sector 6 since it prolongs the time in which an unexpected power loss could occur. In addition, certain types of disk defects can cause some DSDs to attempt multiple write retries if the first write retry is unsuccessful.

In the example of FIG. 3C, another write splice occurs when trying to rewrite the unqualified sector range that is at risk. This time, the write is aborted in sector 4, which now also contains a write splice. The data in sectors 4 and 6 are now vulnerable since they have not been properly recorded in NVM yet. DSD 106 may make a predetermined number of write retries (e.g., three write retries) before reporting a write error and writing the unqualified data in another portion of NVM. As discussed in more detail below, the present disclosure provides for power safe protection of the data in the unqualified sector range at risk by transferring this unqualified data from volatile memory 140 to NVSM 128 in the event of an unexpected power loss.

FIG. 4 is a flowchart for a disk write process that can be performed by controller 120 executing DSD firmware 10 according to an embodiment. In block 402 data is stored in volatile memory 140 such as in write buffer 16 in preparation for writing the data on disk 200. In block 404, controller 120 controls head 136 via servo system 121 to write at least a portion of the data stored in volatile memory 140 on disk 200.

In block 406, controller 120 determines whether the data written on disk 200 is qualified as written. As discussed above, controller 120 may determine whether data is qualified as written based on an indication from servo system 121 indicating whether the data was written within a threshold distance from a center of a track on disk 200.

In block 408, controller 120 updates qualified sector count 14 to indicate a number of sectors qualified as written on disk 200 for data stored in write buffer 16. In other embodiments, controller 120 may instead keep track of the number of sectors written on disk 200 that remain unqualified. As discussed below with reference to FIG. 5, the qualified sector count 14 can be used by controller 120 during a power loss to determine which data stored in volatile memory 140 is unqualified.

FIG. 5 is a flowchart for a power loss process that can be performed by controller 120 executing DSD firmware 10 according to an embodiment. In block 502, an unexpected power loss occurs at DSD 106. An indication of a power loss can come from, for example, a notification from host 101, monitoring of a power supply of DSD 106, or an indication from power supply circuitry of DSD 106.

In block 504, controller 120 identifies unqualified data stored in write buffer 16 of volatile memory 140 based on qualified sector count 14. The identification may include, for example, flagging data corresponding to the unqualified sector range.

In block 506, the unqualified data is transferred from volatile memory 140 to first segment 142 or second segment 144 of NVSM 128 together with metadata for the unqualified data. The metadata can indicate, for example, logical addresses for identifying the data and its intended location on disk 200. Other embodiments may not transfer metadata to NVSM 128.

As noted above, kinetic energy from a rotation of spindle motor 154 can power NVSM 128 and/or volatile memory 140 long enough to facilitate the transfer of the unqualified data. In other embodiments, controller 120 may keep a running identification of the unqualified data in volatile memory 140 rather than identifying the unqualified data at the time of power loss.

FIG. 6 is a flowchart for a power-up process that can be performed by controller 120 executing DSD firmware 10 according to an embodiment. In block 602, DSD 106 is powered-up after an unexpected power loss. In block 604, controller 120 retrieves unqualified data that was transferred to NVSM 128 from volatile memory 140 after the power loss. In some implementations, controller 120 controls head 136 to write the retrieved data on disk 200 before performing any commands involving the data so as to maintain coherency of the unqualified data. Controller 120 may also wait until the retrieved data has been qualified as written on disk 200 before performing any commands involving the data.

In block 606, one of segment 142 or 144 of NVSM 128 is erased after the unqualified data retrieved in block 604 has been qualified as written on disk 200. This can ordinarily ensure that there is space available in either first segment 142 or second segment 144 to quickly store unqualified data in the event of another unexpected power loss.

Power Safe Runt Processing Examples

FIG. 7A illustrates an example of a physical sector written in 512e format according to an embodiment. The 512e format can allow for larger physical sectors such as 4,096 byte sectors while accommodating a logical sector size of 512 bytes that is commonly used by most hosts. As shown in FIG. 7A, a physical sector includes eight logical sectors of 512 bytes written during a write gate.

In cases where new data to be written to disk 200 is not large enough to fill a full physical sector, controller 120 can use data from other sectors called runt data to fill in the remaining portion of the physical sector. In a case where there is an unexpected power loss while writing the physical sector, the runt data or both the runt data and the new data can become vulnerable to data loss in a conventional DSD.

FIG. 7B illustrates an example of a physical sector including new data and runt data according to an embodiment. As shown in FIG. 7B, logical sectors addressed logically as 82h to 85h include new data that does not fill the full physical sector since it is only four logical sectors. The new data can be part of a write command received from host 101 via host interface 126 to write the new data on disk 200. In other situations, the new data can be dirty data stored in NVSM 128 that is to be flushed to disk 200. In yet other situations, the new data can be data stored in a media based cache of disk 200 such as a zone of tracks 202 that is used to quickly access data.

In the example of FIG. 7B, runt data is added at logical sectors addressed as 80h, 81h, 86h, and 87h to fill the physical sector. The runt data includes data that was previously written on disk 200 and is relocated to the physical sector with the new data to fill the physical sector. After reading the runt data from disk 200, the runt data is stored in volatile memory 140 in write buffer 16. The new data may also be stored in write buffer 16 before writing the new data in the physical sector depending on how the new data is accessed.

FIG. 7C illustrates an example of an interruption while writing the physical sector of FIG. 7B according to an embodiment. As shown by the write gate in FIG. 7C, writing is interrupted while writing data for the logical sector 83h. The interruption can come from an unexpected power loss at DSD 106.

In such an example, the runt data and possibly the new data can be lost and the entire physical sector usually becomes unreadable if it is only partially written (i.e., a write splice). In addition, the runt data becomes missing or cannot be located if there is an unexpected power loss while writing the physical sector since the logical address for the runt data has been mapped to the new physical sector at the time of writing.

In view of the foregoing, the runt data stored in write buffer 16 is transferred from volatile memory 140 to NVSM 128 in the event of an unexpected power loss before the data is qualified as written in the physical sector. Any new data stored in write buffer 16 can also be transferred to NVSM 128 in the event of an unexpected power loss. In the case where the new data is dirty data flushed from NVSM 128 or where the new data remains stored in a media based cache of disk 200, some implementations may not store the new data in volatile memory 140. In such implementations, only the runt data stored in volatile memory 140 is transferred to NVSM 128 during an unexpected power loss. In the case where a write command is received from host 101, the new data will likely be stored in volatile memory 140 with the runt data and would therefore be transferred to NVSM 128 in the event of an unexpected power loss.

FIG. 8 is a flow chart for a write process that can be performed by controller 120 executing DSD firmware 10 for writing new data and runt data in a physical sector according to an embodiment. In block 802, a write command is received including new data to be written in a physical sector or new data is retrieved by controller 120 from NVSM 128 or disk 200.

In block 804, controller 120 controls head 136 to read runt data previously written on disk 200 in a physical sector. In block 806, at least the runt data is stored in volatile memory 140 such as in write buffer 16. As noted above, the new data may also be stored in volatile memory 140 with the runt data.

In block 808, controller 120 transfers the runt data and any new data from volatile memory 140 to NVSM 128 if a power loss occurs before determining whether the new data and the runt data are qualified as written in the physical sector. The qualification can, for example, be performed by servo system 121 which can determine whether the new data and runt data in the physical sector have been written within a threshold distance from a center of a track. The write process of FIG. 8 then ends.

After powering up following a power loss, the transferred data can be written to disk 200 before performing any commands involving the new data or the runt data. This can ordinarily ensure consistency in the data written on disk 200.

Other Embodiments

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks, modules, and processes described in connection with the examples disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. Furthermore, the foregoing processes can be embodied on a computer readable medium which causes a processor or computer to perform or execute certain functions.

To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, and modules have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those of ordinary skill in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, units, modules, and controllers described in connection with the examples disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The activities of a method or process described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The steps of the method or algorithm may also be performed in an alternate order from those provided in the examples. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable media, an optical media, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC).

The foregoing description of the disclosed example embodiments is provided to enable any person of ordinary skill in the art to make or use the embodiments in the present disclosure. Various modifications to these examples will be readily apparent to those of ordinary skill in the art, and the principles disclosed herein may be applied to other examples without departing from the spirit or scope of the present disclosure. The described embodiments are to be considered in all respects only as illustrative and not restrictive and the scope of the disclosure is, therefore, indicated by the following claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.