Enhanced phase interpolation circuit

Description

BACKGROUND

Clocked digital communications systems often require timing signals which are offset in phase or delay from a known reference clock signal, either to provide an appropriate set-up or hold interval, or to compensate for propagation delay between the point of use and the location of the reference clock source. Systems relying on a single reference clock often utilize fixed or adjustable delay lines or delay circuits to generate a secondary clock signal which is time-offset from the original reference. As another example, a serial communications receiver may have a local clock synthesized from received data transitions, which must be phase-shifted an appropriate amount to allow its use in sampling the received data stream. Alternatively, systems providing a multi-phase reference clock, one example being a two-phase quadrature clock, may utilize phase interpolation techniques to generate a secondary clock signal intermediate to the two reference clock phases; in other words, having a phase offset interpolated between those of the reference clock phases.

Such phase interpolators also found extensive use in RF communications applications, as one example in producing an output signal having a particular phase relationship used to drive one element of a multi-element antenna array, such that the collection of element arrays driven by such output signals resulted in an output beam with the desired directional characteristics.

In one such application, two sinusoidal reference input signals having relative phase relationships of 90 degrees (thus commonly referred to as sine and cosine signals) are presented as inputs to the phase interpolator having an output W of:
W=A*sin(ωt)+(1−A)*cos(ωt)  (Eqn. 1)
where the control input A is varied between (in this example) 0 and 1 to set the relative phase of output W as compared to reference inputs sin(ωt) and cos(ωt). Following common practice in the art, this document will utilize this well-known phase interpolator nomenclature, without implying any limitation to two phase clocks, sinusoidal signals, single-quadrant versus multiple-quadrant operation, or a particular domain of applicability.

BRIEF DESCRIPTION

A known limitation of conventional phase interpolation circuits is the non-linear nature of the relationship between the phase control signal and the resultant phase offset of the output signal. As will be readily apparent to one familiar with the art, Eqn. 1 implies that the phase of result W varies as arctan

( A 1 - A ) ,
which is linear near A=0.5 but significantly nonlinear as A decreases towards 0 or increases towards +1. In some applications, this non-linearity may simply be tolerated as an intractable source of clock jitter. In other applications, the non-linearity may be compensated by introduction of a correction function incorporated into operational generation of the controlling value A. Where such compensation cannot be performed, as one example where A is incrementally varied with the expectation of corresponding incremental phase adjustment to W, the nonlinearity complicates adjustment and, in the extreme case, may introduce operational instability in the resulting system.

An alternative phase interpolator is described, which utilizes the relationship

W = A * sin ⁡ ( ω ⁢ ⁢ t ) + ( 1 - A ) * cos ⁡ ( ω ⁢ ⁢ t ) ( Eqn . ⁢ 2 )
in at least one mode of operation. As implied by Eqn. 2, the phase of W in this alternative varies as arcsin(√{square root over (A)}), which is approximately linear over a wider range of A between 0 and +1, as compared to a phase interpolator utilizing the relationship of Eqn. 1.

BRIEF DESCRIPTION OF FIGURES

FIG. 1 illustrates one example of a prior art phase interpolation circuit.

FIG. 2 is a schematic circuit diagram of one embodiment of a phase interpolator in accordance with an embodiment.

FIGS. 3A, 3B, and 3C illustrate a conventional saturated current mirror circuit, said circuit modified to produce a current having a square root relationship to the reference current, and a hybrid circuit providing a mixture of linear and square root-related currents related to the reference current, respectively.

FIG. 4 is a graph showing the control transfer linearity of an embodiment compared to a prior art embodiment.

FIG. 5 is a flowchart of a process, in accordance with some embodiments.

DETAILED DESCRIPTION

FIG. 1 illustrates one example of a prior art phase interpolator circuit suitable for embodiment in, as one example, a linear integrated circuit. It accepts sinusoidal reference clock inputs having a fixed quadrature phase relationship, identified as sin(ωt) and cos(ωt), as well as differential control signal inputs A and Á which select the relative phase of an output signal produced at differential output W, as described by Eqn. 1.

As will be well understood by one familiar with the art, the circuit of FIG. 1 utilizes differential transistor pair 110 to partition a fixed source current I_B into two fractional currents I_B*A and I_B*(1−A) as directed by inputs A and Á, those fractional currents thus corresponding to the A and (1−A) factors of Eqn. 1. Fractional current I_B*A is mirrored by current mirror 160 to provide a current sink for differential pair 130, and fractional current I_B*(1−A) is mirrored by current mirror 170 to provide a current sink for differential pair 140. Reference clock signals sin(ωt) are input to 130, thus the current flow through 130 is a linear function of both I_B*A and sin(ωt). Similarly, reference clock signals cos (ωt) are input to 140, thus the current flow through 140 is a linear function of both I_B*(1−A) and cos(ωt). As differential transistor pairs 130 and 140 are connected in parallel to load resistors R_L1 and R_L2 across which differential output W is produced, output W is derived from the sum of the current flows through 130 and 140, thus representing a physical embodiment of the relationship described by Eqn. 1 above.

In one typical embodiment, output W includes a sinusoidal or approximately sinusoidal linear waveform having a phase relationship intermediate between those of the sin(ωt) and cos(ωt) reference clock inputs, as controlled by A in the region 0≦A≦1. In a further embodiment, outputs W and {acute over (W)} are digital waveforms comprising edge transitions having the described phase relationship, the digital output conversion occurring through the introduction such known functional element as a zero-crossing detector, digital comparator, or analog limiter, to convert the sinusoidal result of Eqn. 1 into a digital waveform.

A known limitation of this type of phase interpolation is the non-linear nature of the control relationship between the phase control signal value and the resultant phase offset of the output signal. As will be readily apparent to one familiar with the art, Eqn. 1 implies that the phase of result W varies as arctan

( A 1 - A ) ,
which is linear near the center of its range (e.g. around A=0.5) but becomes significantly nonlinear as A moves towards its extremes. Thus, a system reliant on a phase interpolator of this type where the phase of W is approximately 45 degrees offset from both the sine and cosine reference clocks would experience relatively smooth and consistent incremental variation of such phase for small incremental adjustments of A. However, as A is adjusted further, the amount of phase change per incremental change of A will begin to deviate from that consistent behavior by a nonlinearly varying amount.
Interpolation Using Square Root Terms

A new alternative to the phase interpolation method of Eqn. 1 utilizes differently computed weighting factors for the two quadrature clock terms to provide a more linear control term behavior. One embodiment of such an alternative phase interpolator utilizes the relationship

W = A * sin ⁡ ( ω ⁢ ⁢ t ) + ( 1 - A ) * cos ⁡ ( ω ⁢ ⁢ t ) ( Eqn . ⁢ 2 , repeated )
where A is again considered in the region 0≦A≦1. As implied by Eqn. 2, the phase of W in this alternative varies as arcsin(√{square root over (A)}), which is may be seen in the graph of FIG. 4 to be approximately linear over a wider range of A, as compared with the control relationship of the previous example.

A first embodiment is shown in the circuit diagram of FIG. 2. Comparison of that circuit with the prior art example of FIG. 1 shows the square root terms of Eqn. 2 are implemented in FIG. 2 using function blocks 260 and 270 replacing conventional current mirrors 160 and 170 of FIG. 1. Function blocks 260 and 270 are modified current mirror circuits incorporating a combination of saturated and triode-mode (a.k.a. linear) current transistors. It is well understood that the normal saturated-mode behavior of a current mirror circuit may be modified through the introduction of devices operating in a linear or non-saturated mode, and thus exhibiting square law behavior. Function block 260 mirrors input current I_B*A by producing mirror current sqrt(I_B*A), which sinks current from the sine differential pair 130. Similarly, function block 270 mirrors input current I_B*(1−A) by producing mirror current sqrt(I_B*(1−A)), which sinks current from the cosine differential pair 140. These modifications result in the circuit of FIG. 2 behaving as a physical embodiment of the relationship described by Eqn. 2.

As shown, FIG. 2 includes a phase control circuit, including differential current generator 110, which has a differential output node configured to provide a differential drive current. FIG. 2 also has current conversion circuit including current mirrors 260 and 270, each current mirror having saturated input FETs Mc1 and Mb1 connected to the differential output node configured to receive the differential drive current, the saturated input FETs also connected to a triode-mirroring FET Mb2. Triode-mirroring FETs Mb2 are configured to generate linearized current drive signals through first and second output drive nodes. First and second phase driver circuits 130 and 140 of a phase interpolator are connected to the first and second output drive nodes, respectively, the first phase driver circuit 130 configured to receive a first phase of a reference signal (sin(wt)) and the second phase driver circuit 140 configured to receive a second phase of the reference signal (cos(wt)), the phase interpolator configured to generate a phase interpolated reference signal, W.

Current Mirror Circuits

The analog computation used, as examples at 260 and 270 in the circuit of FIG. 2, are further illustrated in the three example embodiments shown in FIGS. 3A, 3B and 3C.

In the first embodiment of FIG. 3A, a saturated current mirror is shown producing a mirrored current flow Iph duplicating the source current flow Iph. It is well known that exact mirroring of the source current requires close matching of transistors Mc1 and Mc2, as well as Mb1 and Mb2. Conversely, the mirrored current may be scaled by a fixed factor by intentionally modifying transistor geometry; as one obvious example, doubling the channel width of Mc2 and Mb2 as compared to Mc1 and Mb1 also doubles the mirrored current, being equivalent to the addition of a parallel and identical current sink path.

In the second embodiment shown in FIG. 3B, a “linear” current mirror is shown, so-called as it incorporates a triode-connected current sink transistor (or triode-mirroring FET) operating in its linear or unsaturated mode, at Mb2. The square-law transfer characteristics of this transistor result is a mirrored current flow of sqrt(Iph) from source current Iph. The bias current Ibias is chosen to keep triode-mirroring FET Mb2 at an appropriate operating point to produce the desired behavior. In some embodiments, Ibias<Iph.

There are different ways to implement a current mirror in which the devices in the first stage are biased in strong inversion and the mirror transistor operates in triode (linear) region. The schematic diagram in FIG. 3B describes one possible implementation. In FIG. 3B, saturated-cascode FET Mb1, operating in strong inversion, carries the input current, and triode-mirroring FET Mb2 is the mirror device which is biased in triode region.

As Vgd(Mb1)=0, this device is working in saturation region. To put Mb2 in triode mode, it is necessary to have Vgd(Mb2)>Vth. Considering FIG. 3:
Vg(Mb2)=Vth+Vdsat(Mb1)  (1)
Vd(Mb2)=Vth+Vdsat(Mb3)−Vth−Vdsat(Mc2)  (2)
Hence:
Vgd(Mb2)=Vth+Vdsat(Mb1)−Vdsat(Mb3)+Vdsat(Mc2)  (3)

Properly choosing Ibias and the aspect ratio of Mb3, Mb1, and Mc2, it can be guaranteed that:
Vdsat(Mb1)−Vdsat(Mb3)+Vdsat(Mc2)>0  (4)
and consequently:
Vgd(Mb2)>Vth  (5)

Therefore, Mb2 will operate in triode region.

The third embodiment of FIG. 3C illustrates a mixed linear and saturated current mirror, here producing a combined mirrored current of (α*Iph)+β(√{square root over ((Iph))}) by combining both a saturated and a linear current mirror reflecting the same source current Iph. As previously described, transistor geometry within a current mirror may be modified so as to apply an additional scaling factor to a mirrored current, which are illustrated here by the multiplicative factors α and β, which allows the mixed current mirror design to be adapted to utilize different proportions of Eqn. 1 and Eqn. 2 behavior as desired. In one embodiment, all transistor geometries are identical, thus α=β=1.

In other embodiments, a number of identical parallel transistors are provided in each of the saturated and/or linear current mirrors of the previous examples, with the number of transistors activated in each current mirror selectable electronically by driving unneeded transistors into cutoff via a secondary gate signal, allowing the ratios (e.g. the scaling factor of the first embodiment, or the values of α and β of the third embodiment of FIG. 3C) to be changed. In an alternative embodiment, the channels of unneeded transistors are disconnected from the circuit via a separate series pass transistor.

It will be readily apparent to one of skill that other current mirror topologies known in the art may also be utilized in the described embodiments to equal result.

In some embodiments, an apparatus comprises a phase control circuit comprising, a differential current generator having a differential output node configured to provide a differential drive current, a current conversion circuit connected to the differential output node configured to receive the differential drive current through saturated input Field-Effect Transistors (FETs), the saturated input FETs connected to triode mirroring FETs, the triode mirroring FETs configured to generate linearized current drive signals through first and second output drive nodes, and, a phase interpolator circuit having a first phase driver circuit configured to receive a first phase of a reference signal, the first phase driver circuit connected to the first output drive node, and a second phase driver circuit configured to receive a second phase of the reference signal, the second phase driver circuit connected to the second output drive node, and configured to generate a phase interpolated reference signal.

In some embodiments, the phase interpolated reference signal represents a weighted sum of the first and second phases of the reference signal. In some embodiments, the first and second phases of the reference signal have weights determined by the linearized current drive signals.

In some embodiments, the current conversion circuit further comprises saturated-mirroring FETs configured to generate a portion of the linearized current drive signals. In some embodiments, the saturated-mirroring FETs are selectably enabled.

In some embodiments, the triode mirroring FETs are connected to saturated-cascode FETs, the saturated-cascode FETs are biased to force the triode-mirroring FETs into the triode region. In some embodiments, gate terminals of the saturated-cascode FETs are connected to a biasing circuit comprising a pair of gate-connected biasing FETs, one of the pair operating in saturation and the other of the pair operating in the triode region. In some embodiments, the biasing circuit further comprises a biasing current to bias the pair of gate-connected biasing FETs. In some embodiments, the biasing current is less than the differential drive current.

In some embodiments, the first phase and the second phase have a phase difference less than or equal to 90 degrees.

In some embodiments, the differential current generator is driven by a rotation input voltage signal.

FIG. 5 depicts a flowchart of a method 500, in accordance with some embodiments. As shown, method 500 includes the steps of receiving, at step 502, a differential drive current through saturated input Field-Effect Transistors (FETs), generating, at step 504, linearized current drive signals through triode mirroring FETs, the triode mirroring FETs connected to the saturated input FETs, receiving, at step 506, first and second phases of a reference signal, and generating, at step 508, using first and second phase driver circuits, a phase interpolated reference signal based on the received first and second phases of the reference signal and the linearized current drive signals.

In some embodiments, the phase interpolated reference signal represents a weighted sum of the first and second phases of the reference signal. In some further embodiments, the first and second phases of the reference signal have weights determined by the linearized current drive signals.

In some embodiments, a portion of the linearized current drive signals is generated using saturated-mirroring FETs. In further embodiments, the saturated-mirroring FETs are selectably enabled.

In some embodiments, the method further comprises biasing the triode-mirroring FETs into the triode region using saturated-cascode FETs connected to the triode mirroring FETs.

In some embodiments, the first phase and the second phase have a phase difference less than or equal to 90 degrees.

In some embodiments, the differential current generator is driven by a rotation input voltage signal.

In some embodiments, the phase interpolated reference signal has a waveform selected from the group consisting of: sinusoidal, approximately sinusoidal, a square wave, and a saw-tooth wave.

Waveform Effects

For clarity of explanation and consistency with past practice, the previous examples of phase interpolation have assumed the orthogonal reference clocks to be pure sinusoids, and to be orthogonally related in phase. However, other waveforms are equally applicable, and indeed may be more easily produced within a digital integrated circuit environment than pure sinusoids. As one example, pseudo-sinusoidal waveforms, i.e. those having predominantly sinusoidal characteristics but presenting some amount of residual waveform distortion or additional spectral content, often may be utilized in comparable manner to pure sinusoids.

It will be readily apparent to one familiar with the art that ideal square-risetime digital waveform clocks are not suitable reference inputs to the described forms of phase interpolator, as the summing characteristics of Eqn. 1 or Eqn. 2 will allow no distinguishable phase adjustment over a square-wave clock overlap period, obviating the usefulness of the circuit. However, in practical embodiments digital waveforms are not always ideal, and such “degraded” signals may be suitable for the described phase integration techniques. Examples of such degraded signals include digital waveforms having significant rise and fall times, including “rounded” square waves that have undergone significant high-frequency attenuation. Indeed, triangle waves in which the rise and fall times are comparable in duration to the quadrature clock overlap time are well known to be ideally suited for certain phase interpolation methods.

The relative control signal linearity of a phase interpolator operating on non-sinusoidal reference inputs will be dependent on both the actual signal waveforms and on the mixing algorithm used. Perfect triangle wave quadrature reference inputs, for example, are capable of producing completely linear control signal behavior with simple arithmetic summation (as described by Eqn. 1 and the Saturated circuit of FIG. 3A), while reference inputs having rounded (e.g. high frequency attenuated) or logarithmic (e.g. RC time constant constrained) rise times may show more linear control signal behavior with square root summation (as described by Eqn. 2 and the Linear circuit of FIG. 3B) or a mixture of linear and square root summation, such as produced by the mixed Saturated/Linear circuit of FIG. 3C.

In at least one embodiment, a mixed Saturated/Linear mirror circuit as shown in FIG. 3C is used within a phase interpolator circuit as in FIG. 2, wherein the “sine” and “cosine” reference inputs are “rounded” square wave signals having significant rise and fall duration throughout the quadrature overlap interval, and the α and β scaling factors of the mirror circuit of FIG. 3C are fixed at time of design and manufacture. In another embodiment, additional parallel transistors are provided in both the saturated and linear current mirrors, allowing the α and β scaling factors to be selected at time of initialization or operation by electronically disabling one or more of the additional parallel transistors. In a further embodiment, the current Ibias applied to the mirror circuit may be incrementally adjusted at time of system initialization or system operation, allowing incremental modification of the operating point of the current mirror transistors, and thus minor adjustment of the resulting mixed output behavior.

Similarly, any of the described embodiments may equally well be applied to produce an output result having an interpolated phase between two non-orthogonally-related inputs. As one example offered without limitation, the two clock inputs may have a 45 degree phase difference; in such cases the terms “sine” and “cosine” used herein should not be interpreted as limiting but instead as representing colloquial identifiers for such different-phased signals.