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Patent application title:

Chip scale LED packaging method

Publication number:

-

Publication date:
Application number:

15/197,797

Filed date:

2016-06-30

✅ Patent granted

Patent number:

US 9,653,660 B1

Grant date:

2017-05-16

PCT filing:

-

PCT publication:

-

Examiner:

Andres Munoz

Agent:

Leong C. Lei

Adjusted expiration:

2036-06-30

Smart Summary: A new method for packaging chip scale LEDs involves several steps to create efficient LED packages. First, two molds are clamped together, forming grooves where the LED chips will be placed. Then, encapsulation gel is poured into these grooves to secure the chips. After the gel hardens, the molds are separated, allowing each LED package to be removed easily. This method improves production efficiency by reducing the need for precise alignment of the chips during assembly. 🚀 TL;DR

Abstract:

A chip scale LED packaging method includes the following steps: clamping an upper mold with a plurality of through holes and a plate-shaped lower mold together; allowing bottoms of the plurality of through holes of the upper mold to be sealed by the plate-shaped lower mold to form a pattern of a plurality of grooves; placing chips one by one in corresponding through holes of the plurality of through holes; pouring encapsulation gel into each of the corresponding through holes; separating the upper mold from the plate-shaped lower mold after the encapsulation gel is cured and molded; and separating each cured and molded encapsulation gel from each of the corresponding through holes of the upper mold and taking each cured and molded encapsulation gel out of the upper mold to obtain an individual chip scale LED package.

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Classification:

  1. Electricity
  2. Basic electric elements

H01L33/52 »  CPC main

Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages Encapsulations

H01L21/561 »  CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer; Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups  - , e.g. sealing of a cap to a base of a container; Encapsulations, e.g. encapsulation layers, coatings Batch processing

H01L21/568 »  CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer; Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups  - , e.g. sealing of a cap to a base of a container; Encapsulations, e.g. encapsulation layers, coatings Temporary substrate used as encapsulation process aid

H01L23/3185 »  CPC further

Details of semiconductor or other solid state devices; Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape; Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body

H01L33/48 »  CPC further

Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages

H01L21/78 »  CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof; Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

H01L2933/005 »  CPC further

Details relating to devices covered by the group but not provided for in its subgroups; Processes relating to semiconductor body packages relating to encapsulations

H01L2933/0033 »  CPC further

Details relating to devices covered by the group but not provided for in its subgroups; Processes relating to semiconductor body packages

H01L21/56 IPC

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer; Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups  - , e.g. sealing of a cap to a base of a container Encapsulations, e.g. encapsulation layers, coatings

H01L23/31 IPC

Details of semiconductor or other solid state devices; Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape

Description

(a) TECHNICAL FIELD OF THE INVENTION

The present invention relates to a light emitting diode (LED) packaging technology, and more particularly to a chip scale LED packaging method.

(b) DESCRIPTION OF THE PRIOR ART

As everyone knows, global warming is becoming more and more serious such that energy saving and carbon reduction has become a topic advocated by all countries in the world in recent years, allowing a variety of environmentally friendly products conforming to energy-saving and carbon reduction to be taken seriously gradually. Among them, LED is a good example.

The so-called “chip class package” is the size of an encapsulation gel covering around a chip being very close to the size of the chip; it is defined generally as a packaging size being not more than 20% of the size of a chip. A conventional chip scale packaging process, as shown in FIG. 1, mainly includes the following steps: laying a layer of fixing film for fixation of LED chips 30 onto a carrier board 60; distributing a number of LED chips 30 in an array pattern on the surface of the fixing film, a gap being kept between two adjacent LED chips 30 for subsequent cutting; covering a layer of encapsulation gel on the array of LED chips 30; curing the encapsulation gel 40 by baking; cutting the array of the LED chips 30 into individual chip scale LED packaging bodies 50; and taking the individual chip scale LED packaging bodies 50 down from the fixing film.

However, the conventional chip scale packaging processes have the following disadvantages:

    • 1. the array arrangement of the chips 30, as FIG. 2 shows, should not have any angular deviation upon the process; namely, the high precision is required, resulting in reduced production efficiency.
    • 2. the position offset of the chip 30 must be smaller than 20 um; if the chip 30 is moved, a subsequent patch (surface mount technology, SMT) cannot be used.
    • 3. the array arrangement and cutting (indicated by cutting lines L in FIGS. 3 and 4) must be aligned precisely; if the positioning is not good, or the blade or the chip fixing position is skew, it will cause a bad cutting, resulting in a low cutting yield to form a high scrap rate.
    • 4. the thickness of the encapsulation gel 40 is not easy to be controlled even if it is the key to affect a color temperature quality.
    • 5. the cut individual chip scale LED packaging body 50 can only be square or rectangular. However, individual single light sources should have a variety of shape designs to meet market use requirements so as to match secondary optics to conform to lamp requirements.

SUMMARY OF THE INVENTION

The present invention proposes a chip scale LED packaging method, including the following steps: clamping an upper mold with a plurality of through holes and a plate-shaped lower mold together; allowing bottoms of the plurality of through holes of the upper mold to be sealed by the plate-shaped lower mold to form a pattern of a plurality of grooves; placing chips one by one in corresponding through holes of the plurality of through holes; pouring encapsulation gel into each of the corresponding through holes; separating the upper mold from the plate-shaped lower mold after the encapsulation gel is cured and molded; and separating each cured and molded encapsulation gel from each of the corresponding through holes of the upper mold and taking each cured and molded encapsulation gel out of the upper mold to obtain an individual chip scale LED package. The method can achieve accurate processing, the facilities are simple and production efficiency is high without any loss resulting from cutting such that it is suitable for mass production to meet the requirement of a large number of light sources in the market.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view of a conventional chip scale LED packing equipment and process;

FIGS. 2 to 4 are schematic views of arrangement and cutting conditions of chips involved in the conventional chip scale LED packaging process;

FIG. 5 is a schematically perspective view of molds used according to the present invention;

FIG. 6 is a schematically perspective view of the molds used according to the present invention while being combined together;

FIG. 7 is a top view of the molds used according to the present invention;

FIG. 8 is a cross-sectional view of the molds used according to the present invention;

FIG. 9 is a top view of the molds of the present invention after chips are placed therein;

FIG. 10 is a cross-sectional view of the molds of the present invention after chips are placed therein;

FIG. 11 is a top view of the molds of the present invention after encapsulation gel is poured in;

FIG. 12 is a cross-sectional view of the molds of the present invention after encapsulation gel is poured in;

FIG. 13 is a cross-sectional view of the molds of the present invention while the lower mold is separated after the encapsulation gel is cured;

FIG. 14 is a schematic view of the molds of the present invention while molded encapsulation gel therein is being taken out;

FIG. 15 is a top view of a package individual of the present invention;

FIG. 16 is a cross-sectional view of the package individual of the present invention; and

FIG. 17 is a bottom view of the package individual of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIGS. 5 to 17, a chip scale LED packaging method according to the present invention includes the following steps: providing an upper mold 10 having a plurality of through holes 11 and a plate-shaped lower mold 20 as shown in FIG. 5; clamping the upper mold 10 and the plate-shaped lower mold 20 together as shown in FIG. 6; allowing the plate-shaped lower mold 20 to be connected to the upper mold 10 to seal the bottoms of the plurality of through holes 11 of the upper mold 10 to form a plurality of bottom-sealed grooves as shown in FIGS. 7 and 8; placing chips 30 in a one by one manner in corresponding ones of the plurality of through holes 11 as shown in FIGS. 9 and 10; pouring encapsulation gel 40 into each of the corresponding through hole 11 as shown in FIGS. 11 and 12; separating the upper mold 10 from the plate-shaped lower mold 20 after the encapsulation gel 40 is cured and molded as shown in FIG. 13; and finally, using a blanking die 70 to separate each cured and molded encapsulation gel 40 from each of the corresponding through holes 11 of the upper mold 10 and taking each of the cured and molded encapsulation get out of each of the corresponding through holes of the upper mold, thereby obtaining individual chip scale packages 50 as shown in FIGS. 15, 16 and 17.

The present invention may use a upper mold 10 with through holes 11 of a different type to match the lower mold 20′ thereby making a variety of types of individual packages for optical design use.

The present invention has the following advantages:

    • 1. using different upper and lower molds designs can make a variety of shapes of chip scale LED package individuals for optical design use compared with conventional manufacturing methods, which can only make square or rectangular chip scale LED package individuals.
    • 2. the present invention can control the tolerances of the package individuals more precisely compared to conventional cutting manufacturing processes, and the thickness and exterior dimension of the individual package is the key to control the color temperature and light type of a light emitting individual.
    • 3. each package individual of the present invention is made independently, which will not cause the situation that the whole batch production is scrapped due to some problems such as arrangement or machine setting such that the productivity can be increased relatively.
    • 4. the manufacturing process of the present invention is precise, the facilities simple and the productive efficiency high without cutting tear and wear such that it is suitable for mass production to meet the requirement of a large number of light sources in the market.
    • 5. conventional cutting processes must enlarge or widen the distance of the encapsulation gel of chips, causing the material waste, and the cutting cannot be carried out closely to the chip, thereby avoiding damaging the chip such that the encapsulation gel around the chip is thicker. But, the manufacturing process of the present invention can make ultra-small, ultra-thin package individuals, realizing a real chip scale package (CSP).

Claims

I claim:

1. A chip scale light emitting diode (LED) packaging method, comprising the following steps:

clamping an upper mold having a plurality of through holes and a plate-shaped lower mold together;

allowing bottoms of said plurality of through holes of said upper mold to be sealed by said plate-shaped lower mold to form a plurality of bottom-sealed grooves that are separated from each other;

placing a chip in each of said plurality of through holes;

pouring encapsulation gel into each of said plurality of through holes to enclose each of said chips;

separating said upper mold from said plate-shaped lower mold after said encapsulation gel is cured and molded; and

applying a blanking die from tops of said plurality of through holes of said upper mold to simultaneously drive said chips out of said plurality of through holes of said upper mold for separating each said cured and molded encapsulation gel from each of said plurality of through holes of said upper mold and taking each said cured and molded encapsulation gel out of said upper mold to obtain an individual chip scale LED package.

Resources

Images & Drawings included:

Fig. 01 - Chip scale LED packaging method
Fig. 01
Fig. 02 - Chip scale LED packaging method
Fig. 02
Fig. 03 - Chip scale LED packaging method
Fig. 03
Fig. 04 - Chip scale LED packaging method
Fig. 04
Fig. 05 - Chip scale LED packaging method
Fig. 05
Fig. 06 - Chip scale LED packaging method
Fig. 06
Fig. 07 - Chip scale LED packaging method
Fig. 07

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