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Patent application title:

Method for manufacturing thin film transistor (TFT) array substrate

Publication number:

-

Publication date:
Application number:

15/575,684

Filed date:

2017-11-10

✅ Patent granted

Patent number:

US 10,083,999 B1

Grant date:

2018-09-25

PCT filing:

WO; PCT/CN2017/110325; 20171110

PCT publication:

-

Examiner:

David S Blum

Agent:

Kirton McConkie | Evan R. Witt

Adjusted expiration:

2037-11-10

Smart Summary: A method for making a thin film transistor (TFT) array substrate is described. It starts with a substrate where layers of metal, insulation, and metal oxide are added. A first metal layer is then created on top of the metal oxide, followed by a photoresist layer that helps shape this layer into a second metal layer with a defined channel. The process includes extending part of the photomask beyond the second metal layer to prevent over-etching during manufacturing. This approach aims to improve the quality and efficiency of producing TFT array substrates. 🚀 TL;DR

Abstract:

The present invention provides a method for manufacturing a TFT array substrate, comprises: providing a substrate; depositing a metal gate electrode, an insulating layer, and a metal oxide layer on a surface of the substrate; forming a first metal layer on a surface of the metal oxide layer; depositing a photoresist layer on the first metal layer and implementing a photolithography process to the first metal layer to be configured as a second metal layer, a channel is defined in the second metal layer; and a portion of the photomask vertically corresponding to the channel of the second metal layer is extended greater than the second metal layer.

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Classification:

  1. Electricity
  2. Basic electric elements

H01L27/1288 »  CPC main

Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs; Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

G02F1/1368 »  CPC further

Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells; Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements; Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit; Active matrix addressed cells in which the switching element is a three-electrode device

H01L27/127 »  CPC further

Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs; Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

H01L27/1225 »  CPC further

Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

H01L29/247 »  CPC further

Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor; Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups Amorphous materials

H01L21/00 IPC

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/16 IPC

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising cuprous oxide or cuprous iodide

H01L27/12 IPC

Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

H01L29/24 IPC

Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor; Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups

H01L29/786 IPC

Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor; Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched; Unipolar devices, e.g. field effect transistors; Field effect transistors with field effect produced by an insulated gate Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Description

BACKGROUND OF INVENTION

Field of Invention

The present invention relates to displays, and particularly to a method for manufacturing a TFT array substrate.

Description of Prior Art

Thin film transistor-liquid crystal displays (TFT-LCDs) are the most widely used flat panel displays. With methods for manufacturing liquid crystal displays becoming more and more mature and advanced, manufacturing process is simplified, manufacturing time is reduced, and an important way for competing in the industry is to increase process efficiency to reduce production costs.

Indium gallium zinc oxide (IGZO) is amorphous oxide including indium, gallium, and zinc. The IGZO has a high mobility rate, and a mobility rate of current carrier is 20-30 times more than amorphous silicon to improve charge-discharge speed between the TFT and pixel electrode, and has a high on current and a low off current to rapidly turn on and off, to improve pixel response speed, to have faster refresh rates, and improve a line scanning rate of pixels to make TFT-LCDs have an ultrahigh resolution.

Referring to FIG. 1, in a conventional IGZO 4 MASK process, because a halftone photomask 101 has a source and drain electrode metal layer 205 and the IGZO 204 exposed at the same time, then is etched 2 or 3 times by acid, a channel 206 is formed. Because of multiple acid etchings, the source and drain electrode metal layer 205 and the IGZO 204 become over etched.

SUMMARY OF THE INVENTION

The application mainly provides a method for manufacturing a TFT array substrate to avoid a problem of the source and drain electrode metal layer and the IGZO being over etched during more times etching and to improve a finished product ratio of a process of manufacturing TFT array substrate.

For the above-mentioned objective, the present disclosure employs the following technical schemes.

A method for manufacturing a TFT array substrate, comprising:

a step S10 of providing a substrate;

a step S20 of depositing a metal gate electrode on a surface of the substrate;

a step S30 of forming an insulating layer on a surface of the metal gate electrode;

a step S40 of forming a metal oxide layer on a surface of the insulating layer;

a step S50 of forming a first metal layer on a surface of the metal oxide layer;

a step S60 of depositing a photoresist layer on a surface of the first metal layer and implementing a first photolithography process with a photomask to the first metal layer to be configured as a second metal layer, wherein a channel is defined in the second metal layer;

a step S70 of employing a second photolithography process with a photomask to the second metal layer; and

wherein, a portion of the photomask vertically corresponding to the channel of the second metal layer is extended greater than the second metal layer.

In the method for manufacturing the TFT array substrate, the photomask of the step S60 is a halftone photomask.

In the method for manufacturing the TFT array substrate, the second metal layer is a source and drain electrode metal layer.

In the method for manufacturing the TFT array substrate, the metal oxide layer is an indium gallium zinc oxide layer.

In the method for manufacturing the TFT array substrate, a portion of the halftone photomask vertically corresponding to the channel of the second metal layer is extended greater than the second metal at least 1 μm.

In the method for manufacturing the TFT array substrate, an unilateral length of the first metal layer is greater than an unilateral length of the second metal layer from 1 μm to 3 μm.

In the method for manufacturing the TFT array substrate, the step S60 further comprises implementing a third photolithography process with the halftone photomask to the indium gallium zinc oxide layer.

In the method for manufacturing the TFT array substrate, after a first photolithography process to the source and drain electrode metal layer, a third photolithography process is employed to the indium gallium zinc oxide layer.

In the method for manufacturing the TFT array substrate, the first photolithography process of the source and drain electrode metal layer and the third photolithography process of the indium gallium zinc oxide layer are implemented at the same time.

A method for manufacturing a TFT array substrate, comprising:

a step S10 of providing a substrate;

a step S20 of depositing a metal gate electrode on a surface of the substrate;

a step S30 of forming an insulating layer on a surface of the metal gate electrode;

a step S40 of forming a metal oxide layer on a surface of the insulating layer;

a step S50 of forming a first metal layer on a surface of the metal oxide layer;

a step S60 of depositing a photoresist layer on a surface of the first metal layer and implementing a first photolithography process with a photomask to the first metal layer to be configured as a second metal layer, wherein a channel is defined in the second metal layer; and

wherein, a portion of the photomask vertically corresponding to the channel of the second metal layer is extended greater than the second metal layer.

In the method for manufacturing the TFT array substrate, the photomask of the step S60 is a halftone photomask.

In the method for manufacturing the TFT array substrate, the second metal layer is a source and drain electrode metal layer.

In the method for manufacturing the TFT array substrate, the metal oxide layer is an indium gallium zinc oxide layer.

In the method for manufacturing the TFT array substrate, a portion of the halftone photomask vertically corresponding to the channel of the second metal layer is extended greater than the second metal at least 1 μm.

In the method for manufacturing the TFT array substrate, an unilateral length of the first metal layer is greater than an unilateral length of the second metal layer from 1 μm to 3 μm.

In the method for manufacturing the TFT array substrate, the step S60 further comprises implementing a third photolithography process with the halftone photomask to the indium gallium zinc oxide layer.

In the method for manufacturing the TFT array substrate, after a first photolithography process implemented to the source and drain electrode metal layer, a third photolithography process is employed to the indium gallium zinc oxide layer.

In the method for manufacturing the TFT array substrate, the first photolithography process of the source and drain electrode metal layer and the third photolithography process of the indium gallium zinc oxide layer are implemented at the same time.

This application provides a method for manufacturing a TFT array substrate, a portion of a photomask vertically corresponding to a channel of a second metal layer is greater than a second metal layer to avoid a problem of too much loss in a channel of the IGZO layer being made by the IGZO layer being over etched by over times etching and to improve a finished product ratio of a process of manufacturing TFT array substrate.

BRIEF DESCRIPTION OF DRAWINGS

In order to describe clearly the embodiment in the present disclosure or the prior art, the following will introduce the drawings for the embodiment shortly. Obviously, the following description is only a few embodiments, for the common technical personnel in the field it is easy to acquire some other drawings without creative work.

FIG. 1 is a structure diagram of a photomask in a conventional technology.

FIG. 2 is a flowchart of a method for manufacturing a TFT array substrate according to one exemplary embodiment of the present disclosure.

FIGS. 3a-3f are structure diagrams of the method for manufacturing the TFT array substrate according to exemplary embodiments of the present disclosure.

FIG. 4 is a structure diagram of a photomask according to one exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The description of following embodiment, with reference to the accompanying drawings, is used to exemplify specific embodiments which may be carried out in the present disclosure. Directional terms mentioned in the present disclosure, such as “top”, “bottom”, “front”, “back”, “left”, “right”, “inside”, “outside”, “side”, etc., are only used with reference to the orientation of the accompanying drawings. Therefore, the used directional terms are intended to illustrate, but not to limit, the present disclosure. In the drawings, the components having similar structures are denoted by same numerals.

The following combination of the attached drawings and specific embodiments will further illustrate the application.

FIG. 2 is a flowchart of a method for manufacturing a TFT array substrate according to one exemplary embodiment of the present disclosure. FIGS. 3a-3f are structure diagrams of the method for manufacturing the TFT array substrate according to exemplary embodiments of the present disclosure.

Referring to FIG. 3a, a step S10 of providing a substrate 201.

In the step S10, the substrate 201 can be a rigid substrate, and the rigid substrate can be a glass substrate.

Referring to FIG. 3b, a step S20 of depositing a metal gate electrode 202 on a surface of the substrate 201.

The metal gate electrode 202 is a gate electrode of the TFT array substrate, is formed on the surface of the substrate 201 by a sputtering process, and is connected to a pixel electrode.

Referring to FIG. 3c, a step S30 of forming an insulating layer 203 on a surface of the metal gate electrode 202.

The insulating layer 203 of the step S30 is made one of a combination of silicon nitride or silicon oxide. The insulating layer 203 can be formed on the surface of the metal gate electrode 202 and covers the metal gate electrode 202 by physical vapor deposition.

Referring to FIG. 3d, a step S40 of forming a metal oxide layer 204 on a surface of the insulating layer 203.

In this exemplary embodiment, the metal oxide layer 204 is an indium gallium zinc oxide (IGZO) layer. Non-crystal IGZO is material used in channels in a new TFT technology.

IGZO is amorphous oxide including indium, gallium, and zinc. The IGZO has a high mobility rate, and a mobility rate of current carrier is more 20-30 times than amorphous silicon to improve charge-discharge velocity between the TFT and pixel electrode, and has a high on current and a low off current to rapidly turn on and off, to improve a response speed of pixels, to have a faster refresh rate, and to improve a line scanning rate of pixels to make the TFT-LED have a ultrahigh resolution.

Referring to FIG. 3e, a step S50 of forming a first metal layer 205 on a surface of the metal oxide layer 204. The first metal layer 205 is a source and drain electrode metal layer and comprises a source electrode and a drain electrode of the TFT array substrate.

The first metal layer 205 is a source and drain electrode metal layer without etched. In this exemplary embodiment, an unilateral length of the first metal layer is greater 2 μm than an unilateral length of the second metal layer.

Referring to FIG. 3f, a step S60 of depositing a photoresist layer on a surface of the first metal layer 205 and implementing a first photolithography process with a photomask 102 to the first metal layer 205 to be configured as a second metal layer 205a, wherein a channel 206 is defined in the second metal layer 205a.

A portion of the photomask vertically corresponding to the channel of the second metal layer 205a is extended greater than the second metal layer 205a.

The step S60 is main technical features of this application. The portion of the photomask 102 vertically corresponding to the channel 206 is greater than a second metal layer 205a, part of the indium gallium zinc oxide layer 204 is retained and perpendicular to the channel 206 by etching the first metal layer 205 to avoid a problem of too much loss in a channel 206 being over etched.

The portion of the halftone photomask vertically corresponding to the channel of the second metal layer is extended greater than the second metal at least 1 μm, because during many experiments, after the TFT array substrate is etched by three times wet etch and one time dry etch (for example, a rate W/L of the channel is 6 μm/6 μm), the indium gallium zinc oxide layer 204 is extended greater 1.5 μm than the second metal layer 205a, and the second metal layer 205a losses 1.5 μm after etched. During designing the photomask 102, the portion of the halftone photomask vertically corresponding to the channel of the second metal layer is extended greater than the second metal at least 1 μm to avoid the rate W/L of the channel reduce.

In this exemplary embodiment, a halftone photomask 102 is used for implementing a photolithography process to the indium gallium zinc oxide layer 204.

During the photolithography process, a photosensitive material is coated on a surface of an etched material, and after a lithography process, the photosensitive material protects the etched material, and a permanent graphic is formed by etching.

In this exemplary embodiment, after a photolithography process to the source and drain electrode metal layer, a photolithography process is employed to the indium gallium zinc oxide layer 204. The first metal layer 205 is etched by three times wet etch and one time dry etch in this application.

In other exemplary embodiments, a photolithography process of the source and drain electrode metal layer and a photolithography process of the indium gallium zinc oxide layer 204 are implemented at the same time. The first metal layer 205 can be etched by two times wet etch and one time dry etch in this application. This application is not limited to the two methods above

In this exemplary embodiment, the method for manufacturing the TFT array substrate further comprises a step S70 of employing a second photolithography process with a photomask to the second metal layer.

The second metal layer 205a can be etched by a photolithography process with a photomask 102.

This application provides a method for manufacturing a TFT array substrate, a portion of a photomask vertically corresponding to a channel of a second metal layer is greater than a second metal layer to avoid a problem of too much loss in a channel of the IGZO layer being made by the IGZO layer being over etched by over times etching and to improve a finished product ratio of a process of manufacturing TFT array substrate.

As is understood by persons skilled in the art, the foregoing preferred embodiments of the present disclosure are illustrative rather than limiting of the present disclosure. It is intended that they cover various modifications and that similar arrangements be included in the spirit and scope of the present disclosure, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures.

Claims

What is claimed is:

1. A method for manufacturing a thin film transistor (TFT) array substrate, comprising:

a step S10 of providing a substrate;

a step S20 of depositing a metal gate electrode on a surface of the substrate;

a step S30 of forming an insulating layer on a surface of the metal gate electrode;

a step S40 of forming a metal oxide layer on a surface of the insulating layer;

a step S50 of forming a first metal layer on a surface of the metal oxide layer;

a step S60 of depositing a photoresist layer on a surface of the first metal layer and implementing a first photolithography process with a photomask to the first metal layer to be configured as a second metal layer, wherein a channel is defined in the second metal layer;

a step S70 of employing a second photolithography process with a photomask to the second metal layer; and

wherein, a portion of the photomask vertically corresponding to the channel of the second metal layer is extended greater than the second metal layer.

2. The method for manufacturing the TFT array substrate of claim 1, wherein the photomask of the step S60 is a halftone photomask.

3. The method for manufacturing the TFT array substrate of claim 2, wherein the second metal layer is a source and drain electrode metal layer.

4. The method for manufacturing the TFT array substrate of claim 3, wherein the metal oxide layer is an indium gallium zinc oxide layer.

5. The method for manufacturing the TFT array substrate of claim 4, wherein a portion of the halftone photomask vertically corresponding to the channel of the second metal layer is extended greater than the second metal at least 1 μm.

6. The method for manufacturing the TFT array substrate of claim 1, wherein an unilateral length of the first metal layer is greater than an unilateral length of the second metal layer from 1 μm to 3 μm.

7. The method for manufacturing the TFT array substrate of claim 4, wherein the step S60 further comprises implementing a third photolithography process with the halftone photomask to the indium gallium zinc oxide layer.

8. The method for manufacturing the TFT array substrate of claim 7, wherein after a first photolithography process implemented to the source and drain electrode metal layer, a third photolithography process is employed to the indium gallium zinc oxide layer.

9. The method for manufacturing the TFT array substrate of claim 7, wherein the first photolithography process of the source and drain electrode metal layer and the third photolithography process of the indium gallium zinc oxide layer are implemented at the same time.

10. A method for manufacturing a thin film transistor (TFT) array substrate, comprising:

a step S10 of providing a substrate;

a step S20 of depositing a metal gate electrode on a surface of the substrate;

a step S30 of forming an insulating layer on a surface of the metal gate electrode;

a step S40 of forming a metal oxide layer on a surface of the insulating layer;

a step S50 of forming a first metal layer on a surface of the metal oxide layer;

a step S60 of depositing a photoresist layer on a surface of the first metal layer and implementing a first photolithography process with a photomask to the first metal layer to be configured as a second metal layer, wherein a channel is defined in the second metal layer; and

wherein, a portion of the photomask vertically corresponding to the channel of the second metal layer is extended greater than the second metal layer.

11. The method for manufacturing the TFT array substrate of claim 10, wherein the photomask of the step S60 is a halftone photomask.

12. The method for manufacturing the TFT array substrate of claim 11, wherein the second metal layer is a source and drain electrode metal layer.

13. The method for manufacturing the TFT array substrate of claim 12, wherein the metal oxide layer is an indium gallium zinc oxide layer.

14. The method for manufacturing the TFT array substrate of claim 13, wherein a portion of the halftone photomask vertically corresponding to the channel of the second metal layer is extended greater than the second metal at least 1 μm.

15. The method for manufacturing the TFT array substrate of claim 10, wherein an unilateral length of the first metal layer is greater than an unilateral length of the second metal layer from 1 μm to 3 μm.

16. The method for manufacturing the TFT array substrate of claim 13, wherein the step S60 further comprises implementing a third photolithography process with the halftone photomask to the indium gallium zinc oxide layer.

17. The method for manufacturing the TFT array substrate of claim 16, wherein after a first photolithography process implemented to the source and drain electrode metal layer, a third photolithography process is employed to the indium gallium zinc oxide layer.

18. The method for manufacturing the TFT array substrate of claim 16, wherein the first photolithography process of the source and drain electrode metal layer and the third photolithography process of the indium gallium zinc oxide layer are implemented at the same time.

Resources

Images & Drawings included:

Fig. 01 - Method for manufacturing thin film transistor (TFT) array substrate
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Fig. 02 - Method for manufacturing thin film transistor (TFT) array substrate
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Fig. 03 - Method for manufacturing thin film transistor (TFT) array substrate
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Fig. 04 - Method for manufacturing thin film transistor (TFT) array substrate
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Fig. 05 - Method for manufacturing thin film transistor (TFT) array substrate
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