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Patent application title:

Fin-type field effect transistor and method of forming the same

Publication number:

-

Publication date:
Application number:

15/654,552

Filed date:

2017-07-19

✅ Patent granted

Patent number:

US 10,163,659 B1

Grant date:

2018-12-25

PCT filing:

-

PCT publication:

-

Examiner:

Nathan W Ha

Agent:

J.C. Patents

Adjusted expiration:

2037-07-19

Smart Summary: A FinFET is a type of transistor that helps improve the speed and performance of electronic devices. It consists of several layers, including a substrate, a buffer layer, an insulating layer, a fin, and a gate. The buffer layer sits on the substrate and has a small recess, while the insulating layer has structures that isolate different parts and a trench in between. The fin extends from the buffer layer into the trench of the insulating layer, and the gate surrounds the fin to control its electrical activity. This design allows for better control over the flow of electricity in the transistor, making it more efficient for modern technology. 🚀 TL;DR

Abstract:

A FinFET and a method of forming the same are provided. The FinFET includes a substrate, a buffer layer, an insulating layer, a fin and a gate. A buffer layer is disposed over the substrate, and includes a recess without penetrating the buffer layer. The insulating layer is disposed over the buffer layer, and includes a plurality of isolation structures and a trench between the isolation structures. The fin is disposed in the recess of the buffer layer and the trench of the insulating layer. The gate is disposed across the fin.

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Classification:

  1. Electricity
  2. Basic electric elements

H01L21/485 »  CPC main

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer; Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups -; Conductive parts; Leads on or in insulating or insulated substrates, e.g. metallisation Adaptation of interconnections, e.g. engineering charges, repair techniques

H01L29/785 »  CPC further

Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor; Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched; Unipolar devices, e.g. field effect transistors; Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

H01L29/78 IPC

Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor; Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched; Unipolar devices, e.g. field effect transistors; Field effect transistors with field effect produced by an insulated gate

H01L21/48 IPC

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups -

H01L29/66 IPC

Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor Types of semiconductor device ; Multistep manufacturing processes therefor

Description

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to a semiconductor structure and a method of forming the same, and particularly relates to a fin-type field effect transistor (FinFET) and a method of forming the same.

Description of Related Art

With rapid progress of semiconductor processing techniques, it has been necessary to continuously reduce dimensions of circuit elements and increase the integration of the elements in order to improve speed and performance of the elements. Currently, a three-dimensional multiple-gate structure such as a FinFET, for example, has been developed for replacing a complementary metal oxide semiconductor (CMOS) element. The FinFET has a fin portion extending vertically upward from a surface of a substrate and a gate disposed around the fin portion, thereby providing better electric control of a channel of the FinFET.

SUMMARY OF THE INVENTION

Accordingly, the present invention provides a FinFET and a method of forming the same, in which a buffer layer is simultaneously disposed below isolation structures and a fin between the isolation structures.

The present invention provides a FinFET. The FinFET includes a substrate, a buffer layer, an insulating layer, a fin and a gate. A buffer layer is disposed over the substrate, and includes a recess without penetrating the buffer layer. The insulating layer is disposed over the buffer layer, and includes a plurality of isolation structures and a trench between the isolation structures. The fin is disposed in the recess of the buffer layer and the trench of the insulating layer. The gate is disposed across the fin.

According to an embodiment of the present invention, a thickness of the buffer layer under the fin is less than a thickness of the buffer layer under the isolation structures.

According to an embodiment of the present invention, a depth of the recess ranges from 30 angstroms to 50 angstroms.

According to an embodiment of the present invention, a thickness of the buffer layer ranges from 60 angstroms to 100 angstroms.

According to an embodiment of the present invention, the recess is aligned with and has a same size of the trench.

According to an embodiment of the present invention, the fin protrudes from the insulating layer.

According to an embodiment of the present invention, a material of the buffer layer is different from a material of the fin and a material of the substrate.

According to an embodiment of the present invention, a material of the buffer layer includes at least one of Ge, SiGe, InP, InAs, GaSb, GaAs, AlSb, GaAsP, InGaAs, InGaP, InGaSb, InAlAs, AlGaSb, AlAsSb or a combination thereof.

According to an embodiment of the present invention, the buffer layer includes multiple layers.

The present invention further provides a method of forming a FinFET. A buffer layer is formed over a substrate. An insulating layer is formed over the buffer layer. An opening is formed in the insulating layer and the buffer layer without penetrating the buffer layer. A fin is formed in the opening. A gate is formed across the fin.

According to an embodiment of the present invention, the step of forming an opening includes the following steps. A portion of the insulating layer is removed, so as to form a trench penetrating the insulating layer. By using the insulating layer having the trench as a mask, a portion of the buffer layer is removed, so as to form a recess without penetrating the buffer layer.

According to an embodiment of the present invention, the recess is aligned with and has a same size of the trench.

According to an embodiment of the present invention, the step of removing a portion of the buffer layer is performed by using a mixed gas containing a stop etching gas and an etching gas, the stop etching gas includes carbon (C) and fluoride (F), and the etching gas includes silicon (Si) and chloride (Cl).

According to an embodiment of the present invention, the stop etching gas is selected from a group consisting of CF4, C2F6, C3F8, CHF3, CH2F2 and CBrF3.

According to an embodiment of the present invention, the etching gas is selected from a group consisting of SiCl4, SiH2Cl2 and SiHCl3.

According to an embodiment of the present invention, the mixed gas further includes a rare gas selected from a group consisting of He, Ne, Ar, Kr, Xe and Rn.

According to an embodiment of the present invention, the step of forming a fin includes epitaxially growing the fin on the buffer layer exposed by the opening.

According to an embodiment of the present invention, the fin is formed as protruding from the insulating layer.

According to an embodiment of the present invention, a material of the buffer layer is different from a material of the fin and a material of the substrate.

According to an embodiment of the present invention, a material of the buffer layer includes a least one of Ge, SiGe, InP, InAs, GaSb, GaAs, AlSb, GaAsP, InGaAs, InGaP, InGaSb, InAlAs, AlGaSb, AlAsSb or a combination thereof.

In view of the above, in the FinFET of the present invention, by forming recesses in the buffer layer without penetrating the buffer layer, the buffer layer is simultaneously disposed below isolation structures and fins between the isolation structures. In detail, the fin is disposed in the recess of the buffer layer, that is, the fin may be grown in the recess of the buffer layer, and thus compared with directly grown on the substrate, the fin may be grown more easily. In addition, the buffer layer is formed before forming the fins, and thus the buffer layer may have a good uniformity. Therefore, the process of forming the FinFET can be simplified and efficient, and the FinFET may have an improved performance.

Several exemplary embodiments accompanied with figures are described in detail below to further describe the present invention in details.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1A to FIG. 1E are schematic perspective views of a method of forming a FinFET according to an embodiment of the present invention.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG. 1A to FIG. 1E are schematic perspective views of a method of forming a FinFET according to an embodiment of the present invention.

Referring to FIG. 1A, a buffer layer 110 is formed over a substrate 100. The substrate 100 can be a semiconductor substrate, and includes Si, SiGe, Ge, SiC, InAs, InP, GaSb, GaAs, GaAsSb, the like or a combination thereof. A material of the buffer layer 110 is different from the substrate 100. In an embodiment, the buffer layer 110 includes at least one of Ge, SiGe, InP, InAs, GaSb, GaAs, AlSb, GaAsP, InGaAs, InGaP, InGaSb, InAlAs, AlGaSb, AlAsSb, the like or a combination thereof, and the forming method thereof includes performing a suitable deposition process such as chemical vapor deposition (CVD). In an embodiment, the buffer layer 110 may be a single layer or include multiple layers. A thickness t of the buffer layer 110 ranges from 60 angstroms to 100 angstroms, for example.

Then, an insulating layer 120 is formed over the buffer layer 110. In an embodiment, a material of the insulating layer 120 may be oxide (such as a silicon oxide), nitride (such as a silicon nitride), the like or a combination thereof; and the forming method thereof includes performing a suitable deposition process such as CVD, a thermal oxidation, the like or a combination thereof.

Referring to FIG. 1B, at least one trench 124 is formed in the insulating layer 120. The method of forming the trench 124 includes removing a portion of the insulating layer 120 by a suitable photolithographic and etching technique such as reactive ion etching (RIE), a sputter etch, capacitively coupled plasma (CCP), inductively coupled plasma (ICP), or the like. In an embodiment, after forming the trenches 124, a plurality of isolation structures 122 such as shallow trench isolation (STI) structures is formed, and the trenches 124 are disposed between the isolation structures 122. In an embodiment, a thickness of the isolation structure 122 ranges from 500 angstroms to 700 angstroms, for example.

Referring to FIG. 1C, at least one recess 112 is formed in the buffer layer 110 without penetrating the buffer layer 110. The recess 112 is aligned with the trench 124, that is, a size of the recess 112 is substantially the same as a size of the trench 124. In an embodiment, the recess 112 and the trench 124 may be collectively referred to as an opening. In an embodiment, the method of forming the recess 112 includes removing a portion of the buffer layer 110 by using the insulating layer 120 having the trench 124 as a mask. The buffer layer 110 may be removed by a mixed gas containing a stop etching gas and an etching gas. In an embodiment, the stop etching gas may include carbon (C), fluoride (F), the like, or a combination thereof; and the stop etching gas may be selected from a group consisting of CF4, C2F6, C3F8, CHF3, CH2F2, CBrF3, the like, or a combination thereof. The etching gas may include silicon (Si), chloride (Cl), the like, or a combination thereof, and the etching gas may be selected from a group consisting of SiCl4, SiH2Cl2, SiHCl3, the like, or a combination thereof. In an embodiment, the mixed gas may further include a rare gas selected from a group consisting of He, Ne, Ar, Kr, Xe, Rn, the like, or a combination thereof. In an embodiment, a depth d of the recess 112 ranges from 30 angstroms to 50 angstroms, for example. In another embodiment, the trench 124 and the recess 112 aligned with the trench 124 may be formed simultaneously.

Referring to FIG. 1D, a fin 130 is formed in the recess 112 and the trench 124. In an embodiment, the method of forming the fin 130 includes epitaxially growing the fin 130 on the buffer layer 110 exposed by the recess 112. In an embodiment, the material of the fin 130 may include a group-III, a group-IV, a group-V semiconductor material, or a combination thereof, such as SiGe, InAs, InGaAs, InGaP, AlInSb or the like. The method of forming the fin 130 includes performing an epitaxial growth process such as vapor phase epitaxy (VPE), metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), solid phase epitaxy (SPE) or a suitable epitaxy technique.

In an embodiment, materials of the substrate 100, the buffer layer 110 and the fin 130 are different and lattice constants thereof are matched, and some examples are shown in Table 1 below, but the invention is not limited thereto. In an embodiment, the buffer layer 110 includes a relaxed silicon germanium alloy, and the fin 130 includes a tensile strained silicon such as silicon or a silicon germanium alloy having a germanium content less than the germanium content of the relaxed silicon germanium alloy of the buffer layer 110. Alternatively, the fin 130 includes a compressive strained silicon-containing germanium alloy having a germanium content higher than the germanium content of the relaxed silicon germanium alloy of the buffer layer 110.

TABLE 1
Substrate SixGe1−x InP GaSb Ge GaAs Si GaAs GaAsSb
Buffer SiyGe1−y, InxGa1−xAs, AlSb SixGe1−x GaAsxP1−x GaAs/ AlGaSb/ AlAsSb
layer where where x > InAlAs InGaSb
y > x 0.53
Fin SixGe1−z, InyGa1−yAs, InAs InyGa1−yAs InyGa1−yP, InGaAs AlInSb InGaAs
where where y < where y >
z < x 0.53 0.51

In an embodiment, the fin 130 extends along a first direction. In an embodiment, the fin 130 protrudes from the insulating layer 120, and a height of the protruded portion of the fin 130 from the top of the insulating layer 120 may be 300 angstroms to 400 angstroms. In another embodiment, a chemical mechanical polishing process can be optionally performed to remove the excess material of the fin 130 outside of the trench 124. In an embodiment, the fin 130 is disposed in the recess 112 of the buffer layer 110 while the isolation structure 122 is formed on the top surface of the buffer layer 110, and thus a thickness of the buffer layer 110 under the fin 130 is less than a thickness of the buffer layer 110 under the isolation structures 122.

Referring to FIG. 1E, a gate 140 is formed across the fin 130. The gate 140 includes a silicon-containing material or metal. The silicon-containing material includes polysilicon, amorphous silicon or a combination thereof. The metal includes a work function metal (such as TiAl, TiN or the like) and a low-resistance metal (such as Cu, Al, W or the like). In an embodiment, the gate 140 extends in a second direction different from the first direction. For example, the second direction is perpendicular to the first direction. In another embodiment, a gate dielectric layer is disposed between the gate and the fin 130. The gate dielectric layer includes a high-dielectric constant (high-k) layer. The high-k layer includes a dielectric material having a dielectric constant greater than about 7 or even greater than about 10, such as metal oxide. In an embodiment, source/drain regions (not shown) are disposed at two sides of the fin 130. The source/drain regions include epitaxial layers (such as SiGe, SiP or SiC layers) and doped regions (such as N-type or P-type doped regions).

In summary, in the present invention, the recess is formed in the buffer layer without penetrating the buffer layer, and thus the buffer layer is simultaneously disposed below the isolation structures and the fins between the isolation structures. Therefore, the fin may be grown in the recess of the buffer layer rather than directly grown on the substrate, and the fin may be grown more easily. In addition, since the buffer layer is formed before forming the fins, the buffer layer may have a good uniformity. Accordingly, the method of forming the FinFET has simplified steps and reduced cost, and the FinFET may have an improved performance.

The present invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be defined by the following claims.

Claims

What is claimed is:

1. A fin-type field effect transistor (FinFET), comprising:

a substrate;

a buffer layer over the substrate, including a recess without penetrating the buffer layer;

an insulating layer over the buffer layer, including a plurality of isolation structures and a trench between the isolation structures;

a fin disposed in the recess of the buffer layer and the trench of the insulating layer; and

a gate, across the fin,

wherein a bottom surface of the gate is in contact with top surfaces of the isolation structures, and separated from the buffer layer by the isolation structures.

2. The FinFET of claim 1, wherein a thickness of the buffer layer under the fin is less than a thickness of the buffer layer under the isolation structures.

3. The FinFET of claim 1, wherein a depth of the recess ranges from 30 angstroms to 50 angstroms.

4. The FinFET of claim 1, wherein a thickness of the buffer layer ranges from 60 angstroms to 100 angstroms.

5. The FinFET of claim 1, wherein the recess is aligned with and has a same size of the trench.

6. The FinFET of claim 1, wherein the fin protrudes from the insulating layer.

7. The FinFET of claim 1, wherein a material of the buffer layer is different from a material of the fin and a material of the substrate.

8. The FinFET of claim 1, wherein a material of the buffer layer comprises at least one of Ge, SiGe, InP, InAs, GaSb, GaAs, AlSb, GaAsP, InGaAs, InGaP, InGaSb, InAlAs, AlGaSb, AlAsSb or a combination thereof.

9. The FinFET of claim 1, wherein the buffer layer comprises multiple layers.

10. A method of forming a FinFET, comprising:

forming a buffer layer over a substrate;

forming an insulating layer over the buffer layer;

forming an opening in the insulating layer and the buffer layer without penetrating the buffer layer;

forming a fin in the opening; and

forming a gate across the fin,

wherein a bottom surface of the gate is formed to be in contact with a top surface of the insulating layer, and separated from the buffer layer by the insulating layer.

11. The method of claim 10, wherein the step of forming an opening comprises:

removing a portion of the insulating layer, so as to form a trench penetrating the insulating layer; and

by using the insulating layer having the trench as a mask, removing a portion of the buffer layer, so as to form a recess without penetrating the buffer layer.

12. The method of claim 11, wherein the recess is aligned with and has a same size of the trench.

13. The method of claim 10, wherein the step of removing a portion of the buffer layer is performed by using a mixed gas containing a stop etching gas and an etching gas, the stop etching gas comprises carbon (C) and fluoride (F), and the etching gas comprises silicon (Si) and chloride (Cl).

14. The method of claim 13, wherein the stop etching gas is selected from a group consisting of CF4, C2F6, C3F8, CHF3, CH2F2 and CBrF3.

15. The method of claim 13, wherein the etching gas is selected from a group consisting of SiCl4, SiH2Cl2 and SiHCl3.

16. The method of claim 13, wherein the mixed gas further comprises a rare gas selected from a group consisting of He, Ne, Ar, Kr, Xe and Rn.

17. The method of claim 10, wherein the step of forming a fin comprises epitaxially growing the fin on the buffer layer exposed by the opening.

18. The method of claim 10, wherein the fin is formed as protruding from the insulating layer.

19. The method of claim 10, wherein a material of the buffer layer is different from a material of the fin and a material of the substrate.

20. The method of claim 10, wherein a material of the buffer layer comprises a least one of Ge, SiGe, InP, InAs, GaSb, GaAs, AlSb, GaAsP, InGaAs, InGaP, InGaSb, InAlAs, AlGaSb, AlAsSb or a combination thereof.

Resources

Images & Drawings included:

Fig. 01 - Fin-type field effect transistor and method of forming the same
Fig. 01
Fig. 02 - Fin-type field effect transistor and method of forming the same
Fig. 02
Fig. 03 - Fin-type field effect transistor and method of forming the same
Fig. 03
Fig. 04 - Fin-type field effect transistor and method of forming the same
Fig. 04

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