Method and apparatus for generating twenty-five percent duty cycle clock

Description

BACKGROUND OF THE DISCLOSURE

Field of the Disclosure

The present disclosure generally relates to generation of quadrature clock and more particularly to methods and circuits for generating quadrature clocks.

Description of Related Art

Quadrature clocks are widely used in radio transceivers. In some applications, a quadrature clock with a 25% duty cycle is needed. FIG. 1A depicts a conventional clock generator circuit. As depicted in FIG. 1A, a prior art 25% duty quadrature clock generator 100 comprises: a divide-by-two circuit 101 configured to receive a two-phase clock comprising a first phase CK and a second phase CB and output a four-phase, 50% duty clock comprising a first phase X₁, a second phase X₂, a third phase X₃, and a fourth phase X₄; and a 50% to 25% duty conversion circuit 102 comprising four AND gates 102A, 102B, 102C, and 102D configured to receive the four-phase, 50% duty clock and output a four-phase, 25% duty clock comprising a first phase Y₁, a second phase Y₂, a third phase Y₃, and a fourth phase Y₄. Let a fundamental period of the two-phase clock be T. The fundamental period of the four-phase, 50% duty clock will be 2T, and there is a timing difference of T/2 between X₁ (X₂, X₃, X₄) and X₂ (X₃, X₄, X₁), where an edge of X₁ (X₂, X₃, X₄) arrives earlier than a subsequent edge of X₂ (X₃, X₄, X₁) by a time of T/2. The divide-by-two circuit 101 comprises a first data latch 101A and a second data latch 101B configured in a ring topology with a negative feedback, wherein each of the two data latches 101A and 101B has two input pins labeled by “D₊,” and “D₋,” two output pins labeled by “Q₊” and “Q₋,” and an enabling pin labeled by “E.” The first (second) data latch 101A (101B) receives X₄ (X₁) and X₂ (X₃) via its two input pins “D₊” and “D₋,” respectively, outputs X₁ (X₂) and X₃ (X₄) via its two output pin pins “Q₊” and “Q₋,” respectively, and works in accordance with CK (CB) via its enabling pin “E.” AND gate 102A (102B, 102C, 102D) receives X₁ (X₂, X₃, X₄) and X₄ (X₁, X₂, X₃) and output Y₁ (Y₂, Y₃, Y₄). Since there is a timing difference of T/2 between X₁ (X₂, X₃, X₄) and X₄ (X₁, X₂, X₃) there is an overlap of T/2 in timing where X₁ (X₂, X₃, X₄) and X₄ (X₁, X₂, X₃) are both high and therefore Y₁ (Y₂, Y₃, Y₄) is high. As a result, X₁, X₂, X₃, and X₄ all have 25% duty cycle and are evenly spaced in time.

A schematic diagram of a data latch 120 that can be instantiated to embody the two data latches 101A and 101B is shown in FIG. 1B. Data latch 120 comprises a differential pair 121, a cross-coupling pair 122, and a switch 123. Throughout this disclosure, “V_DD” denotes a power supply node. The differential pair 121 comprises a first NMOS (n-channel metal oxide semiconductor) transistor 121A and a second NMOS transistor 121B configured to receive a differential input signal received from the two input pins “D₊” and “D₋,” and output a differential output signal to the two output pins “Q₊” and “Q₋.” The cross-coupling pair 122 comprises a first PMOS (p-channel metal oxide semiconductor) transistor 122A and a second PMOS transistor 122B, wherein PMOS transistor 122A is configured to receive the voltage at pin “Q₊” via its gate and regenerate the voltage at pin Q₋” via its drain, while PMOS transistor 122B is configured to receive the voltage at pin “Q₋” via its gate and regenerate the voltage at pin “Q₊” via its drain. The switch 123 comprises a third NMOS transistor 123A, controlled by a control voltage received from the enabling pin “E” and configured to provide a discharge path for the differential pair 121 when enabled. For brevity, hereafter the voltages at pins “D₊,” “D₋,” “Q₊,” “Q₋,” and “E” are simply referred to as “D₊,” “D₋,” “Q₊,” “Q₋,” and “E,” respectively. When “E” is high (low), the switch 123 is switched on (off) to allow (disallow) the differential pair 121 to update a state of the cross-coupling pair 122; as such, the data latch 120 is in an active (a frozen) state and the state of the cross-coupling pair 122 is updated (latched).

There is an issue with the data latch 120. When “Q₊” is low, “Q₋” is high, “D₊” is high, and “D₋” is low, “Q₋” and “Q₊” should toggle in response to a low-to-high transition of “E.” The toggling occurs in two stages: an early stage, followed by a late stage. During the early stage of the toggling where “Q₋” has not fallen sufficiently low to turn on PMOS transistor 122B, “Q₊” stays at low since both NMOS transistor 121B and PMOS transistor 122B are in an off state, while “Q₋” is being pulled down by NMOS transistor 121A in the presence of contention from PMOS transistor 122A that strives to hold “Q₋” at high. During the late stage of the toggling where “Q₋” has fallen sufficiently low to turn on PMOS transistor 122B, “Q₋” continues to fall, while “Q₊” is being pulled up by PMOS transistor 122B. Using a large width-to-length ratio for PMOS transistors 122A and 122B will slow down the early stage of the toggling since the contention from PMOS transistor 122A will be strong; using a small width-to-length ratio for PMOS transistors 122A and 122B will slow down the late stage of the toggling since the pull-up of PMOS transistor 122B will be weak. Therefore, the speed of the toggling is hindered, one way or the other.

There is also an issue with the 25% duty quadrature clock generator 100 that hinders a high-speed application. AND gate is usually embodied by a NAND gate followed by an inverter. NAND gate is generally a slow circuit and a heavy load to its preceding circuit. Therefore, the 50% to 25% duty conversion circuit 102 is not only slow itself but also slows down data latches 101A and 101B.

What is desired is a method to speed up both the divide-by-two circuit and the 50% to 25% duty conversion circuit.

SUMMARY OF THE DISCLOSURE

In an embodiment, a clock generator comprises a divide-by-two circuit configured to receive an input clock and output an interim clock, and a duty converter configured to receive the interim clock and output an output clock, wherein: the divide-by-two circuit comprises eight inverters; the duty converter comprises four buffers; a first, a second, a third, and a fourth inverter among said eight inverters are configured in a ring topology to output a first, a second, a third, and a fourth phase of the interim clock, respectively; the second and the fourth inverter are enabled during a first phase of the input clock; the first and the third inverter are enabled during a second phase of the input clock; a fifth and a sixth inverter among said eight inverters are configured in a cross-coupling topology to enforce a complementary relation between the second and the fourth phase of the interim clock; a seventh and an eighth inverter of said eight inverters are configured in a cross-coupling topology to enforce a complementary relation between the first and the third phase of the interim clock; a first, a second, a third, and a fourth buffer among said four buffers are configured to receive the first, the second, the third, and the fourth phase of the interim clock and output a first, a second, a third, and a fourth phase of the output clock, respectively; the first and the third buffers are enabled during the first phase of the input clock or reset otherwise; and the second and the fourth buffer are enabled during the second phase of the input clock or reset otherwise.

In an embodiment, a method comprises: receiving an input clock; cascading a first inverter, a second inverter, a third inverter, and a fourth inverter in a ring topology to output a first phase, a second phase, a third phase, and a fourth phase of an interim clock; enabling the second inverter and the fourth inverter during a first phase of the input clock and enforcing a complementary relation between the second phase and the fourth phase of the interim clock by using a fifth inverter and a sixth inverter configured in a cross-coupling topology; enabling the first inverter and the third inverter during a second phase of the input clock and enforcing a complementary relation between the first phase and the third phase of the interim clock by using a seventh inverter and an eighth inverter configured in a cross-coupling topology; and incorporating a first buffer, a second buffer, a third buffer, and a fourth buffer to receive the first phase, the second phase, the third phase, and the fourth phase of the interim clock and output a first phase, a second phase, a third phase, and a fourth phase of an output clock, respectively, wherein the first buffer and the third buffers are enabled during the first phase of the input clock or reset otherwise, while the second buffer and the fourth buffer are enabled during the second phase of the input clock or reset otherwise.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a schematic diagram of a prior art clock generator.

FIG. 1B shows a schematic diagram of a data latch.

FIG. 2A shows a schematic diagram of a clock generator in accordance with an embodiment of the present disclosure.

FIG. 2B shows a schematic diagram of an inverter.

FIG. 2C shows a schematic diagram of a return-to-zero buffer.

FIG. 3 shows a simulation result of the clock generator of FIG. 2A.

FIG. 4 shows a flow diagram of a method in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THIS DISCLOSURE

The present disclosure is directed to clock generation. While the specification describes several example embodiments of the disclosure considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure.

Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “circuit node,” “power node,” “ground node,” “inverter,” “voltage,” “current,” “CMOS (complementary metal oxide semiconductor),” “PMOS (P-channel metal oxide semiconductor) transistor,” “NMOS (N-channel metal oxide semiconductor) transistor,” “phase,” “clock,” “signal,” and “loading.” Terms and basic concepts like these are apparent to those of ordinary skill in the art and thus will not be explained in detail here. Those of ordinary skill in the art can also recognize symbols of PMOS transistor and NMOS transistor, and identify the “source,” the “gate,” and the “drain” terminals thereof.

This disclosure is presented in an engineering sense, instead of a rigorous mathematical sense. For instance, “A is equal to B” means “a difference between A and B is smaller than an engineering tolerance.

Throughout this disclosure, a ground node is used as a reference node of zero voltage (0V) electrical potential. A power supply node is denoted by “V_DD.” A clock is a voltage signal that cyclically toggles back and forth between a low level (e.g. 0V) and a high level (e.g., the electrical potential at the power supply node “V_DD,” or V_DD for short). By way of example but not limitation, a 28 nm CMOS (complementary metal oxide semiconductor) process is used for circuit fabrication, and V_DD is 1.1V throughout this disclosure.

A schematic diagram of a clock generator 200 in accordance with an embodiment of the present disclosure is depicted in FIG. 2A. Clock generator 200 comprises a divide-by-two circuit 210 configured to receive an input clock (which is a two-phase clock comprising a first phase C₊ and a second phase C₋) and output an interim clock (which is a four-phase clock comprising a first phase U₁, a second phase U₂, a third phase U₃, and a fourth phase U₄) and a duty converter 220 configured to receive the interim clock and output an output clock (which is a four-phase clock comprising a first phase V₁, a second phase V₂, a third phase V₃, and a fourth phase V₄). The divide-by-two circuit 210 comprises eight inverters including a first inverter 211, a second inverter 212, a third inverter 213, a fourth inverter 214, a fifth inverter 215, a sixth inverter 216, a seventh inverter 217, and an eighth inverter 218. The duty converter 220 comprises four return-to-zero (hereafter RZ for short) buffers including a first RZ buffer 221, a second RZ buffer 222, a third RZ buffer 223, and a fourth RZ buffer 224. The first, the second, the third, and the fourth inverter (i.e. inverters 211, 212, 213, and 214) are cascaded in a ring topology to output the first, the second, the third, and the fourth phases of the interim clock (i.e. U₁, U₂, U₃, and U₄), respectively. The second and the fourth inverters (i.e. inverters 212 and 214) are enabled during a first phase of the input clock wherein C₊ is high and C₋ is low, while the first and the third inverters (i.e. inverters 211 and 213) are enabled during a second phase of the input clock wherein C₊ is low and C₋ is high. The fifth and the sixth inverters (i.e. inverters 215 and 216) are configured in a cross-coupling topology to enforce a complementary relation between the second and the fourth phase of the interim clock (i.e. U₂ and U₄). The seventh and the eighth inverters (i.e. inverters 217 and 218) are configured in a cross-coupling topology to enforce a complementary relation between the first and the third phase of the interim clock (i.e. U₁ and U₃).

The first, the second, the third, and the fourth RZ buffer 221, 222, 223, and 224 are configured to receive the first, the second, the third, and the fourth phase of the interim clock (i.e. U₁, U₂, U₃, and U₄) and output the first, the second, the third, and the fourth phase of the output clock (i.e. V₁, V₂, V₃, and V₄), respectively. The first and the third RZ buffer 221 and 223 are controlled by the first phase of the input clock C₊, and the second and the fourth RZ buffer 222 and 224 are controlled by the second phase of the input clock C₋. Each inverter of said eight inverters 211˜218 has an input pin labeled by “1,” an output pin labeled by “0,” a power pin labeled by “P,” and a ground pin labeled by “G.” Each inverter receives an input signal from its input pin “I” and output an output signal via its output pin “O.” Each inverter is enabled when its power pin “P” is connected to V_DD and its ground pin “G” is connected to ground. Clock generator further comprises four NMOS transistors MN1, MN2, MN3, and MN4 and four PMOS transistors MP1, MP2, MP3, and MP4. NMOS transistor MN1 (MN3) and PMOS transistor MP1 (MP3) are controlled by C₋ and C₊, respectively, and jointly embody the function of enabling the first (third) inverter 211 (213) by connecting its power pin “P” to V_DD and connecting its ground pin “G” to ground during the second phase of the input clock wherein C₊ is low and C₋ is high. NMOS transistor MN2 (MN4) and PMOS transistor MP2 (MP4) are controlled by C₊ and C₋, respectively, and jointly embody the function of enabling the second (fourth) inverter 212 (214) by connecting its power pin “P” to V_DD and connecting its ground pin “G” to ground during the first phase of the input clock wherein C₊ is high and C₋ is low. Each of the four RZ buffers 221, 222, 223, and 224 has an input pin labeled by “1,” and output pin labeled by “0,” and a control pin labeled by “C.” RZ buffer 221 (222, 223, 224) receives U₁ (U₂, U₃, U₄) via its input pin “I” and output V₁ (V₂, V₃, V₄) via its output pin “O” in accordance with a control by C₊ (C₋, C₊, C₋) via its control pin “C.”

In an alternative embodiment that is not explicitly shown in FIG. 2A but would be clear to those of ordinary skill in the art: NMOS transistor MN3 is removed and the ground pin “G” of inverter 213 is tied to the ground pin “G” of inverter 211; PMOS transistor MP3 is removed and the power pin “P” of inverter 213 is tied to the power pin “P” of inverter 211; NMOS transistor MN4 is removed and the ground pin “G” of inverter 214 is tied to the ground pin “G” of inverter 212; PMOS transistor MP4 is removed and the power pin “P” of inverter 214 is tied to the power pin “P” of inverter 212.

A schematic diagram of an inverter 230 that can be instantiated to embody the eight inverters 211˜218 is shown in FIG. 2B. Inverter 230 comprises: a NMOS transistor 230A and a PMOS transistor 230B. The source, the gate, and the drain of NMOS transistor 230A connect to the ground pin “G,”, the input pin “I,” and the output pin “O,” respectively; the source, the gate, and the drain of PMOS transistor 230B connect to the power pin “P,” the input pin “I,” and the output pin “O,” respectively. In an embodiment, by way of example but not limitation: W/L (which stands for width/length) of each of the four NMOS transistors MN1˜MN4 is 8.5 □m/30 nm; W/L of each of the four PMOS transistors MP1˜MP4 is 10.92□m/30 nm; when instantiating inverter 230 to embody inverters 211, 212, 213, and 214, W/L of NMOS transistor 230A is 3 □m/30 nm, and W/L of PMOS transistor 230B is 3.9 □m/30 nm; and when instantiating inverters 230 to embody inverters 215, 216, 217, and 218, W/L of NMOS transistor 230A is 1.8 □m/30 nm, and W/L of PMOS transistor 230B is 2.34 □m/30 nm. In any case, inverters 211˜214 are appreciably stronger than inverters 215˜218. Here, a strength of an inverter refers to its current-driving capability, and an inverter comprising MOS transistors of a larger width-to-length ratio is stronger than an inverter comprising MOS transistors of a smaller width-to-length ratio. By way of example but not limitation, inverters 211˜214 are approximately 67% stronger than inverters 215˜218.

A schematic diagram of a RZ buffer 240 that can be instantiated to embody RZ buffers 221, 222, 223, and 224 is shown in FIG. 2C. RZ buffer 240 comprises: a return-to-one inverter 241 configured to receive an input signal from the input pin “I” and output an inter-stage signal V_X to an inter-stage node 249 in accordance with a control signal received via the control pin “C”; and an inverter 242 configured to receive the inter-stage signal V_X and output the output signal to the output pin “O.” When the control signal at the control pin “C” is low, the RZ buffer 240 is reset; when the control signal at the control pin “C” is high, the RZ buffer 240 is enabled. The return-to-one inverter 241 comprises: a first NMOS transistor 241A, a second NMOS transistor 241B, and a PMOS transistor 241C. The source, the gate, and the drain of NMOS transistor 241A connect to ground, the input pin “I,” and an internal node 248, respectively. The source, the gate, and the drain of NMOS transistor 241B connect to the internal node 248, the control pin “C,” and the inter-stage node 249, respectively. The source, the gate, and the drain of PMOS transistor 241C connect to V_DD, the control pin “C,” and the inter-stage node 249, respectively. When the control signal at the control pin “C” is low, the inter-stage signal V_X will be high (i.e. V_DD; “return-to-one”) regardless of the input signal at the input pin “I”; when the control signal at the control pin “C” is high, the intermediate signal V_X will remain high if the input signal at the input pin “I” is low, or be pulled down to ground if the input signal at the input pin “I” is high. Thanks to inverter 242, the output signal at the output pin “O” is an inversion of the inter-stage signal V_X. Therefore, when the control signal at the control pin “C” is low, the output signal at the output pin “O” will be low (i.e. ground; “return-to-zero”) regardless of the input signal at the input pin “I”; when the control signal at the control pin “C” is high, the output signal at the control pin “O” will remain low if the input signal at the input pin “I” is low, or rise to V_DD if the input signal at the input pin “I” is high. In an embodiment, by way of example but not limitation: W/L of NMOS transistor 241A is 6.4 □m/30 nm; W/L of NMOS transistor 241B is 7.2 □m/30 nm; W/L of PMOS transistor 241C is 4.68 □m/30 nm; inverter 230 is instantiated to embody inverter 242 with W/L of NMOS transistor 230A being 4.8 □m/30 nm, and W/L of PMOS transistor 230B being 9.36□m/30 nm.

A simulation result of quadrature clock generator 200 is shown in FIG. 3. Here, a fundamental frequency of the two-phase input clock is 10 GHz. C₊ and C₋ are complementary and have the same period of 100 ps. U₁, U₂, U₃, and U₄ have the same period of 200 ps and the same duty cycle of approximately 50%. A difference in timing between U₁(U₂, U₃, U₄) and U₂ (U₃, U₄, U₁) is 50 ps. V₁, V₂, V₃, and V₄ have the same period of 200 ps and the same duty cycle of approximately 25%. A difference in timing between V₁(V₂, V₃, V₄) and V₂ (V₃, V₄, V₁) is 50 ps. Note that the cross-coupling of inverters 215 and 216 enforces a complementary relation between U₂ and U₄, and the cross-coupling of inverters 217 and 218 enforces a complementary relation between U₁ and U₃, as clearly shown in FIG. 3.

Divide-by-two circuit 210 is by nature faster than divide-by-two circuit 101 of FIG. 1A. For any of the four phases U₁, U₂, U₃, and U₄, there will always be a PMOS transistor working to pull up all along the process of a low-to-high toggling, and a NMOS transistor working to pull down all along the process of a high-to-low toggling. RZ buffer 240 is by nature faster than AND gate, as there are fewer transistors and lighter loading. Therefore, clock generator 200 is by nature faster than clock generator 100 of FIG. 1A.

As depicted in a flow diagram shown in FIG. 4, a method in accordance with an embodiment of the present disclosure includes the following steps: (step 410) receiving an input clock; (step 420) cascading a first inverter, a second inverter, a third inverter, and a fourth inverter in a ring topology to output a first phase, a second phase, a third phase, and a fourth phase of an interim clock; (step 430) enabling the second inverter and the fourth inverter during a first phase of the input clock and enforcing a complementary relation between the second phase and the fourth phase of the interim clock by using a fifth inverter and a sixth inverter configured in a cross-coupling topology; (step 440) enabling the first inverter and the third inverter during a second phase of the input clock and enforcing a complementary relation between the first phase and the third phase of the interim clock by using a seventh inverter and an eighth inverter configured in a cross-coupling topology; and (step 450) incorporating a first buffer, a second buffer, a third buffer, and a fourth buffer to receive the first phase, the second phase, the third phase, and the fourth phase of the interim clock and output a first phase, a second phase, a third phase, and a fourth phase of an output clock, respectively, wherein the first buffer and the third buffers are enabled during the first phase of the input clock or reset otherwise, while the second buffer and the fourth buffer are enabled during the second phase of the input clock or reset otherwise.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.