Power supply circuit capable of setting turn-off point

Description

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority of Taiwan Application No. 108118512 filed on 2019 May 29.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to a power supply circuit, and more particularly, to a power supply circuit capable of setting turn-off point.

2. Description of the Prior Art

Power supply circuits are commonly used to convert alternative-current (AC) power into direct-current (DC) voltages for driving various components in a computer system which may have different operating voltages.

Although a traditional power supply circuit is capable of working properly if the input voltage is anywhere between 100-240V, an input range between 90-264V (with ±10% buffer) is usually adopted in order to accommodate different input voltage standards indifferent countries. Most prior art power supply circuits are designed to shut down their operations when the input voltage drops to 80V, and can thus be turned off prematurely when the mains electricity somehow fluctuates. Under such circumstance, the user needs to replug the power supply circuit to reboot, which takes time and influences the operation of the computer system.

SUMMARY OF THE INVENTION

The present invention provides a power supply circuit capable of setting turn-off point and including a main transformer, a pulse width modulation integrated circuit, an input voltage detecting circuit, a detecting voltage adjusting circuit, and a driving voltage supply circuit. The main transformer includes a primary side for receiving an input voltage and a secondary side for providing an output voltage. The pulse width modulation integrated circuit is configured to activate a driving voltage according to a first detecting voltage and a second detecting voltage. The input voltage detecting circuit is disposed on the primary side of the main transformer and configured to provide a first voltage and a second voltage associated with the input voltage. The detecting voltage adjusting circuit is disposed on the primary side of the main transformer and configured to provide the first detecting voltage and the second detecting voltage according to the first voltage and the second voltage. The driving voltage supply circuit is configured to provide the driving voltage for operating the pulse width modulation integrated circuit.

The present invention also provides a power supply circuit capable of setting turn-off point and including a main transformer, a pulse width modulation integrated circuit, an input voltage detecting circuit, a detecting voltage adjusting circuit, and a driving voltage supply circuit. The main transformer includes a primary side for receiving an input voltage and a secondary side for providing an output voltage. The pulse width modulation integrated circuit is configured to activate a driving voltage according to a first detecting voltage and a second detecting voltage. The input voltage detecting circuit is disposed on the primary side of the main transformer and includes an input capacitor coupled between the input voltage and a ground level; a first diode, a first resistor and a second resistor coupled in series between the input voltage and the ground level for providing a first voltage associated with the input voltage between the first resistor and the second resistor; and a second diode, a third resistor and a fourth resistor coupled in series between the input voltage and the ground level, and coupled in parallel with the first diode, the first resistor and the second resistor for providing a second voltage associated with the input voltage between the third resistor and the fourth resistor. The detecting voltage adjusting circuit is disposed on the primary side of the main transformer and configured to provide the first detecting voltage and the second detecting voltage according to the first voltage and the second voltage, and includes a third diode, a fourth diode, a fifth diode, a Zener diode, a first switch, a second switch, and a third switch. The third diode includes an anode coupled between the first resistor and the second resistor and a cathode. The fourth diode includes an anode coupled between the third resistor and the fourth resistor and a cathode. The fifth diode includes an anode coupled to the pulse width modulation circuit and a cathode. The Zener diode includes an anode coupled to the ground level and a cathode. The first switch includes a first end coupled to the cathode of the fourth diode via the fifth resistor, a second end coupled to the ground level, and a control end. The a second switch includes a first end coupled to the cathode of the fifth diode, a second end coupled to the ground level, and a control end coupled between the first end of the first switch and the fifth resistor. The third switch includes a first end coupled to the cathode of the third diode, a second end coupled to the control end of the first switch, and a control end coupled to the cathode of the Zener diode. The driving voltage supply circuit is configured to provide the driving voltage for operating the pulse width modulation integrated circuit.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional diagram illustrating a power supply circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an implementation of the power supply circuit according to an embodiment of the present invention.

FIG. 3 is a state diagram illustrating the operation of the power supply circuit according to an embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 1 is a functional diagram illustrating a power supply circuit 100 according to an embodiment of the present invention. The power supply circuit 100 includes a main transformer TR1, a pulse width modulation integrated circuit (PWM IC) 10, an input voltage detecting circuit 20, a detecting voltage adjusting circuit 30, and a driving voltage supply circuit 40. The power supply circuit 100 is configured to convert an input voltage V_IN into an output voltage V_OUT for driving a load 50.

FIG. 2 is a diagram illustrating an implementation of the power supply circuit 100 according to an embodiment of the present invention. The main transformer TR1 includes a primary winding (NP1 turns) coupled to the input voltage V_IN and a secondary winding (NS1 turns) coupled to the load 50, wherein I_IN represents the input current flowing through the primary side of the main transformer TR1, and I_OUT represents the output current flowing through the secondary side of the main transformer TR1. Base on Faraday's law of induction, the operation of an ideal transformer may be described by an equation of V_IN/V_OUT=I_OUT/I_IN=NP1/NS1. In step-up applications, the number of turns in the secondary winding NS1 is larger than the number of turns in the primary winding NP1. In step-down applications, the number of turns in the primary winding NP1 is larger than the number of turns in the secondary winding NS1. However, the number of turns in the primary or second winding does not limit the scope of the present invention.

The pulse width modulation integrated circuit 10 includes 3 pins P1˜P3, wherein Pin P1 is used to receive a detecting voltage V_SENSE1/Pin P2 is used to receive a detecting voltage V_SENSE2, and Pin P3 is coupled to the driving voltage supply circuit 40 for receiving a driving voltage V_CC required to operate the pulse width modulation integrated circuit 10. The pulse width modulation integrated circuit 10 is configured to activate the driving voltage V_CC according to detecting voltages V_SENSE1 and V_SENSE2. When in operation, the pulse width modulation integrated circuit 10 may regulate the input current I_IN flowing through the primary side of the main transformer TR1, thereby allowing the power supply circuit 100 to operate in different modes.

The input voltage detecting circuit 20 is disposed on the primary side of the main transformer TR1 and includes an input capacitor C_IN, resistors R1˜R4, and diodes D1˜D2. The resistor R1, the resistor R2 and the diode D1 is coupled in series, thereby forming a voltage-dividing circuit between the input voltage V_IN and a ground level GND. The resistor R3, the resistor R4 and the diode D2 is coupled in series, thereby forming a voltage-dividing circuit between the input voltage V_IN and the ground level GND. More specifically, the voltage V1 established between the resistors R1 and R2 and the voltage V2 established between the resistors R3 and R4 may reflect the level of the input voltage V_IN.

The detecting voltage adjusting circuit 30 includes switches Q1˜Q3, a resistor R5, a Zener diode ZD, and diodes D3-D5. The switch Q1 includes a first end coupled between the resistors R3 and R4 in the input voltage detecting circuit 20 via the resistor R5 and the diode D4, a second end coupled to the ground level GND, and a control end coupled to Pin P1 of the pulse width modulation integrated circuit 10 for receiving the detecting voltage V_SENSE1. The switch Q2 includes a first end coupled to the driving voltage supply circuit 40 via the diode D5, a second end coupled to the ground level GND, and a control end coupled to the first end of the switch Q1 and Pin P2 of the pulse width modulation integrated circuit 10. The switch Q3 includes a first end coupled between the resistors R1 and R2 in the input voltage detecting circuit 20 via the diode D3, a second end coupled to the control end of the switch Q1, and a control end coupled to the ground level GND via the Zener diode ZD. The detecting voltage adjusting circuit 30 is configured to provide the detecting voltages V_SENSE1 and V_SENSE2 according to the voltages V1 and V2 provided by the input voltage detecting circuit 20, and its operation will be described in more details in subsequent paragraphs.

The driving voltage supply circuit 40 includes a supply capacitor C_VCC, an auxiliary transformer TR2, an auxiliary capacitor C_AUX, and an auxiliary diode D_AUX. The auxiliary transformer TR2 includes a primary winding (NP2 turns) and a secondary winding (NS2 turns). The primary winding of the auxiliary transformer TR2 is coupled to the secondary side of the main transformer TR1 for charging the auxiliary capacitor C_AUX when the output voltage V_OUT is not zero, thereby establishing the driving voltage V_CC on the auxiliary capacitor C_AUX for operating the pulse width modulation circuit 10.

In an embodiment of the present invention, each of the switches Q1 and Q2 may be a metal-oxide-semiconductor field-effect transistor (MOSFET) or another device with similar function. The switch Q3 may be a bipolar junction transistor (BJT) or another device with similar function. However, the types of the switches Q1˜Q3 do not limit the scope of the present invention.

In an embodiment of the present invention, the value of the input capacitor C_IN may be 120 μF, the value of the auxiliary capacitor C_AUX may be 47 μF, the value of the supply capacitor C_VCC may be 47 μF, the value of the resistor R1 may be 300KΩ, the value of the resistor R2 may be 99KΩ, the value of the resistor R3 may be 200KΩ, the value of the resistor R4 may be 100KΩ, and the value of the resistor R5 may be 10KΩ. However, the values of the above-mentioned devices do not limit the scope of the present invention.

FIG. 3 is a state diagram illustrating the operation of the power supply circuit 100 according to an embodiment of the present invention. For illustrative purpose, FIG. 3 depicts the states S1˜S9 associated with the present invention. However, the operation of the power supply circuit 100 may include other states.

In state S1, the power supply circuit 100 is turned on. For illustrative purpose, it is assumed that the input voltage V_IN of the power supply circuit 100 is 90V after turning on.

In state S2, the input capacitor C_IN in the input voltage detecting circuit 20 is charged by the input voltage V_IN. Once the input capacitor C_IN is fully charged, the voltages V1 and V2 (such as 20V) may be established across the resistors R2 and R4, wherein the forward-biased diode D3 is conducting and the reverse-biased Zener diode ZD provides a break-down voltage (such as 15V) which thus turns on the switch Q3. Under such circumstance, the switch Q1 is turned on when its first end and its control end are pulled to a high voltage level, and the switch Q2 is turned off when its control end is pulled downed to a low voltage level by the conducting switch Q1. Meanwhile, the detecting voltage V_SENSE1 has a high voltage level, and the detecting voltage V_SENSE2 has a low voltage level.

In state S3, the auxiliary transformer TR2 of the driving voltage supply circuit 40 is used to charge the auxiliary capacitor C_AUX, thereby establishing the driving voltage V_CC on the supply capacitor C_VCC for operating the pulse width modulation circuit 10.

In state S4, when receiving the detecting voltage V_SENSE1 having a high voltage level at its Pin P1 and receiving the detecting voltage V_SENSE2 having a low voltage level at its Pin P2, the pulse width modulation circuit 10 is configured to activate the driving voltage V_CC provided by the driving voltage supply circuit 40 and starts its operation.

In state S5, after the pulse width modulation circuit 10 starts its operation, the power supply circuit 100 also starts its operation, thereby converting the input voltage V_IN into the output voltage V_OUT for driving the load 50.

In state S6, when the input voltage V_IN somehow drops to a value which is insufficient to break down the Zener diode ZD (such as 60V), the switch Q1 is turned off due to insufficient voltage V2, and the switch Q2 is turned on by its control end at a high voltage level. Meanwhile, the detecting voltage V_SENSE1 has a low voltage level, and the detecting voltage V_SENSE2 has a high voltage level.

In state S7, the driving voltage V_CC is pulled down to the ground level GND by the conducting switch Q2.

In state S8, when receiving the detecting voltage V_SENSE1 having a low voltage level at its Pin P1 and receiving the detecting voltage V_SENSE2 having a high voltage level at its Pin P2, the pulse width modulation circuit 10 is configured to shut down its operation.

In state S9, after the pulse width modulation circuit 10 shuts down its operation, the power supply circuit 100 also shuts down its operation.

In the present invention, the power supply circuit 10 provides the flexibility of setting multiple turn-off points. For example, if it is desired for the power supply circuit 10 to shut down at V_IN=60V, the values of the resistors in the voltage detecting circuit 20 may be chosen so that the voltage V1 established across the resistor R2 drops below 15V when V_IN=60V, thereby shutting down the power supply circuit 10 at V_IN=60V.

In conclusion, the present power supply circuit uses the input voltage detecting circuit to monitor the input voltage. The detecting voltage adjusting circuit may adjust the detecting signals when detecting a low input voltage so that the pulse width modulation can deactivate its driving voltage, thereby shutting down the power supply circuit. Therefore, the present power supply circuit 100 is able to shut down flexibly at multiple turn-off points, instead of the prior art single turn-off point which may be prematurely triggered by temporary fluctuations of the mains electricity.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.