10GBASE-T training algorithm
US20090225648A1
2009-09-10
12/284,959
2008-09-26
Abstract:
A method of identifying and correcting each of the changes that may occur with wire pairs between the transmitter and receiver in Ethernet 10 GBase-T cabling is provided. The method includes four wire pairs A, B, C and D, a polarity swapping and scrambler state machine that determine if the chosen pair matches the requirements for pair A. A slave Tap state machine generates a rule for correct B, C and D patterns based on a pair chosen as pair A. The cables B, C and D are iteratively swapped to rearrange the pair mapping into the polarity swap state machine, and a deskew state machine identifies the latency difference between the different pairs. If the rules are not satisfied, a new pair A is designated at the swapping state machine and the process is repeated until the rules are satisfied.
Inventors:
- PRAVEEN GOPALAPURAM 4 🇺🇸 ROSEVILLE, CA, United States
- Manl Kumaran 1 🇺🇸 Milpitas, CA, United States
- Tamleigh Rose 1 🇺🇸 Sacramento, CA, United States
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Classification:
H04L47/6245 » CPC main
Traffic control in data switching networks; Queue scheduling characterised by scheduling criteria Modifications to standard FIFO or LIFO
G06F1/10 » CPC further
Details not covered by groups - and; Generating or distributing clock signals or signals derived directly therefrom Distribution of clock signals, e.g. skew
H03L7/00 » CPC further
Automatic control of frequency or phase; Synchronisation
H04B3/32 » CPC further
Line transmission systems; Details Reducing cross-talk, e.g. by compensating
H04L25/0278 » CPC further
Baseband systems; Details ; arrangements for supplying electrical power along data transmission lines; Arrangements for coupling to transmission lines Arrangements for impedance matching
H04L43/16 » CPC further
Arrangements for monitoring or testing data switching networks Threshold monitoring
H04L47/25 » CPC further
Traffic control in data switching networks; Flow control; Congestion control with rate being modified by the source upon detecting a change of network conditions
H04L47/521 » CPC further
Traffic control in data switching networks; Queue scheduling by attributing bandwidth to queues Static queue service slot or fixed bandwidth allocation
H04L47/6215 » CPC further
Traffic control in data switching networks; Queue scheduling characterised by scheduling criteria Individual queue per QOS, rate or priority
H04L47/722 » CPC further
Traffic control in data switching networks; Admission control; Resource allocation using reservation actions during connection setup at the destination endpoint, e.g. reservation of terminal resources or buffer space
H04J3/0697 » CPC further
Time-division multiplex systems; Details; Synchronising arrangements; Clock or time synchronisation in a network; Clock or time synchronisation in a node; Intranode synchronisation Synchronisation in a packet node
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. application Ser. No. 12/012,725, filed Feb. 1, 2008. application Ser. No. 12/012,725 claims the benefit of U.S. Provisional Patent Application 60/900,180 filed Feb. 7, 2007, which is hereby incorporated by reference.
FIELD OF THE INVENTION
The invention relates generally to electronic communication systems. More particularly, the invention relates to a training pattern to enable recognition of proper wire-pair orientation and correction in electronic communication systems.
BACKGROUND
In Ethernet 10 GBase-T cabling, the data is sent over four pairs of wires. Between the transmitter and receiver, the pairs can be swapped with each other, and the wires in a pair can be swapped. These reconfigurations can result in an inverted signal or the latency of the four pairs can differ. 10 GBASE-T, or IEEE 802.3an-2006, is a standard to provide 10 gigabit/second connections over conventional unshielded or shielded twisted pair cables, over distances up to 100 m. This standard mandates specific training patterns to enable recognition of the proper correction, but does not provide a means to find the proper corrections from all the possibilities. Accordingly, there is a need to develop an algorithm to efficiently search the possible corrections and identify the correct one.
SUMMARY OF THE INVENTION
The current invention is a method of recognizing inverted signals and latency difference in wire pairs between a transmitter and receiver in 10 GBase-T Ethernet cabling due to wire pair mismatch, and correcting the inversion and latency by swapping the cable orders. The method includes providing four pairs of wires, wherein the wires transmit data between the transmitter and the receiver. The wire pairs include pairs A, B, C, and D, whereas the pairs are arranged in a quadrille pattern having two top pairs and two bottom pairs. The method includes providing a pair swapping state machine, where the swapping state machine selects one pair from the top pairs, whereas the selected pair is designated as pair A. A polarity swapping and scrambler lock state machine is provided, where the lock state machine determines if the designated pair A is a correct choice for position A. The lock state machine then determines if the selected pair is inverted. If the selection for A is not correct a next pair of the wires is designated as pair A and the determination is repeated until the requirements for pair A are met and the pair is not inverted. A slave tap state machine is provided, where the tap state machine establishes a rule for a correct B, C, and D pattern based on the determined pair A. The lock state machine is used to designate a second top pair as pair B. The lock state machine is further used to designate a first bottom pair as pair C and to designate a first bottom pair as pair D. A deskew state machine is provided, where the deskew state machine compares all the designations over all possible latencies with the rules generated by the slave tap machine, where if the rules are not satisfied, the cable swap state machine reverses the designated pair C with designated pair D. The deskew state machine is used to re-compare all the designations over all possible latencies with the rules generated by the slave tap machine, where if the rules are not satisfied, a new pair A is designated at the swapping state machine and the process is repeated until the rules are satisfied.
DETAILED DESCRIPTION OF THE INVENTION
Details of various embodiments of the present invention are disclosed in the following appendices:
Appendix A.
Appendix B.
Appendix C.
As one of ordinary skill in the art will appreciate, various changes, substitutions, and alterations could be made or otherwise implemented without departing from the principles of the present invention. Accordingly, the examples and drawings disclosed herein including the appendix are for purposes of illustrating the preferred embodiments of the present invention and are not to be construed as limiting the invention.
Claims
What is claimed:1. A method of recognizing and correcting wire pair swapping between a transmitter and receiver in 10 GBase-T Ethernet cabling comprising:
a. providing four pairs of wires, wherein said wires transmit data between said transmitter and said receiver, whereby said wire pairs comprise A, B, C, and D, whereas said pairs are arranged in a quadrille pattern comprising two top pairs and two bottom pairs;
b. providing a cable swapping state machine, wherein said swapping state machine selects one pair from said top pairs, whereas said selected pair is designated as pair A;
c. providing a polarity swapping and scrambler lock state machine, whereby said lock state machine determines if said designated pair A is a correct choice for position A, whereas said lock state machine determines if said selected pair is inverted, wherein if said selection for A is not correct a next pair of said wires is designated and said determination is repeated until said requirements for pair A are met and said pair is not inverted;
d. providing a slave tap state machine, wherein said tap state machine establishes a rule for a correct B, C, and D pattern based on said determined pair A;
e. using said lock state machine to designate a second said top pair as pair B;
f. using said lock state machine to designate a first said bottom pair as pair C;
g. using said lock state machine to designate a first said bottom pair as pair D;
h. providing a deskew state machine, wherein said deskew state machine compares all said designations over all possible latencies with said rules generated by said slave tap machine, whereby if said rules are not satisfied said cable swap state machine reverses said designated pair C with designated pair D;
i. using said deskew state machine to re-compare all said designations over all possible latencies with said rules generated by said slave tap machine, wherein if said rules are not satisfied a new pair A is selected and steps b through i are repeated until said rules are satisfied.