Dark current reduction for large area photodiodes

Description

PRIORITY INFORMATION

This application claims priority from provisional application Ser. No. 61/081,766 filed Jul. 18, 2008, which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The invention is related to the field of photodiodes, and in particular to dark current reduction for large area photodiodes.

Large area, high performance photodiodes are critical for advances in information technology (polymer optical fiber (POF) networks, multimode optical fibers), for advanced photovoltaic applications and for imaging applications. Because of low cost requirements, high performance semiconductor materials are increasingly deposited on low cost substrates like silicon.

The epitaxial growth of lattice mismatched semiconductor materials for devices generally results in misfit and threading dislocations as well as point defects in the epitaxial grown semiconductor material. The high defect density leads to poor device performance, generally resulting in a large dark current of the device. An example is epitaxial germanium (Ge) on silicon (Si). The lattice mismatch between Si and Ge is 4.2% and Ge devices like photodiodes show large dark current for large area devices (>50 μm diameter). Similarly, large dark current due to lattice mismatch has for example limited device performance for CdZnTe on Si or HgCdTe on Si. Similar results can also be observed for SiGe alloys and III-V semiconductor materials, epitaxially grown on Si.

Several methods have been developed in the past to alleviate the dark current problem. For small size devices, etched mesas combined with high temperature annealing helped reduce threading dislocation densities and point defects, resulting in smaller dark currents. Another approach was the introduction of graded buffer layers, epitaxial layers of materials with smaller lattice mismatch, that reduce the threading dislocation density. While this method can reduce dark current significantly, the several micron thick buffer layer is in many cases undesirable.

Recently it has been shown that micron sized Ge detectors, grown selectively in windows of a dielectric material like silicon oxide or silicon nitride on Si have very low dark currents. Two effects lead to the small dark current. First, the small size allows threading dislocation reduction very similar to the mesa approach described before. Secondly, the growth in the dielectric window improves the sidewall passivation of the detector significantly.

Large detectors of lattice mismatched materials can utilize these effects to reduce dark currents by dividing the large area into smaller sections that are separated by a dielectric material, thereby reducing misfit dislocations due to the mesa effect and improving side wall passivation due to the growth in the dielectric window.

SUMMARY OF THE INVENTION

According to one aspect of the invention, there is provided a method of fabricating a large area photodiode. The method includes providing a substrate where a first contact layer is formed on the substrate. Also, the method includes forming a dielectric layer on the first contact layer and patterning selective areas of the dielectric layer to form a plurality of dielectric windows. Each of the dielectric windows has an open region exposing the first contact layer. Furthermore, the method includes epitaxially growing photodiode material(s) in the dielectric windows, wherein each of the dielectric windows are individualized photodiode structures.

According to another aspect of the invention, there is provided a large area photodiode. The large area photodiode includes a substrate where a first contact layer is formed on the substrate. A dielectric layer is formed on the first contact layer. A plurality of dielectric windows is formed on selective areas of the dielectric layer. Each of the dielectric windows includes an open region exposing the first contact layer and filled with epitaxially grown photodiode material(s), wherein each of the dielectric windows are individualized photodiode structures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating the novel large area photodiode structure;

FIG. 2 is a schematic diagram illustrating the cross sectional view of the large area photodiode illustrated in FIG. 1; and

FIG. 3 is a flowchart illustrating the steps used for fabricating the novel large area photodiode.

DETAILED DESCRIPTION OF THE INVENTION

The invention provides a novel technique for fabrication of photodiode structures by dividing a single large area photodiode device into smaller segments of photodiode elements that are separated by thin dielectric “walls”.

FIG. 1 shows the top view of a novel large photodiode structure 2 in accordance with an exemplary embodiment of the invention. The large photodiode structure 2 includes a plurality of specifically designed dielectric windows 10 etched on a dielectric layer 8. Each of these dielectric windows 10 includes epitaxially grown mismatched photodiode material(s) 4 and acts as a single photodiode element. Also, the dielectric windows 10 are separated by dielectric walls 6 associated with the dielectric layer 8 to provide isolation from adjacent dielectric windows.

This arrangement can reduce the dark current density of the large photodiode structure 2 significantly. The size of the dielectric windows 10 can be chosen so that the performance metric can be optimized. There is a trade-off between window size (determines dark current) and device efficiency since the dielectric walls 6 do not contribute to the device performance and, in the case of photodiodes, light that illuminates the dielectric walls 6 will not contribute to the photocurrent. In the same way, the thickness of the dielectric walls 6 can influence the device efficiency. Thicker walls will result in lower device efficiency.

FIG. 2 shows the cross section view of the of the large photodiode structure 2. This view shows that the large photodiode structure 2 includes a substrate 12 and a bottom contact layer 16 is grown on the substrate. The dielectric layer 8 is grown or deposited on a bottom contact layer 16. Selective areas of the dielectric layer 8 are patterned to form dielectric windows 10 exposing the substrate 12. Mismatched photodiode material(s) are grown in the dielectric windows 10. Dielectric walls 6 provide separation between the dielectric windows 10 so as to provide proper isolation. The thickness of the dielectric walls 6 are based on the efficiency needed. A top contact 14 can be positioned on the top region of the large photodiode structure, however, this is optional.

FIG. 3 is a flowchart demonstrating the fabrication steps used in forming the large area photodiode 2. A substrate is provided where a bottom contact layer is formed on that substrate, as shown in step 22. The substrate includes a crystalline structure that can have II-VI, III-V, or group IV semiconductor materials. The bottom contact layer covers the entire surface of the substrate, and can include materials such as any doped semiconductor material or metal. The doped semiconductor can have a doping concentration of 10¹⁸ or higher. A dielectric layer is formed on the bottom contact layer, as shown in step 24. The dielectric layer covers the entire surface of the bottom contact layer. Selective areas of the dielectric layer are patterned to form a plurality of dielectric windows, as shown in step 26. The dielectric windows are comparable to an opening that exposes the surface of the bottom contact layer. Any conventional known techniques in patterning dielectric layers can be used, such as dry etching. The dielectric windows can be patterned into any shape, however, the shape must be in conformance so as to not be a deterrent in the proper operation of the large area photodiode. The dielectric layer can include semiconductor materials such as silicon dioxide SiO₂, Si₃N₄, SiON, or any dielectric material that allows growth in the dielectric windows can be used. Each of the dielectric windows is separated by an isolation distance from adjacent dielectric windows by the thickness of the dielectric walls. Photodiode material(s) are epitaxially grown in the dielectric windows, as show in step 28. The photodiode material(s) can includes group IV, II-V, and II-VI semiconductor materials but must have a different lattice constant then the substrate. Each of the filled dielectric windows operates as single individualized photodiodes. These fabrication steps form the inventive large area photodiode 2.

A top contact can be grown on the top surface of the large photodiode 2 as shown in step 30, but it is optional. The top contact includes materials similar to that described for the bottom contact layer.

Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.