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Patent application title:

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

Publication number:

US20240079255A1

Publication date:

2024-03-07

Application number:

17/953,285

Filed date:

2022-09-26

✅ Patent granted

Patent number:

US 12,588,462 B2

Grant date:

2026-03-24

PCT filing:

PCT publication:

Examiner:

Bac H Au

Agent:

Winston Hsu

Adjusted expiration:

2044-10-07

Smart Summary: The invention is a semiconductor structure made up of layers on a substrate, including a top metal layer, passivation layers, a pad layer, and a spin-on glass layer. These layers are designed to protect and connect the components within the semiconductor structure. The fabrication method involves carefully assembling these layers to ensure proper functioning of the semiconductor device. 🚀 TL;DR

Abstract:

A semiconductor structure includes a substrate; a top metal layer disposed in a top inter-metal dielectric (IMD) layer on the substrate; a first passivation layer covering the top metal layer and the top IMD layer; a pad layer disposed on the first passivation layer and electrically connected to the top metal layer; a spin-on glass (SOG) layer covering the pad layer and the first passivation layer; and a second passivation layer disposed on the SOG layer.

Inventors:

Ji He Huang 3 🇨🇳 Suzhou City, China

Assignee:

United Semiconductor (Xiamen) Co., Ltd. 75 🇨🇳 Xiamen, China

Applicant:

United Semiconductor (Xiamen) Co., Ltd. 🇨🇳 Xiamen, China

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Classification:

H01L21/67288 » CPC main

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere; Apparatus not specifically provided for elsewhere; Apparatus for monitoring, sorting or marking Monitoring of warpage, curvature, damage, defects or the like

H01L21/76831 » CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof; Manufacture of specific parts of devices defined in group; Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

H01L21/76879 » CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof; Manufacture of specific parts of devices defined in group; Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors; Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

H01L23/5226 » CPC further

Details of semiconductor or other solid state devices; Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body Via connections in a multilevel interconnection structure

H01L23/5286 » CPC further

Details of semiconductor or other solid state devices; Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body layout of the interconnection structure Arrangements of power or ground buses

H01L21/67 IPC

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere

H01L21/02 IPC

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/768 IPC

H01L23/522 IPC

H01L23/528 IPC

H01L23/532 IPC

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of semiconductor technology, in particular to the field of semiconductor back-end-of-the-line (BEOL) technology.

2. Description of the Prior Art

In conventional semiconductor back-end-of-the-line (BEOL) process, after the aluminum pad layer is formed, a plasma-enhanced chemical vapor deposition (PECVD) process is performed to conformally deposit passivation layers, for example, a phosphorous silicate glass (PSG) layer and a silicon nitride layer, on the surface of the aluminum pad layer in a high temperature (over 400 degrees Celsius) environment after.

However, the difference in thermal expansion coefficient between the passivation layer and the aluminum pad layer may lead to a cracking problem of the passivation layer.

SUMMARY OF THE INVENTION

It is one object of the present invention to provide an improved semiconductor structure and fabrication method to solve the above-mentioned deficiencies or shortcomings of the prior art.

One aspect of the invention provides a semiconductor structure including a substrate; a top metal layer disposed in a top inter-metal dielectric (IMD) layer on the substrate; a first passivation layer covering the top metal layer and the top IMD layer; a pad layer disposed on the first passivation layer and electrically connected to the top metal layer; a spin-on glass (SOG) layer covering the pad layer and the first passivation layer; and a second passivation layer disposed on the SOG layer.

According to some embodiments, the pad layer is an aluminum pad layer.

According to some embodiments, the top metal layer is a copper layer.

According to some embodiments, the SOG layer has a flat top surface.

According to some embodiments, a partial top surface of the SOG layer is higher than a top surface of the pad layer.

According to some embodiments, the SOG layer is in direct contact with sidewalls and the top surface of the pad layer.

According to some embodiments, the first passivation layer is a silicon oxide layer.

According to some embodiments, the second passivation layer is a silicon nitride layer.

According to some embodiments, the second passivation layer is in direct contact with the SOG layer.

According to some embodiments, the semiconductor structure further includes a via plug in the first passivation layer to electrically connect the pad layer with the top metal layer; and a liner layer between the via plug and the first passivation layer.

Another aspect of the invention provides a method for fabricating a semiconductor structure. A substrate is provided. A top metal layer is formed in a top inter-metal dielectric (IMD) layer on the substrate. A first passivation layer covering the top metal layer and the top IMD layer is formed. A pad layer is formed on the first passivation layer. The pad layer is electrically connected to the top metal layer. A spin-on glass (SOG) layer is formed to cover the pad layer and the first passivation layer at a temperature lower than 400 degrees Celsius. A second passivation layer is formed on the SOG layer.